1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <stdint.h> 10 #include <stdlib.h> 11 #include <errno.h> 12 13 #include <ethdev_driver.h> 14 #include <rte_bus_pci.h> 15 #include <rte_mbuf.h> 16 #include <rte_common.h> 17 #include <rte_interrupts.h> 18 #include <rte_malloc.h> 19 #include <rte_string_fns.h> 20 #include <rte_rwlock.h> 21 #include <rte_cycles.h> 22 23 #include <mlx5_malloc.h> 24 25 #include "mlx5_rxtx.h" 26 #include "mlx5_rx.h" 27 #include "mlx5_tx.h" 28 #include "mlx5_autoconf.h" 29 30 /** 31 * Get the interface index from device name. 32 * 33 * @param[in] dev 34 * Pointer to Ethernet device. 35 * 36 * @return 37 * Nonzero interface index on success, zero otherwise and rte_errno is set. 38 */ 39 unsigned int 40 mlx5_ifindex(const struct rte_eth_dev *dev) 41 { 42 struct mlx5_priv *priv = dev->data->dev_private; 43 unsigned int ifindex; 44 45 MLX5_ASSERT(priv); 46 MLX5_ASSERT(priv->if_index); 47 if (priv->master && priv->sh->bond.ifindex > 0) 48 ifindex = priv->sh->bond.ifindex; 49 else 50 ifindex = priv->if_index; 51 if (!ifindex) 52 rte_errno = ENXIO; 53 return ifindex; 54 } 55 56 /** 57 * DPDK callback for Ethernet device configuration. 58 * 59 * @param dev 60 * Pointer to Ethernet device structure. 61 * 62 * @return 63 * 0 on success, a negative errno value otherwise and rte_errno is set. 64 */ 65 int 66 mlx5_dev_configure(struct rte_eth_dev *dev) 67 { 68 struct mlx5_priv *priv = dev->data->dev_private; 69 unsigned int rxqs_n = dev->data->nb_rx_queues; 70 unsigned int txqs_n = dev->data->nb_tx_queues; 71 const uint8_t use_app_rss_key = 72 !!dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key; 73 int ret = 0; 74 75 if (use_app_rss_key && 76 (dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key_len != 77 MLX5_RSS_HASH_KEY_LEN)) { 78 DRV_LOG(ERR, "port %u RSS key len must be %s Bytes long", 79 dev->data->port_id, RTE_STR(MLX5_RSS_HASH_KEY_LEN)); 80 rte_errno = EINVAL; 81 return -rte_errno; 82 } 83 priv->rss_conf.rss_key = 84 mlx5_realloc(priv->rss_conf.rss_key, MLX5_MEM_RTE, 85 MLX5_RSS_HASH_KEY_LEN, 0, SOCKET_ID_ANY); 86 if (!priv->rss_conf.rss_key) { 87 DRV_LOG(ERR, "port %u cannot allocate RSS hash key memory (%u)", 88 dev->data->port_id, rxqs_n); 89 rte_errno = ENOMEM; 90 return -rte_errno; 91 } 92 93 if ((dev->data->dev_conf.txmode.offloads & 94 RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP) && 95 rte_mbuf_dyn_tx_timestamp_register(NULL, NULL) != 0) { 96 DRV_LOG(ERR, "port %u cannot register Tx timestamp field/flag", 97 dev->data->port_id); 98 return -rte_errno; 99 } 100 memcpy(priv->rss_conf.rss_key, 101 use_app_rss_key ? 102 dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key : 103 rss_hash_default_key, 104 MLX5_RSS_HASH_KEY_LEN); 105 priv->rss_conf.rss_key_len = MLX5_RSS_HASH_KEY_LEN; 106 priv->rss_conf.rss_hf = dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf; 107 priv->rxqs = (void *)dev->data->rx_queues; 108 priv->txqs = (void *)dev->data->tx_queues; 109 if (txqs_n != priv->txqs_n) { 110 DRV_LOG(INFO, "port %u Tx queues number update: %u -> %u", 111 dev->data->port_id, priv->txqs_n, txqs_n); 112 priv->txqs_n = txqs_n; 113 } 114 if (rxqs_n > priv->config.ind_table_max_size) { 115 DRV_LOG(ERR, "port %u cannot handle this many Rx queues (%u)", 116 dev->data->port_id, rxqs_n); 117 rte_errno = EINVAL; 118 return -rte_errno; 119 } 120 if (rxqs_n != priv->rxqs_n) { 121 DRV_LOG(INFO, "port %u Rx queues number update: %u -> %u", 122 dev->data->port_id, priv->rxqs_n, rxqs_n); 123 priv->rxqs_n = rxqs_n; 124 } 125 priv->skip_default_rss_reta = 0; 126 ret = mlx5_proc_priv_init(dev); 127 if (ret) 128 return ret; 129 return 0; 130 } 131 132 /** 133 * Configure default RSS reta. 134 * 135 * @param dev 136 * Pointer to Ethernet device structure. 137 * 138 * @return 139 * 0 on success, a negative errno value otherwise and rte_errno is set. 140 */ 141 int 142 mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev) 143 { 144 struct mlx5_priv *priv = dev->data->dev_private; 145 unsigned int rxqs_n = dev->data->nb_rx_queues; 146 unsigned int i; 147 unsigned int j; 148 unsigned int reta_idx_n; 149 int ret = 0; 150 unsigned int *rss_queue_arr = NULL; 151 unsigned int rss_queue_n = 0; 152 153 if (priv->skip_default_rss_reta) 154 return ret; 155 rss_queue_arr = mlx5_malloc(0, rxqs_n * sizeof(unsigned int), 0, 156 SOCKET_ID_ANY); 157 if (!rss_queue_arr) { 158 DRV_LOG(ERR, "port %u cannot allocate RSS queue list (%u)", 159 dev->data->port_id, rxqs_n); 160 rte_errno = ENOMEM; 161 return -rte_errno; 162 } 163 for (i = 0, j = 0; i < rxqs_n; i++) { 164 struct mlx5_rxq_data *rxq_data; 165 struct mlx5_rxq_ctrl *rxq_ctrl; 166 167 rxq_data = (*priv->rxqs)[i]; 168 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq); 169 if (rxq_ctrl && rxq_ctrl->type == MLX5_RXQ_TYPE_STANDARD) 170 rss_queue_arr[j++] = i; 171 } 172 rss_queue_n = j; 173 if (rss_queue_n > priv->config.ind_table_max_size) { 174 DRV_LOG(ERR, "port %u cannot handle this many Rx queues (%u)", 175 dev->data->port_id, rss_queue_n); 176 rte_errno = EINVAL; 177 mlx5_free(rss_queue_arr); 178 return -rte_errno; 179 } 180 DRV_LOG(INFO, "port %u Rx queues number update: %u -> %u", 181 dev->data->port_id, priv->rxqs_n, rxqs_n); 182 priv->rxqs_n = rxqs_n; 183 /* 184 * If the requested number of RX queues is not a power of two, 185 * use the maximum indirection table size for better balancing. 186 * The result is always rounded to the next power of two. 187 */ 188 reta_idx_n = (1 << log2above((rss_queue_n & (rss_queue_n - 1)) ? 189 priv->config.ind_table_max_size : 190 rss_queue_n)); 191 ret = mlx5_rss_reta_index_resize(dev, reta_idx_n); 192 if (ret) { 193 mlx5_free(rss_queue_arr); 194 return ret; 195 } 196 /* 197 * When the number of RX queues is not a power of two, 198 * the remaining table entries are padded with reused WQs 199 * and hashes are not spread uniformly. 200 */ 201 for (i = 0, j = 0; (i != reta_idx_n); ++i) { 202 (*priv->reta_idx)[i] = rss_queue_arr[j]; 203 if (++j == rss_queue_n) 204 j = 0; 205 } 206 mlx5_free(rss_queue_arr); 207 return ret; 208 } 209 210 /** 211 * Sets default tuning parameters. 212 * 213 * @param dev 214 * Pointer to Ethernet device. 215 * @param[out] info 216 * Info structure output buffer. 217 */ 218 static void 219 mlx5_set_default_params(struct rte_eth_dev *dev, struct rte_eth_dev_info *info) 220 { 221 struct mlx5_priv *priv = dev->data->dev_private; 222 223 /* Minimum CPU utilization. */ 224 info->default_rxportconf.ring_size = 256; 225 info->default_txportconf.ring_size = 256; 226 info->default_rxportconf.burst_size = MLX5_RX_DEFAULT_BURST; 227 info->default_txportconf.burst_size = MLX5_TX_DEFAULT_BURST; 228 if ((priv->link_speed_capa & RTE_ETH_LINK_SPEED_200G) | 229 (priv->link_speed_capa & RTE_ETH_LINK_SPEED_100G)) { 230 info->default_rxportconf.nb_queues = 16; 231 info->default_txportconf.nb_queues = 16; 232 if (dev->data->nb_rx_queues > 2 || 233 dev->data->nb_tx_queues > 2) { 234 /* Max Throughput. */ 235 info->default_rxportconf.ring_size = 2048; 236 info->default_txportconf.ring_size = 2048; 237 } 238 } else { 239 info->default_rxportconf.nb_queues = 8; 240 info->default_txportconf.nb_queues = 8; 241 if (dev->data->nb_rx_queues > 2 || 242 dev->data->nb_tx_queues > 2) { 243 /* Max Throughput. */ 244 info->default_rxportconf.ring_size = 4096; 245 info->default_txportconf.ring_size = 4096; 246 } 247 } 248 } 249 250 /** 251 * Sets tx mbuf limiting parameters. 252 * 253 * @param dev 254 * Pointer to Ethernet device. 255 * @param[out] info 256 * Info structure output buffer. 257 */ 258 static void 259 mlx5_set_txlimit_params(struct rte_eth_dev *dev, struct rte_eth_dev_info *info) 260 { 261 struct mlx5_priv *priv = dev->data->dev_private; 262 struct mlx5_dev_config *config = &priv->config; 263 unsigned int inlen; 264 uint16_t nb_max; 265 266 inlen = (config->txq_inline_max == MLX5_ARG_UNSET) ? 267 MLX5_SEND_DEF_INLINE_LEN : 268 (unsigned int)config->txq_inline_max; 269 MLX5_ASSERT(config->txq_inline_min >= 0); 270 inlen = RTE_MAX(inlen, (unsigned int)config->txq_inline_min); 271 inlen = RTE_MIN(inlen, MLX5_WQE_SIZE_MAX + 272 MLX5_ESEG_MIN_INLINE_SIZE - 273 MLX5_WQE_CSEG_SIZE - 274 MLX5_WQE_ESEG_SIZE - 275 MLX5_WQE_DSEG_SIZE * 2); 276 nb_max = (MLX5_WQE_SIZE_MAX + 277 MLX5_ESEG_MIN_INLINE_SIZE - 278 MLX5_WQE_CSEG_SIZE - 279 MLX5_WQE_ESEG_SIZE - 280 MLX5_WQE_DSEG_SIZE - 281 inlen) / MLX5_WSEG_SIZE; 282 info->tx_desc_lim.nb_seg_max = nb_max; 283 info->tx_desc_lim.nb_mtu_seg_max = nb_max; 284 } 285 286 /** 287 * DPDK callback to get information about the device. 288 * 289 * @param dev 290 * Pointer to Ethernet device structure. 291 * @param[out] info 292 * Info structure output buffer. 293 */ 294 int 295 mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info) 296 { 297 struct mlx5_priv *priv = dev->data->dev_private; 298 struct mlx5_dev_config *config = &priv->config; 299 unsigned int max; 300 301 /* FIXME: we should ask the device for these values. */ 302 info->min_rx_bufsize = 32; 303 info->max_rx_pktlen = 65536; 304 info->max_lro_pkt_size = MLX5_MAX_LRO_SIZE; 305 /* 306 * Since we need one CQ per QP, the limit is the minimum number 307 * between the two values. 308 */ 309 max = RTE_MIN(priv->sh->device_attr.max_cq, 310 priv->sh->device_attr.max_qp); 311 /* max_rx_queues is uint16_t. */ 312 max = RTE_MIN(max, (unsigned int)UINT16_MAX); 313 info->max_rx_queues = max; 314 info->max_tx_queues = max; 315 info->max_mac_addrs = MLX5_MAX_UC_MAC_ADDRESSES; 316 info->rx_queue_offload_capa = mlx5_get_rx_queue_offloads(dev); 317 info->rx_seg_capa.max_nseg = MLX5_MAX_RXQ_NSEG; 318 info->rx_seg_capa.multi_pools = !config->mprq.enabled; 319 info->rx_seg_capa.offset_allowed = !config->mprq.enabled; 320 info->rx_seg_capa.offset_align_log2 = 0; 321 info->rx_offload_capa = (mlx5_get_rx_port_offloads() | 322 info->rx_queue_offload_capa); 323 info->tx_offload_capa = mlx5_get_tx_port_offloads(dev); 324 info->dev_capa = RTE_ETH_DEV_CAPA_FLOW_SHARED_OBJECT_KEEP; 325 info->if_index = mlx5_ifindex(dev); 326 info->reta_size = priv->reta_idx_n ? 327 priv->reta_idx_n : config->ind_table_max_size; 328 info->hash_key_size = MLX5_RSS_HASH_KEY_LEN; 329 info->speed_capa = priv->link_speed_capa; 330 info->flow_type_rss_offloads = ~MLX5_RSS_HF_MASK; 331 mlx5_set_default_params(dev, info); 332 mlx5_set_txlimit_params(dev, info); 333 info->switch_info.name = dev->data->name; 334 info->switch_info.domain_id = priv->domain_id; 335 info->switch_info.port_id = priv->representor_id; 336 if (priv->representor) { 337 uint16_t port_id; 338 339 MLX5_ETH_FOREACH_DEV(port_id, dev->device) { 340 struct mlx5_priv *opriv = 341 rte_eth_devices[port_id].data->dev_private; 342 343 if (!opriv || 344 opriv->representor || 345 opriv->sh != priv->sh || 346 opriv->domain_id != priv->domain_id) 347 continue; 348 /* 349 * Override switch name with that of the master 350 * device. 351 */ 352 info->switch_info.name = opriv->dev_data->name; 353 break; 354 } 355 } 356 return 0; 357 } 358 359 /** 360 * Calculate representor ID from port switch info. 361 * 362 * Uint16 representor ID bits definition: 363 * pf: 2 364 * type: 2 365 * vf/sf: 12 366 * 367 * @param info 368 * Port switch info. 369 * @param hpf_type 370 * Use this type if port is HPF. 371 * 372 * @return 373 * Encoded representor ID. 374 */ 375 uint16_t 376 mlx5_representor_id_encode(const struct mlx5_switch_info *info, 377 enum rte_eth_representor_type hpf_type) 378 { 379 enum rte_eth_representor_type type = RTE_ETH_REPRESENTOR_VF; 380 uint16_t repr = info->port_name; 381 382 if (info->representor == 0) 383 return UINT16_MAX; 384 if (info->name_type == MLX5_PHYS_PORT_NAME_TYPE_PFSF) 385 type = RTE_ETH_REPRESENTOR_SF; 386 if (info->name_type == MLX5_PHYS_PORT_NAME_TYPE_PFHPF) { 387 type = hpf_type; 388 repr = UINT16_MAX; 389 } 390 return MLX5_REPRESENTOR_ID(info->pf_num, type, repr); 391 } 392 393 /** 394 * DPDK callback to get information about representor. 395 * 396 * Representor ID bits definition: 397 * vf/sf: 12 398 * type: 2 399 * pf: 2 400 * 401 * @param dev 402 * Pointer to Ethernet device structure. 403 * @param[out] info 404 * Nullable info structure output buffer. 405 * 406 * @return 407 * negative on error, or the number of representor ranges. 408 */ 409 int 410 mlx5_representor_info_get(struct rte_eth_dev *dev, 411 struct rte_eth_representor_info *info) 412 { 413 struct mlx5_priv *priv = dev->data->dev_private; 414 int n_type = 4; /* Representor types, VF, HPF@VF, SF and HPF@SF. */ 415 int n_pf = 2; /* Number of PFs. */ 416 int i = 0, pf; 417 int n_entries; 418 419 if (info == NULL) 420 goto out; 421 422 n_entries = n_type * n_pf; 423 if ((uint32_t)n_entries > info->nb_ranges_alloc) 424 n_entries = info->nb_ranges_alloc; 425 426 info->controller = 0; 427 info->pf = priv->pf_bond >= 0 ? priv->pf_bond : 0; 428 for (pf = 0; pf < n_pf; ++pf) { 429 /* VF range. */ 430 info->ranges[i].type = RTE_ETH_REPRESENTOR_VF; 431 info->ranges[i].controller = 0; 432 info->ranges[i].pf = pf; 433 info->ranges[i].vf = 0; 434 info->ranges[i].id_base = 435 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, 0); 436 info->ranges[i].id_end = 437 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1); 438 snprintf(info->ranges[i].name, 439 sizeof(info->ranges[i].name), "pf%dvf", pf); 440 i++; 441 if (i == n_entries) 442 break; 443 /* HPF range of VF type. */ 444 info->ranges[i].type = RTE_ETH_REPRESENTOR_VF; 445 info->ranges[i].controller = 0; 446 info->ranges[i].pf = pf; 447 info->ranges[i].vf = UINT16_MAX; 448 info->ranges[i].id_base = 449 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1); 450 info->ranges[i].id_end = 451 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1); 452 snprintf(info->ranges[i].name, 453 sizeof(info->ranges[i].name), "pf%dvf", pf); 454 i++; 455 if (i == n_entries) 456 break; 457 /* SF range. */ 458 info->ranges[i].type = RTE_ETH_REPRESENTOR_SF; 459 info->ranges[i].controller = 0; 460 info->ranges[i].pf = pf; 461 info->ranges[i].vf = 0; 462 info->ranges[i].id_base = 463 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, 0); 464 info->ranges[i].id_end = 465 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1); 466 snprintf(info->ranges[i].name, 467 sizeof(info->ranges[i].name), "pf%dsf", pf); 468 i++; 469 if (i == n_entries) 470 break; 471 /* HPF range of SF type. */ 472 info->ranges[i].type = RTE_ETH_REPRESENTOR_SF; 473 info->ranges[i].controller = 0; 474 info->ranges[i].pf = pf; 475 info->ranges[i].vf = UINT16_MAX; 476 info->ranges[i].id_base = 477 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1); 478 info->ranges[i].id_end = 479 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1); 480 snprintf(info->ranges[i].name, 481 sizeof(info->ranges[i].name), "pf%dsf", pf); 482 i++; 483 if (i == n_entries) 484 break; 485 } 486 info->nb_ranges = i; 487 out: 488 return n_type * n_pf; 489 } 490 491 /** 492 * Get firmware version of a device. 493 * 494 * @param dev 495 * Ethernet device port. 496 * @param fw_ver 497 * String output allocated by caller. 498 * @param fw_size 499 * Size of the output string, including terminating null byte. 500 * 501 * @return 502 * 0 on success, or the size of the non truncated string if too big. 503 */ 504 int 505 mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size) 506 { 507 struct mlx5_priv *priv = dev->data->dev_private; 508 struct mlx5_dev_attr *attr = &priv->sh->device_attr; 509 size_t size = strnlen(attr->fw_ver, sizeof(attr->fw_ver)) + 1; 510 511 if (fw_size < size) 512 return size; 513 if (fw_ver != NULL) 514 strlcpy(fw_ver, attr->fw_ver, fw_size); 515 return 0; 516 } 517 518 /** 519 * Get supported packet types. 520 * 521 * @param dev 522 * Pointer to Ethernet device structure. 523 * 524 * @return 525 * A pointer to the supported Packet types array. 526 */ 527 const uint32_t * 528 mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev) 529 { 530 static const uint32_t ptypes[] = { 531 /* refers to rxq_cq_to_pkt_type() */ 532 RTE_PTYPE_L2_ETHER, 533 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 534 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 535 RTE_PTYPE_L4_NONFRAG, 536 RTE_PTYPE_L4_FRAG, 537 RTE_PTYPE_L4_TCP, 538 RTE_PTYPE_L4_UDP, 539 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN, 540 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN, 541 RTE_PTYPE_INNER_L4_NONFRAG, 542 RTE_PTYPE_INNER_L4_FRAG, 543 RTE_PTYPE_INNER_L4_TCP, 544 RTE_PTYPE_INNER_L4_UDP, 545 RTE_PTYPE_UNKNOWN 546 }; 547 548 if (dev->rx_pkt_burst == mlx5_rx_burst || 549 dev->rx_pkt_burst == mlx5_rx_burst_mprq || 550 dev->rx_pkt_burst == mlx5_rx_burst_vec || 551 dev->rx_pkt_burst == mlx5_rx_burst_mprq_vec) 552 return ptypes; 553 return NULL; 554 } 555 556 /** 557 * DPDK callback to change the MTU. 558 * 559 * @param dev 560 * Pointer to Ethernet device structure. 561 * @param in_mtu 562 * New MTU. 563 * 564 * @return 565 * 0 on success, a negative errno value otherwise and rte_errno is set. 566 */ 567 int 568 mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) 569 { 570 struct mlx5_priv *priv = dev->data->dev_private; 571 uint16_t kern_mtu = 0; 572 int ret; 573 574 ret = mlx5_get_mtu(dev, &kern_mtu); 575 if (ret) 576 return ret; 577 /* Set kernel interface MTU first. */ 578 ret = mlx5_set_mtu(dev, mtu); 579 if (ret) 580 return ret; 581 ret = mlx5_get_mtu(dev, &kern_mtu); 582 if (ret) 583 return ret; 584 if (kern_mtu == mtu) { 585 priv->mtu = mtu; 586 DRV_LOG(DEBUG, "port %u adapter MTU set to %u", 587 dev->data->port_id, mtu); 588 return 0; 589 } 590 rte_errno = EAGAIN; 591 return -rte_errno; 592 } 593 594 /** 595 * Configure the RX function to use. 596 * 597 * @param dev 598 * Pointer to private data structure. 599 * 600 * @return 601 * Pointer to selected Rx burst function. 602 */ 603 eth_rx_burst_t 604 mlx5_select_rx_function(struct rte_eth_dev *dev) 605 { 606 eth_rx_burst_t rx_pkt_burst = mlx5_rx_burst; 607 608 MLX5_ASSERT(dev != NULL); 609 if (mlx5_check_vec_rx_support(dev) > 0) { 610 if (mlx5_mprq_enabled(dev)) { 611 rx_pkt_burst = mlx5_rx_burst_mprq_vec; 612 DRV_LOG(DEBUG, "port %u selected vectorized" 613 " MPRQ Rx function", dev->data->port_id); 614 } else { 615 rx_pkt_burst = mlx5_rx_burst_vec; 616 DRV_LOG(DEBUG, "port %u selected vectorized" 617 " SPRQ Rx function", dev->data->port_id); 618 } 619 } else if (mlx5_mprq_enabled(dev)) { 620 rx_pkt_burst = mlx5_rx_burst_mprq; 621 DRV_LOG(DEBUG, "port %u selected MPRQ Rx function", 622 dev->data->port_id); 623 } else { 624 DRV_LOG(DEBUG, "port %u selected SPRQ Rx function", 625 dev->data->port_id); 626 } 627 return rx_pkt_burst; 628 } 629 630 /** 631 * Get the E-Switch parameters by port id. 632 * 633 * @param[in] port 634 * Device port id. 635 * @param[in] valid 636 * Device port id is valid, skip check. This flag is useful 637 * when trials are performed from probing and device is not 638 * flagged as valid yet (in attaching process). 639 * @param[out] es_domain_id 640 * E-Switch domain id. 641 * @param[out] es_port_id 642 * The port id of the port in the E-Switch. 643 * 644 * @return 645 * pointer to device private data structure containing data needed 646 * on success, NULL otherwise and rte_errno is set. 647 */ 648 struct mlx5_priv * 649 mlx5_port_to_eswitch_info(uint16_t port, bool valid) 650 { 651 struct rte_eth_dev *dev; 652 struct mlx5_priv *priv; 653 654 if (port >= RTE_MAX_ETHPORTS) { 655 rte_errno = EINVAL; 656 return NULL; 657 } 658 if (!valid && !rte_eth_dev_is_valid_port(port)) { 659 rte_errno = ENODEV; 660 return NULL; 661 } 662 dev = &rte_eth_devices[port]; 663 priv = dev->data->dev_private; 664 if (!(priv->representor || priv->master)) { 665 rte_errno = EINVAL; 666 return NULL; 667 } 668 return priv; 669 } 670 671 /** 672 * Get the E-Switch parameters by device instance. 673 * 674 * @param[in] port 675 * Device port id. 676 * @param[out] es_domain_id 677 * E-Switch domain id. 678 * @param[out] es_port_id 679 * The port id of the port in the E-Switch. 680 * 681 * @return 682 * pointer to device private data structure containing data needed 683 * on success, NULL otherwise and rte_errno is set. 684 */ 685 struct mlx5_priv * 686 mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev) 687 { 688 struct mlx5_priv *priv; 689 690 priv = dev->data->dev_private; 691 if (!(priv->representor || priv->master)) { 692 rte_errno = EINVAL; 693 return NULL; 694 } 695 return priv; 696 } 697 698 /** 699 * DPDK callback to retrieve hairpin capabilities. 700 * 701 * @param dev 702 * Pointer to Ethernet device structure. 703 * @param[out] cap 704 * Storage for hairpin capability data. 705 * 706 * @return 707 * 0 on success, a negative errno value otherwise and rte_errno is set. 708 */ 709 int 710 mlx5_hairpin_cap_get(struct rte_eth_dev *dev, struct rte_eth_hairpin_cap *cap) 711 { 712 struct mlx5_priv *priv = dev->data->dev_private; 713 struct mlx5_dev_config *config = &priv->config; 714 715 if (!priv->sh->devx || !config->dest_tir || !config->dv_flow_en) { 716 rte_errno = ENOTSUP; 717 return -rte_errno; 718 } 719 cap->max_nb_queues = UINT16_MAX; 720 cap->max_rx_2_tx = 1; 721 cap->max_tx_2_rx = 1; 722 cap->max_nb_desc = 8192; 723 return 0; 724 } 725