1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <stdint.h> 10 #include <stdlib.h> 11 #include <errno.h> 12 13 #include <ethdev_driver.h> 14 #include <rte_bus_pci.h> 15 #include <rte_mbuf.h> 16 #include <rte_common.h> 17 #include <rte_interrupts.h> 18 #include <rte_malloc.h> 19 #include <rte_string_fns.h> 20 #include <rte_rwlock.h> 21 #include <rte_cycles.h> 22 23 #include <mlx5_malloc.h> 24 25 #include "mlx5_rxtx.h" 26 #include "mlx5_autoconf.h" 27 28 /** 29 * Get the interface index from device name. 30 * 31 * @param[in] dev 32 * Pointer to Ethernet device. 33 * 34 * @return 35 * Nonzero interface index on success, zero otherwise and rte_errno is set. 36 */ 37 unsigned int 38 mlx5_ifindex(const struct rte_eth_dev *dev) 39 { 40 struct mlx5_priv *priv = dev->data->dev_private; 41 unsigned int ifindex; 42 43 MLX5_ASSERT(priv); 44 MLX5_ASSERT(priv->if_index); 45 if (priv->master && priv->sh->bond.ifindex > 0) 46 ifindex = priv->sh->bond.ifindex; 47 else 48 ifindex = priv->if_index; 49 if (!ifindex) 50 rte_errno = ENXIO; 51 return ifindex; 52 } 53 54 /** 55 * DPDK callback for Ethernet device configuration. 56 * 57 * @param dev 58 * Pointer to Ethernet device structure. 59 * 60 * @return 61 * 0 on success, a negative errno value otherwise and rte_errno is set. 62 */ 63 int 64 mlx5_dev_configure(struct rte_eth_dev *dev) 65 { 66 struct mlx5_priv *priv = dev->data->dev_private; 67 unsigned int rxqs_n = dev->data->nb_rx_queues; 68 unsigned int txqs_n = dev->data->nb_tx_queues; 69 const uint8_t use_app_rss_key = 70 !!dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key; 71 int ret = 0; 72 73 if (use_app_rss_key && 74 (dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key_len != 75 MLX5_RSS_HASH_KEY_LEN)) { 76 DRV_LOG(ERR, "port %u RSS key len must be %s Bytes long", 77 dev->data->port_id, RTE_STR(MLX5_RSS_HASH_KEY_LEN)); 78 rte_errno = EINVAL; 79 return -rte_errno; 80 } 81 priv->rss_conf.rss_key = 82 mlx5_realloc(priv->rss_conf.rss_key, MLX5_MEM_RTE, 83 MLX5_RSS_HASH_KEY_LEN, 0, SOCKET_ID_ANY); 84 if (!priv->rss_conf.rss_key) { 85 DRV_LOG(ERR, "port %u cannot allocate RSS hash key memory (%u)", 86 dev->data->port_id, rxqs_n); 87 rte_errno = ENOMEM; 88 return -rte_errno; 89 } 90 91 if ((dev->data->dev_conf.txmode.offloads & 92 DEV_TX_OFFLOAD_SEND_ON_TIMESTAMP) && 93 rte_mbuf_dyn_tx_timestamp_register(NULL, NULL) != 0) { 94 DRV_LOG(ERR, "port %u cannot register Tx timestamp field/flag", 95 dev->data->port_id); 96 return -rte_errno; 97 } 98 memcpy(priv->rss_conf.rss_key, 99 use_app_rss_key ? 100 dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key : 101 rss_hash_default_key, 102 MLX5_RSS_HASH_KEY_LEN); 103 priv->rss_conf.rss_key_len = MLX5_RSS_HASH_KEY_LEN; 104 priv->rss_conf.rss_hf = dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf; 105 priv->rxqs = (void *)dev->data->rx_queues; 106 priv->txqs = (void *)dev->data->tx_queues; 107 if (txqs_n != priv->txqs_n) { 108 DRV_LOG(INFO, "port %u Tx queues number update: %u -> %u", 109 dev->data->port_id, priv->txqs_n, txqs_n); 110 priv->txqs_n = txqs_n; 111 } 112 if (rxqs_n > priv->config.ind_table_max_size) { 113 DRV_LOG(ERR, "port %u cannot handle this many Rx queues (%u)", 114 dev->data->port_id, rxqs_n); 115 rte_errno = EINVAL; 116 return -rte_errno; 117 } 118 if (rxqs_n != priv->rxqs_n) { 119 DRV_LOG(INFO, "port %u Rx queues number update: %u -> %u", 120 dev->data->port_id, priv->rxqs_n, rxqs_n); 121 priv->rxqs_n = rxqs_n; 122 } 123 priv->skip_default_rss_reta = 0; 124 ret = mlx5_proc_priv_init(dev); 125 if (ret) 126 return ret; 127 return 0; 128 } 129 130 /** 131 * Configure default RSS reta. 132 * 133 * @param dev 134 * Pointer to Ethernet device structure. 135 * 136 * @return 137 * 0 on success, a negative errno value otherwise and rte_errno is set. 138 */ 139 int 140 mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev) 141 { 142 struct mlx5_priv *priv = dev->data->dev_private; 143 unsigned int rxqs_n = dev->data->nb_rx_queues; 144 unsigned int i; 145 unsigned int j; 146 unsigned int reta_idx_n; 147 int ret = 0; 148 unsigned int *rss_queue_arr = NULL; 149 unsigned int rss_queue_n = 0; 150 151 if (priv->skip_default_rss_reta) 152 return ret; 153 rss_queue_arr = mlx5_malloc(0, rxqs_n * sizeof(unsigned int), 0, 154 SOCKET_ID_ANY); 155 if (!rss_queue_arr) { 156 DRV_LOG(ERR, "port %u cannot allocate RSS queue list (%u)", 157 dev->data->port_id, rxqs_n); 158 rte_errno = ENOMEM; 159 return -rte_errno; 160 } 161 for (i = 0, j = 0; i < rxqs_n; i++) { 162 struct mlx5_rxq_data *rxq_data; 163 struct mlx5_rxq_ctrl *rxq_ctrl; 164 165 rxq_data = (*priv->rxqs)[i]; 166 rxq_ctrl = container_of(rxq_data, struct mlx5_rxq_ctrl, rxq); 167 if (rxq_ctrl && rxq_ctrl->type == MLX5_RXQ_TYPE_STANDARD) 168 rss_queue_arr[j++] = i; 169 } 170 rss_queue_n = j; 171 if (rss_queue_n > priv->config.ind_table_max_size) { 172 DRV_LOG(ERR, "port %u cannot handle this many Rx queues (%u)", 173 dev->data->port_id, rss_queue_n); 174 rte_errno = EINVAL; 175 mlx5_free(rss_queue_arr); 176 return -rte_errno; 177 } 178 DRV_LOG(INFO, "port %u Rx queues number update: %u -> %u", 179 dev->data->port_id, priv->rxqs_n, rxqs_n); 180 priv->rxqs_n = rxqs_n; 181 /* 182 * If the requested number of RX queues is not a power of two, 183 * use the maximum indirection table size for better balancing. 184 * The result is always rounded to the next power of two. 185 */ 186 reta_idx_n = (1 << log2above((rss_queue_n & (rss_queue_n - 1)) ? 187 priv->config.ind_table_max_size : 188 rss_queue_n)); 189 ret = mlx5_rss_reta_index_resize(dev, reta_idx_n); 190 if (ret) { 191 mlx5_free(rss_queue_arr); 192 return ret; 193 } 194 /* 195 * When the number of RX queues is not a power of two, 196 * the remaining table entries are padded with reused WQs 197 * and hashes are not spread uniformly. 198 */ 199 for (i = 0, j = 0; (i != reta_idx_n); ++i) { 200 (*priv->reta_idx)[i] = rss_queue_arr[j]; 201 if (++j == rss_queue_n) 202 j = 0; 203 } 204 mlx5_free(rss_queue_arr); 205 return ret; 206 } 207 208 /** 209 * Sets default tuning parameters. 210 * 211 * @param dev 212 * Pointer to Ethernet device. 213 * @param[out] info 214 * Info structure output buffer. 215 */ 216 static void 217 mlx5_set_default_params(struct rte_eth_dev *dev, struct rte_eth_dev_info *info) 218 { 219 struct mlx5_priv *priv = dev->data->dev_private; 220 221 /* Minimum CPU utilization. */ 222 info->default_rxportconf.ring_size = 256; 223 info->default_txportconf.ring_size = 256; 224 info->default_rxportconf.burst_size = MLX5_RX_DEFAULT_BURST; 225 info->default_txportconf.burst_size = MLX5_TX_DEFAULT_BURST; 226 if ((priv->link_speed_capa & ETH_LINK_SPEED_200G) | 227 (priv->link_speed_capa & ETH_LINK_SPEED_100G)) { 228 info->default_rxportconf.nb_queues = 16; 229 info->default_txportconf.nb_queues = 16; 230 if (dev->data->nb_rx_queues > 2 || 231 dev->data->nb_tx_queues > 2) { 232 /* Max Throughput. */ 233 info->default_rxportconf.ring_size = 2048; 234 info->default_txportconf.ring_size = 2048; 235 } 236 } else { 237 info->default_rxportconf.nb_queues = 8; 238 info->default_txportconf.nb_queues = 8; 239 if (dev->data->nb_rx_queues > 2 || 240 dev->data->nb_tx_queues > 2) { 241 /* Max Throughput. */ 242 info->default_rxportconf.ring_size = 4096; 243 info->default_txportconf.ring_size = 4096; 244 } 245 } 246 } 247 248 /** 249 * Sets tx mbuf limiting parameters. 250 * 251 * @param dev 252 * Pointer to Ethernet device. 253 * @param[out] info 254 * Info structure output buffer. 255 */ 256 static void 257 mlx5_set_txlimit_params(struct rte_eth_dev *dev, struct rte_eth_dev_info *info) 258 { 259 struct mlx5_priv *priv = dev->data->dev_private; 260 struct mlx5_dev_config *config = &priv->config; 261 unsigned int inlen; 262 uint16_t nb_max; 263 264 inlen = (config->txq_inline_max == MLX5_ARG_UNSET) ? 265 MLX5_SEND_DEF_INLINE_LEN : 266 (unsigned int)config->txq_inline_max; 267 MLX5_ASSERT(config->txq_inline_min >= 0); 268 inlen = RTE_MAX(inlen, (unsigned int)config->txq_inline_min); 269 inlen = RTE_MIN(inlen, MLX5_WQE_SIZE_MAX + 270 MLX5_ESEG_MIN_INLINE_SIZE - 271 MLX5_WQE_CSEG_SIZE - 272 MLX5_WQE_ESEG_SIZE - 273 MLX5_WQE_DSEG_SIZE * 2); 274 nb_max = (MLX5_WQE_SIZE_MAX + 275 MLX5_ESEG_MIN_INLINE_SIZE - 276 MLX5_WQE_CSEG_SIZE - 277 MLX5_WQE_ESEG_SIZE - 278 MLX5_WQE_DSEG_SIZE - 279 inlen) / MLX5_WSEG_SIZE; 280 info->tx_desc_lim.nb_seg_max = nb_max; 281 info->tx_desc_lim.nb_mtu_seg_max = nb_max; 282 } 283 284 /** 285 * DPDK callback to get information about the device. 286 * 287 * @param dev 288 * Pointer to Ethernet device structure. 289 * @param[out] info 290 * Info structure output buffer. 291 */ 292 int 293 mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info) 294 { 295 struct mlx5_priv *priv = dev->data->dev_private; 296 struct mlx5_dev_config *config = &priv->config; 297 unsigned int max; 298 299 /* FIXME: we should ask the device for these values. */ 300 info->min_rx_bufsize = 32; 301 info->max_rx_pktlen = 65536; 302 info->max_lro_pkt_size = MLX5_MAX_LRO_SIZE; 303 /* 304 * Since we need one CQ per QP, the limit is the minimum number 305 * between the two values. 306 */ 307 max = RTE_MIN(priv->sh->device_attr.max_cq, 308 priv->sh->device_attr.max_qp); 309 /* max_rx_queues is uint16_t. */ 310 max = RTE_MIN(max, (unsigned int)UINT16_MAX); 311 info->max_rx_queues = max; 312 info->max_tx_queues = max; 313 info->max_mac_addrs = MLX5_MAX_UC_MAC_ADDRESSES; 314 info->rx_queue_offload_capa = mlx5_get_rx_queue_offloads(dev); 315 info->rx_seg_capa.max_nseg = MLX5_MAX_RXQ_NSEG; 316 info->rx_seg_capa.multi_pools = !config->mprq.enabled; 317 info->rx_seg_capa.offset_allowed = !config->mprq.enabled; 318 info->rx_seg_capa.offset_align_log2 = 0; 319 info->rx_offload_capa = (mlx5_get_rx_port_offloads() | 320 info->rx_queue_offload_capa); 321 info->tx_offload_capa = mlx5_get_tx_port_offloads(dev); 322 info->if_index = mlx5_ifindex(dev); 323 info->reta_size = priv->reta_idx_n ? 324 priv->reta_idx_n : config->ind_table_max_size; 325 info->hash_key_size = MLX5_RSS_HASH_KEY_LEN; 326 info->speed_capa = priv->link_speed_capa; 327 info->flow_type_rss_offloads = ~MLX5_RSS_HF_MASK; 328 mlx5_set_default_params(dev, info); 329 mlx5_set_txlimit_params(dev, info); 330 info->switch_info.name = dev->data->name; 331 info->switch_info.domain_id = priv->domain_id; 332 info->switch_info.port_id = priv->representor_id; 333 if (priv->representor) { 334 uint16_t port_id; 335 336 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) { 337 struct mlx5_priv *opriv = 338 rte_eth_devices[port_id].data->dev_private; 339 340 if (!opriv || 341 opriv->representor || 342 opriv->sh != priv->sh || 343 opriv->domain_id != priv->domain_id) 344 continue; 345 /* 346 * Override switch name with that of the master 347 * device. 348 */ 349 info->switch_info.name = opriv->dev_data->name; 350 break; 351 } 352 } 353 return 0; 354 } 355 356 /** 357 * Calculate representor ID from port switch info. 358 * 359 * Uint16 representor ID bits definition: 360 * pf: 2 361 * type: 2 362 * vf/sf: 12 363 * 364 * @param info 365 * Port switch info. 366 * @param hpf_type 367 * Use this type if port is HPF. 368 * 369 * @return 370 * Encoded representor ID. 371 */ 372 uint16_t 373 mlx5_representor_id_encode(const struct mlx5_switch_info *info, 374 enum rte_eth_representor_type hpf_type) 375 { 376 enum rte_eth_representor_type type = RTE_ETH_REPRESENTOR_VF; 377 uint16_t repr = info->port_name; 378 379 if (info->representor == 0) 380 return UINT16_MAX; 381 if (info->name_type == MLX5_PHYS_PORT_NAME_TYPE_PFSF) 382 type = RTE_ETH_REPRESENTOR_SF; 383 if (info->name_type == MLX5_PHYS_PORT_NAME_TYPE_PFHPF) { 384 type = hpf_type; 385 repr = UINT16_MAX; 386 } 387 return MLX5_REPRESENTOR_ID(info->pf_num, type, repr); 388 } 389 390 /** 391 * DPDK callback to get information about representor. 392 * 393 * Representor ID bits definition: 394 * vf/sf: 12 395 * type: 2 396 * pf: 2 397 * 398 * @param dev 399 * Pointer to Ethernet device structure. 400 * @param[out] info 401 * Nullable info structure output buffer. 402 * 403 * @return 404 * negative on error, or the number of representor ranges. 405 */ 406 int 407 mlx5_representor_info_get(struct rte_eth_dev *dev, 408 struct rte_eth_representor_info *info) 409 { 410 struct mlx5_priv *priv = dev->data->dev_private; 411 int n_type = 4; /* Representor types, VF, HPF@VF, SF and HPF@SF. */ 412 int n_pf = 2; /* Number of PFs. */ 413 int i = 0, pf; 414 415 if (info == NULL) 416 goto out; 417 info->controller = 0; 418 info->pf = priv->pf_bond >= 0 ? priv->pf_bond : 0; 419 for (pf = 0; pf < n_pf; ++pf) { 420 /* VF range. */ 421 info->ranges[i].type = RTE_ETH_REPRESENTOR_VF; 422 info->ranges[i].controller = 0; 423 info->ranges[i].pf = pf; 424 info->ranges[i].vf = 0; 425 info->ranges[i].id_base = 426 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, 0); 427 info->ranges[i].id_end = 428 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1); 429 snprintf(info->ranges[i].name, 430 sizeof(info->ranges[i].name), "pf%dvf", pf); 431 i++; 432 /* HPF range of VF type. */ 433 info->ranges[i].type = RTE_ETH_REPRESENTOR_VF; 434 info->ranges[i].controller = 0; 435 info->ranges[i].pf = pf; 436 info->ranges[i].vf = UINT16_MAX; 437 info->ranges[i].id_base = 438 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1); 439 info->ranges[i].id_end = 440 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1); 441 snprintf(info->ranges[i].name, 442 sizeof(info->ranges[i].name), "pf%dvf", pf); 443 i++; 444 /* SF range. */ 445 info->ranges[i].type = RTE_ETH_REPRESENTOR_SF; 446 info->ranges[i].controller = 0; 447 info->ranges[i].pf = pf; 448 info->ranges[i].vf = 0; 449 info->ranges[i].id_base = 450 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, 0); 451 info->ranges[i].id_end = 452 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1); 453 snprintf(info->ranges[i].name, 454 sizeof(info->ranges[i].name), "pf%dsf", pf); 455 i++; 456 /* HPF range of SF type. */ 457 info->ranges[i].type = RTE_ETH_REPRESENTOR_SF; 458 info->ranges[i].controller = 0; 459 info->ranges[i].pf = pf; 460 info->ranges[i].vf = UINT16_MAX; 461 info->ranges[i].id_base = 462 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1); 463 info->ranges[i].id_end = 464 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1); 465 snprintf(info->ranges[i].name, 466 sizeof(info->ranges[i].name), "pf%dsf", pf); 467 i++; 468 } 469 out: 470 return n_type * n_pf; 471 } 472 473 /** 474 * Get firmware version of a device. 475 * 476 * @param dev 477 * Ethernet device port. 478 * @param fw_ver 479 * String output allocated by caller. 480 * @param fw_size 481 * Size of the output string, including terminating null byte. 482 * 483 * @return 484 * 0 on success, or the size of the non truncated string if too big. 485 */ 486 int 487 mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size) 488 { 489 struct mlx5_priv *priv = dev->data->dev_private; 490 struct mlx5_dev_attr *attr = &priv->sh->device_attr; 491 size_t size = strnlen(attr->fw_ver, sizeof(attr->fw_ver)) + 1; 492 493 if (fw_size < size) 494 return size; 495 if (fw_ver != NULL) 496 strlcpy(fw_ver, attr->fw_ver, fw_size); 497 return 0; 498 } 499 500 /** 501 * Get supported packet types. 502 * 503 * @param dev 504 * Pointer to Ethernet device structure. 505 * 506 * @return 507 * A pointer to the supported Packet types array. 508 */ 509 const uint32_t * 510 mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev) 511 { 512 static const uint32_t ptypes[] = { 513 /* refers to rxq_cq_to_pkt_type() */ 514 RTE_PTYPE_L2_ETHER, 515 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 516 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 517 RTE_PTYPE_L4_NONFRAG, 518 RTE_PTYPE_L4_FRAG, 519 RTE_PTYPE_L4_TCP, 520 RTE_PTYPE_L4_UDP, 521 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN, 522 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN, 523 RTE_PTYPE_INNER_L4_NONFRAG, 524 RTE_PTYPE_INNER_L4_FRAG, 525 RTE_PTYPE_INNER_L4_TCP, 526 RTE_PTYPE_INNER_L4_UDP, 527 RTE_PTYPE_UNKNOWN 528 }; 529 530 if (dev->rx_pkt_burst == mlx5_rx_burst || 531 dev->rx_pkt_burst == mlx5_rx_burst_mprq || 532 dev->rx_pkt_burst == mlx5_rx_burst_vec || 533 dev->rx_pkt_burst == mlx5_rx_burst_mprq_vec) 534 return ptypes; 535 return NULL; 536 } 537 538 /** 539 * DPDK callback to change the MTU. 540 * 541 * @param dev 542 * Pointer to Ethernet device structure. 543 * @param in_mtu 544 * New MTU. 545 * 546 * @return 547 * 0 on success, a negative errno value otherwise and rte_errno is set. 548 */ 549 int 550 mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) 551 { 552 struct mlx5_priv *priv = dev->data->dev_private; 553 uint16_t kern_mtu = 0; 554 int ret; 555 556 ret = mlx5_get_mtu(dev, &kern_mtu); 557 if (ret) 558 return ret; 559 /* Set kernel interface MTU first. */ 560 ret = mlx5_set_mtu(dev, mtu); 561 if (ret) 562 return ret; 563 ret = mlx5_get_mtu(dev, &kern_mtu); 564 if (ret) 565 return ret; 566 if (kern_mtu == mtu) { 567 priv->mtu = mtu; 568 DRV_LOG(DEBUG, "port %u adapter MTU set to %u", 569 dev->data->port_id, mtu); 570 return 0; 571 } 572 rte_errno = EAGAIN; 573 return -rte_errno; 574 } 575 576 /** 577 * Configure the RX function to use. 578 * 579 * @param dev 580 * Pointer to private data structure. 581 * 582 * @return 583 * Pointer to selected Rx burst function. 584 */ 585 eth_rx_burst_t 586 mlx5_select_rx_function(struct rte_eth_dev *dev) 587 { 588 eth_rx_burst_t rx_pkt_burst = mlx5_rx_burst; 589 590 MLX5_ASSERT(dev != NULL); 591 if (mlx5_check_vec_rx_support(dev) > 0) { 592 if (mlx5_mprq_enabled(dev)) { 593 rx_pkt_burst = mlx5_rx_burst_mprq_vec; 594 DRV_LOG(DEBUG, "port %u selected vectorized" 595 " MPRQ Rx function", dev->data->port_id); 596 } else { 597 rx_pkt_burst = mlx5_rx_burst_vec; 598 DRV_LOG(DEBUG, "port %u selected vectorized" 599 " SPRQ Rx function", dev->data->port_id); 600 } 601 } else if (mlx5_mprq_enabled(dev)) { 602 rx_pkt_burst = mlx5_rx_burst_mprq; 603 DRV_LOG(DEBUG, "port %u selected MPRQ Rx function", 604 dev->data->port_id); 605 } else { 606 DRV_LOG(DEBUG, "port %u selected SPRQ Rx function", 607 dev->data->port_id); 608 } 609 return rx_pkt_burst; 610 } 611 612 /** 613 * Get the E-Switch parameters by port id. 614 * 615 * @param[in] port 616 * Device port id. 617 * @param[in] valid 618 * Device port id is valid, skip check. This flag is useful 619 * when trials are performed from probing and device is not 620 * flagged as valid yet (in attaching process). 621 * @param[out] es_domain_id 622 * E-Switch domain id. 623 * @param[out] es_port_id 624 * The port id of the port in the E-Switch. 625 * 626 * @return 627 * pointer to device private data structure containing data needed 628 * on success, NULL otherwise and rte_errno is set. 629 */ 630 struct mlx5_priv * 631 mlx5_port_to_eswitch_info(uint16_t port, bool valid) 632 { 633 struct rte_eth_dev *dev; 634 struct mlx5_priv *priv; 635 636 if (port >= RTE_MAX_ETHPORTS) { 637 rte_errno = EINVAL; 638 return NULL; 639 } 640 if (!valid && !rte_eth_dev_is_valid_port(port)) { 641 rte_errno = ENODEV; 642 return NULL; 643 } 644 dev = &rte_eth_devices[port]; 645 priv = dev->data->dev_private; 646 if (!(priv->representor || priv->master)) { 647 rte_errno = EINVAL; 648 return NULL; 649 } 650 return priv; 651 } 652 653 /** 654 * Get the E-Switch parameters by device instance. 655 * 656 * @param[in] port 657 * Device port id. 658 * @param[out] es_domain_id 659 * E-Switch domain id. 660 * @param[out] es_port_id 661 * The port id of the port in the E-Switch. 662 * 663 * @return 664 * pointer to device private data structure containing data needed 665 * on success, NULL otherwise and rte_errno is set. 666 */ 667 struct mlx5_priv * 668 mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev) 669 { 670 struct mlx5_priv *priv; 671 672 priv = dev->data->dev_private; 673 if (!(priv->representor || priv->master)) { 674 rte_errno = EINVAL; 675 return NULL; 676 } 677 return priv; 678 } 679 680 /** 681 * DPDK callback to retrieve hairpin capabilities. 682 * 683 * @param dev 684 * Pointer to Ethernet device structure. 685 * @param[out] cap 686 * Storage for hairpin capability data. 687 * 688 * @return 689 * 0 on success, a negative errno value otherwise and rte_errno is set. 690 */ 691 int 692 mlx5_hairpin_cap_get(struct rte_eth_dev *dev, struct rte_eth_hairpin_cap *cap) 693 { 694 struct mlx5_priv *priv = dev->data->dev_private; 695 struct mlx5_dev_config *config = &priv->config; 696 697 if (!priv->sh->devx || !config->dest_tir || !config->dv_flow_en) { 698 rte_errno = ENOTSUP; 699 return -rte_errno; 700 } 701 cap->max_nb_queues = UINT16_MAX; 702 cap->max_rx_2_tx = 1; 703 cap->max_tx_2_rx = 1; 704 cap->max_nb_desc = 8192; 705 return 0; 706 } 707