1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <stdint.h> 10 #include <stdlib.h> 11 #include <errno.h> 12 13 #include <ethdev_driver.h> 14 #include <bus_pci_driver.h> 15 #include <rte_mbuf.h> 16 #include <rte_common.h> 17 #include <rte_interrupts.h> 18 #include <rte_malloc.h> 19 #include <rte_string_fns.h> 20 #include <rte_rwlock.h> 21 #include <rte_cycles.h> 22 23 #include <mlx5_malloc.h> 24 25 #include "mlx5_rxtx.h" 26 #include "mlx5_rx.h" 27 #include "mlx5_tx.h" 28 #include "mlx5_autoconf.h" 29 #include "mlx5_devx.h" 30 #include "rte_pmd_mlx5.h" 31 32 /** 33 * Get the interface index from device name. 34 * 35 * @param[in] dev 36 * Pointer to Ethernet device. 37 * 38 * @return 39 * Nonzero interface index on success, zero otherwise and rte_errno is set. 40 */ 41 unsigned int 42 mlx5_ifindex(const struct rte_eth_dev *dev) 43 { 44 struct mlx5_priv *priv = dev->data->dev_private; 45 unsigned int ifindex; 46 47 MLX5_ASSERT(priv); 48 MLX5_ASSERT(priv->if_index); 49 if (priv->master && priv->sh->bond.ifindex > 0) 50 ifindex = priv->sh->bond.ifindex; 51 else 52 ifindex = priv->if_index; 53 if (!ifindex) 54 rte_errno = ENXIO; 55 return ifindex; 56 } 57 58 /** 59 * DPDK callback for Ethernet device configuration. 60 * 61 * @param dev 62 * Pointer to Ethernet device structure. 63 * 64 * @return 65 * 0 on success, a negative errno value otherwise and rte_errno is set. 66 */ 67 int 68 mlx5_dev_configure(struct rte_eth_dev *dev) 69 { 70 struct mlx5_priv *priv = dev->data->dev_private; 71 unsigned int rxqs_n = dev->data->nb_rx_queues; 72 unsigned int txqs_n = dev->data->nb_tx_queues; 73 const uint8_t use_app_rss_key = 74 !!dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key; 75 int ret = 0; 76 77 if (use_app_rss_key && 78 (dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key_len != 79 MLX5_RSS_HASH_KEY_LEN)) { 80 DRV_LOG(ERR, "port %u RSS key len must be %s Bytes long", 81 dev->data->port_id, RTE_STR(MLX5_RSS_HASH_KEY_LEN)); 82 rte_errno = EINVAL; 83 return -rte_errno; 84 } 85 priv->rss_conf.rss_key = mlx5_realloc(priv->rss_conf.rss_key, 86 MLX5_MEM_RTE, 87 MLX5_RSS_HASH_KEY_LEN, 0, 88 SOCKET_ID_ANY); 89 if (!priv->rss_conf.rss_key) { 90 DRV_LOG(ERR, "port %u cannot allocate RSS hash key memory (%u)", 91 dev->data->port_id, rxqs_n); 92 rte_errno = ENOMEM; 93 return -rte_errno; 94 } 95 96 if ((dev->data->dev_conf.txmode.offloads & 97 RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP) && 98 rte_mbuf_dyn_tx_timestamp_register(NULL, NULL) != 0) { 99 DRV_LOG(ERR, "port %u cannot register Tx timestamp field/flag", 100 dev->data->port_id); 101 return -rte_errno; 102 } 103 memcpy(priv->rss_conf.rss_key, 104 use_app_rss_key ? 105 dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key : 106 rss_hash_default_key, 107 MLX5_RSS_HASH_KEY_LEN); 108 priv->rss_conf.rss_key_len = MLX5_RSS_HASH_KEY_LEN; 109 priv->rss_conf.rss_hf = dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf; 110 priv->rxq_privs = mlx5_realloc(priv->rxq_privs, 111 MLX5_MEM_RTE | MLX5_MEM_ZERO, 112 sizeof(void *) * rxqs_n, 0, 113 SOCKET_ID_ANY); 114 if (rxqs_n && priv->rxq_privs == NULL) { 115 DRV_LOG(ERR, "port %u cannot allocate rxq private data", 116 dev->data->port_id); 117 rte_errno = ENOMEM; 118 return -rte_errno; 119 } 120 priv->txqs = (void *)dev->data->tx_queues; 121 if (txqs_n != priv->txqs_n) { 122 DRV_LOG(INFO, "port %u Tx queues number update: %u -> %u", 123 dev->data->port_id, priv->txqs_n, txqs_n); 124 priv->txqs_n = txqs_n; 125 } 126 if (priv->ext_txqs && txqs_n >= MLX5_EXTERNAL_TX_QUEUE_ID_MIN) { 127 DRV_LOG(ERR, "port %u cannot handle this many Tx queues (%u), " 128 "the maximal number of internal Tx queues is %u", 129 dev->data->port_id, txqs_n, 130 MLX5_EXTERNAL_TX_QUEUE_ID_MIN - 1); 131 rte_errno = EINVAL; 132 return -rte_errno; 133 } 134 if (rxqs_n > priv->sh->dev_cap.ind_table_max_size) { 135 DRV_LOG(ERR, "port %u cannot handle this many Rx queues (%u)", 136 dev->data->port_id, rxqs_n); 137 rte_errno = EINVAL; 138 return -rte_errno; 139 } 140 if (priv->ext_rxqs && rxqs_n >= RTE_PMD_MLX5_EXTERNAL_RX_QUEUE_ID_MIN) { 141 DRV_LOG(ERR, "port %u cannot handle this many Rx queues (%u), " 142 "the maximal number of internal Rx queues is %u", 143 dev->data->port_id, rxqs_n, 144 RTE_PMD_MLX5_EXTERNAL_RX_QUEUE_ID_MIN - 1); 145 rte_errno = EINVAL; 146 return -rte_errno; 147 } 148 if (rxqs_n != priv->rxqs_n) { 149 DRV_LOG(INFO, "port %u Rx queues number update: %u -> %u", 150 dev->data->port_id, priv->rxqs_n, rxqs_n); 151 priv->rxqs_n = rxqs_n; 152 } 153 priv->skip_default_rss_reta = 0; 154 ret = mlx5_proc_priv_init(dev); 155 if (ret) 156 return ret; 157 ret = mlx5_dev_set_mtu(dev, dev->data->mtu); 158 if (ret) { 159 DRV_LOG(ERR, "port %u failed to set MTU to %u", dev->data->port_id, 160 dev->data->mtu); 161 return ret; 162 } 163 return 0; 164 } 165 166 /** 167 * Configure default RSS reta. 168 * 169 * @param dev 170 * Pointer to Ethernet device structure. 171 * 172 * @return 173 * 0 on success, a negative errno value otherwise and rte_errno is set. 174 */ 175 int 176 mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev) 177 { 178 struct mlx5_priv *priv = dev->data->dev_private; 179 unsigned int rxqs_n = dev->data->nb_rx_queues; 180 unsigned int i; 181 unsigned int j; 182 unsigned int reta_idx_n; 183 int ret = 0; 184 unsigned int *rss_queue_arr = NULL; 185 unsigned int rss_queue_n = 0; 186 187 if (priv->skip_default_rss_reta) 188 return ret; 189 rss_queue_arr = mlx5_malloc(0, rxqs_n * sizeof(unsigned int), 0, 190 SOCKET_ID_ANY); 191 if (!rss_queue_arr) { 192 DRV_LOG(ERR, "port %u cannot allocate RSS queue list (%u)", 193 dev->data->port_id, rxqs_n); 194 rte_errno = ENOMEM; 195 return -rte_errno; 196 } 197 for (i = 0, j = 0; i < rxqs_n; i++) { 198 struct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_ctrl_get(dev, i); 199 200 if (rxq_ctrl && !rxq_ctrl->is_hairpin) 201 rss_queue_arr[j++] = i; 202 } 203 rss_queue_n = j; 204 if (rss_queue_n > priv->sh->dev_cap.ind_table_max_size) { 205 DRV_LOG(ERR, "port %u cannot handle this many Rx queues (%u)", 206 dev->data->port_id, rss_queue_n); 207 rte_errno = EINVAL; 208 mlx5_free(rss_queue_arr); 209 return -rte_errno; 210 } 211 DRV_LOG(INFO, "port %u Rx queues number update: %u -> %u", 212 dev->data->port_id, priv->rxqs_n, rxqs_n); 213 priv->rxqs_n = rxqs_n; 214 /* 215 * If the requested number of RX queues is not a power of two, 216 * use the maximum indirection table size for better balancing. 217 * The result is always rounded to the next power of two. 218 */ 219 reta_idx_n = (1 << log2above((rss_queue_n & (rss_queue_n - 1)) ? 220 priv->sh->dev_cap.ind_table_max_size : 221 rss_queue_n)); 222 ret = mlx5_rss_reta_index_resize(dev, reta_idx_n); 223 if (ret) { 224 mlx5_free(rss_queue_arr); 225 return ret; 226 } 227 /* 228 * When the number of RX queues is not a power of two, 229 * the remaining table entries are padded with reused WQs 230 * and hashes are not spread uniformly. 231 */ 232 for (i = 0, j = 0; (i != reta_idx_n); ++i) { 233 (*priv->reta_idx)[i] = rss_queue_arr[j]; 234 if (++j == rss_queue_n) 235 j = 0; 236 } 237 mlx5_free(rss_queue_arr); 238 return ret; 239 } 240 241 /** 242 * Sets default tuning parameters. 243 * 244 * @param dev 245 * Pointer to Ethernet device. 246 * @param[out] info 247 * Info structure output buffer. 248 */ 249 static void 250 mlx5_set_default_params(struct rte_eth_dev *dev, struct rte_eth_dev_info *info) 251 { 252 struct mlx5_priv *priv = dev->data->dev_private; 253 254 /* Minimum CPU utilization. */ 255 info->default_rxportconf.ring_size = 256; 256 info->default_txportconf.ring_size = 256; 257 info->default_rxportconf.burst_size = MLX5_RX_DEFAULT_BURST; 258 info->default_txportconf.burst_size = MLX5_TX_DEFAULT_BURST; 259 if (priv->link_speed_capa >> rte_bsf32(RTE_ETH_LINK_SPEED_100G)) { 260 /* if supports at least 100G */ 261 info->default_rxportconf.nb_queues = 16; 262 info->default_txportconf.nb_queues = 16; 263 if (dev->data->nb_rx_queues > 2 || 264 dev->data->nb_tx_queues > 2) { 265 /* Max Throughput. */ 266 info->default_rxportconf.ring_size = 2048; 267 info->default_txportconf.ring_size = 2048; 268 } 269 } else { 270 info->default_rxportconf.nb_queues = 8; 271 info->default_txportconf.nb_queues = 8; 272 if (dev->data->nb_rx_queues > 2 || 273 dev->data->nb_tx_queues > 2) { 274 /* Max Throughput. */ 275 info->default_rxportconf.ring_size = 4096; 276 info->default_txportconf.ring_size = 4096; 277 } 278 } 279 } 280 281 /** 282 * Sets tx mbuf limiting parameters. 283 * 284 * @param dev 285 * Pointer to Ethernet device. 286 * @param[out] info 287 * Info structure output buffer. 288 */ 289 static void 290 mlx5_set_txlimit_params(struct rte_eth_dev *dev, struct rte_eth_dev_info *info) 291 { 292 struct mlx5_priv *priv = dev->data->dev_private; 293 struct mlx5_port_config *config = &priv->config; 294 unsigned int inlen; 295 uint16_t nb_max; 296 297 inlen = (config->txq_inline_max == MLX5_ARG_UNSET) ? 298 MLX5_SEND_DEF_INLINE_LEN : 299 (unsigned int)config->txq_inline_max; 300 MLX5_ASSERT(config->txq_inline_min >= 0); 301 inlen = RTE_MAX(inlen, (unsigned int)config->txq_inline_min); 302 inlen = RTE_MIN(inlen, MLX5_WQE_SIZE_MAX + 303 MLX5_ESEG_MIN_INLINE_SIZE - 304 MLX5_WQE_CSEG_SIZE - 305 MLX5_WQE_ESEG_SIZE - 306 MLX5_WQE_DSEG_SIZE * 2); 307 nb_max = (MLX5_WQE_SIZE_MAX + 308 MLX5_ESEG_MIN_INLINE_SIZE - 309 MLX5_WQE_CSEG_SIZE - 310 MLX5_WQE_ESEG_SIZE - 311 MLX5_WQE_DSEG_SIZE - 312 inlen) / MLX5_WSEG_SIZE; 313 info->tx_desc_lim.nb_seg_max = nb_max; 314 info->tx_desc_lim.nb_mtu_seg_max = nb_max; 315 } 316 317 /** 318 * DPDK callback to get information about the device. 319 * 320 * @param dev 321 * Pointer to Ethernet device structure. 322 * @param[out] info 323 * Info structure output buffer. 324 */ 325 int 326 mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info) 327 { 328 struct mlx5_priv *priv = dev->data->dev_private; 329 unsigned int max; 330 331 /* FIXME: we should ask the device for these values. */ 332 info->min_rx_bufsize = 32; 333 info->max_rx_pktlen = 65536; 334 info->max_lro_pkt_size = MLX5_MAX_LRO_SIZE; 335 /* 336 * Since we need one CQ per QP, the limit is the minimum number 337 * between the two values. 338 */ 339 max = RTE_MIN(priv->sh->dev_cap.max_cq, priv->sh->dev_cap.max_qp); 340 /* max_rx_queues is uint16_t. */ 341 max = RTE_MIN(max, (unsigned int)UINT16_MAX); 342 info->max_rx_queues = max; 343 info->max_tx_queues = max; 344 info->max_mac_addrs = MLX5_MAX_UC_MAC_ADDRESSES; 345 info->rx_queue_offload_capa = mlx5_get_rx_queue_offloads(dev); 346 info->rx_seg_capa.max_nseg = MLX5_MAX_RXQ_NSEG; 347 info->rx_seg_capa.multi_pools = !priv->config.mprq.enabled; 348 info->rx_seg_capa.offset_allowed = !priv->config.mprq.enabled; 349 info->rx_seg_capa.offset_align_log2 = 0; 350 info->rx_offload_capa = (mlx5_get_rx_port_offloads() | 351 info->rx_queue_offload_capa); 352 info->tx_offload_capa = mlx5_get_tx_port_offloads(dev); 353 info->dev_capa = RTE_ETH_DEV_CAPA_FLOW_SHARED_OBJECT_KEEP; 354 info->if_index = mlx5_ifindex(dev); 355 info->reta_size = priv->reta_idx_n ? 356 priv->reta_idx_n : priv->sh->dev_cap.ind_table_max_size; 357 info->hash_key_size = MLX5_RSS_HASH_KEY_LEN; 358 info->speed_capa = priv->link_speed_capa; 359 info->flow_type_rss_offloads = ~MLX5_RSS_HF_MASK; 360 mlx5_set_default_params(dev, info); 361 mlx5_set_txlimit_params(dev, info); 362 if (priv->sh->cdev->config.hca_attr.mem_rq_rmp && 363 priv->obj_ops.rxq_obj_new == devx_obj_ops.rxq_obj_new) 364 info->dev_capa |= RTE_ETH_DEV_CAPA_RXQ_SHARE; 365 info->switch_info.name = dev->data->name; 366 info->switch_info.domain_id = priv->domain_id; 367 info->switch_info.port_id = priv->representor_id; 368 info->switch_info.rx_domain = 0; /* No sub Rx domains. */ 369 if (priv->representor) { 370 uint16_t port_id; 371 372 MLX5_ETH_FOREACH_DEV(port_id, dev->device) { 373 struct mlx5_priv *opriv = 374 rte_eth_devices[port_id].data->dev_private; 375 376 if (!opriv || 377 opriv->representor || 378 opriv->sh != priv->sh || 379 opriv->domain_id != priv->domain_id) 380 continue; 381 /* 382 * Override switch name with that of the master 383 * device. 384 */ 385 info->switch_info.name = opriv->dev_data->name; 386 break; 387 } 388 } 389 return 0; 390 } 391 392 /** 393 * Calculate representor ID from port switch info. 394 * 395 * Uint16 representor ID bits definition: 396 * pf: 2 397 * type: 2 398 * vf/sf: 12 399 * 400 * @param info 401 * Port switch info. 402 * @param hpf_type 403 * Use this type if port is HPF. 404 * 405 * @return 406 * Encoded representor ID. 407 */ 408 uint16_t 409 mlx5_representor_id_encode(const struct mlx5_switch_info *info, 410 enum rte_eth_representor_type hpf_type) 411 { 412 enum rte_eth_representor_type type; 413 uint16_t repr = info->port_name; 414 int32_t pf = info->pf_num; 415 416 switch (info->name_type) { 417 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK: 418 if (!info->representor) 419 return UINT16_MAX; 420 type = RTE_ETH_REPRESENTOR_PF; 421 pf = info->mpesw_owner; 422 break; 423 case MLX5_PHYS_PORT_NAME_TYPE_PFSF: 424 type = RTE_ETH_REPRESENTOR_SF; 425 break; 426 case MLX5_PHYS_PORT_NAME_TYPE_PFHPF: 427 type = hpf_type; 428 repr = UINT16_MAX; 429 break; 430 case MLX5_PHYS_PORT_NAME_TYPE_PFVF: 431 default: 432 type = RTE_ETH_REPRESENTOR_VF; 433 break; 434 } 435 return MLX5_REPRESENTOR_ID(pf, type, repr); 436 } 437 438 /** 439 * DPDK callback to get information about representor. 440 * 441 * Representor ID bits definition: 442 * vf/sf: 12 443 * type: 2 444 * pf: 2 445 * 446 * @param dev 447 * Pointer to Ethernet device structure. 448 * @param[out] info 449 * Nullable info structure output buffer. 450 * 451 * @return 452 * negative on error, or the number of representor ranges. 453 */ 454 int 455 mlx5_representor_info_get(struct rte_eth_dev *dev, 456 struct rte_eth_representor_info *info) 457 { 458 struct mlx5_priv *priv = dev->data->dev_private; 459 int n_type = 5; /* Representor types: PF, VF, HPF@VF, SF and HPF@SF. */ 460 int n_pf = 2; /* Number of PFs. */ 461 int i = 0, pf; 462 int n_entries; 463 464 if (info == NULL) 465 goto out; 466 467 n_entries = n_type * n_pf; 468 if ((uint32_t)n_entries > info->nb_ranges_alloc) 469 n_entries = info->nb_ranges_alloc; 470 471 info->controller = 0; 472 info->pf = 0; 473 if (mlx5_is_port_on_mpesw_device(priv)) { 474 info->pf = priv->mpesw_port; 475 /* PF range, both ports will show the same information. */ 476 info->ranges[i].type = RTE_ETH_REPRESENTOR_PF; 477 info->ranges[i].controller = 0; 478 info->ranges[i].pf = priv->mpesw_owner + 1; 479 info->ranges[i].vf = 0; 480 /* 481 * The representor indexes should be the values set of "priv->mpesw_port". 482 * In the real case now, only 1 PF/UPLINK representor is supported. 483 * The port index will always be the value of "owner + 1". 484 */ 485 info->ranges[i].id_base = 486 MLX5_REPRESENTOR_ID(priv->mpesw_owner, info->ranges[i].type, 487 info->ranges[i].pf); 488 info->ranges[i].id_end = 489 MLX5_REPRESENTOR_ID(priv->mpesw_owner, info->ranges[i].type, 490 info->ranges[i].pf); 491 snprintf(info->ranges[i].name, sizeof(info->ranges[i].name), 492 "pf%d", info->ranges[i].pf); 493 i++; 494 } else if (priv->pf_bond >= 0) 495 info->pf = priv->pf_bond; 496 for (pf = 0; pf < n_pf; ++pf) { 497 /* VF range. */ 498 info->ranges[i].type = RTE_ETH_REPRESENTOR_VF; 499 info->ranges[i].controller = 0; 500 info->ranges[i].pf = pf; 501 info->ranges[i].vf = 0; 502 info->ranges[i].id_base = 503 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, 0); 504 info->ranges[i].id_end = 505 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1); 506 snprintf(info->ranges[i].name, 507 sizeof(info->ranges[i].name), "pf%dvf", pf); 508 i++; 509 if (i == n_entries) 510 break; 511 /* HPF range of VF type. */ 512 info->ranges[i].type = RTE_ETH_REPRESENTOR_VF; 513 info->ranges[i].controller = 0; 514 info->ranges[i].pf = pf; 515 info->ranges[i].vf = UINT16_MAX; 516 info->ranges[i].id_base = 517 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1); 518 info->ranges[i].id_end = 519 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1); 520 snprintf(info->ranges[i].name, 521 sizeof(info->ranges[i].name), "pf%dvf", pf); 522 i++; 523 if (i == n_entries) 524 break; 525 /* SF range. */ 526 info->ranges[i].type = RTE_ETH_REPRESENTOR_SF; 527 info->ranges[i].controller = 0; 528 info->ranges[i].pf = pf; 529 info->ranges[i].vf = 0; 530 info->ranges[i].id_base = 531 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, 0); 532 info->ranges[i].id_end = 533 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1); 534 snprintf(info->ranges[i].name, 535 sizeof(info->ranges[i].name), "pf%dsf", pf); 536 i++; 537 if (i == n_entries) 538 break; 539 /* HPF range of SF type. */ 540 info->ranges[i].type = RTE_ETH_REPRESENTOR_SF; 541 info->ranges[i].controller = 0; 542 info->ranges[i].pf = pf; 543 info->ranges[i].vf = UINT16_MAX; 544 info->ranges[i].id_base = 545 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1); 546 info->ranges[i].id_end = 547 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1); 548 snprintf(info->ranges[i].name, 549 sizeof(info->ranges[i].name), "pf%dsf", pf); 550 i++; 551 if (i == n_entries) 552 break; 553 } 554 info->nb_ranges = i; 555 out: 556 return n_type * n_pf; 557 } 558 559 /** 560 * Get firmware version of a device. 561 * 562 * @param dev 563 * Ethernet device port. 564 * @param fw_ver 565 * String output allocated by caller. 566 * @param fw_size 567 * Size of the output string, including terminating null byte. 568 * 569 * @return 570 * 0 on success, or the size of the non truncated string if too big. 571 */ 572 int 573 mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size) 574 { 575 struct mlx5_priv *priv = dev->data->dev_private; 576 struct mlx5_dev_cap *attr = &priv->sh->dev_cap; 577 size_t size = strnlen(attr->fw_ver, sizeof(attr->fw_ver)) + 1; 578 579 if (fw_size < size) 580 return size; 581 if (fw_ver != NULL) 582 strlcpy(fw_ver, attr->fw_ver, fw_size); 583 return 0; 584 } 585 586 /** 587 * Get supported packet types. 588 * 589 * @param dev 590 * Pointer to Ethernet device structure. 591 * 592 * @return 593 * A pointer to the supported Packet types array. 594 */ 595 const uint32_t * 596 mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev, size_t *no_of_elements) 597 { 598 static const uint32_t ptypes[] = { 599 /* refers to rxq_cq_to_pkt_type() */ 600 RTE_PTYPE_L2_ETHER, 601 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 602 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 603 RTE_PTYPE_L4_NONFRAG, 604 RTE_PTYPE_L4_FRAG, 605 RTE_PTYPE_L4_TCP, 606 RTE_PTYPE_L4_UDP, 607 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN, 608 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN, 609 RTE_PTYPE_INNER_L4_NONFRAG, 610 RTE_PTYPE_INNER_L4_FRAG, 611 RTE_PTYPE_INNER_L4_TCP, 612 RTE_PTYPE_INNER_L4_UDP, 613 }; 614 615 if (dev->rx_pkt_burst == mlx5_rx_burst || 616 dev->rx_pkt_burst == mlx5_rx_burst_mprq || 617 dev->rx_pkt_burst == mlx5_rx_burst_vec || 618 dev->rx_pkt_burst == mlx5_rx_burst_mprq_vec) { 619 *no_of_elements = RTE_DIM(ptypes); 620 return ptypes; 621 } 622 return NULL; 623 } 624 625 /** 626 * DPDK callback to change the MTU. 627 * 628 * @param dev 629 * Pointer to Ethernet device structure. 630 * @param in_mtu 631 * New MTU. 632 * 633 * @return 634 * 0 on success, a negative errno value otherwise and rte_errno is set. 635 */ 636 int 637 mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) 638 { 639 struct mlx5_priv *priv = dev->data->dev_private; 640 uint16_t kern_mtu = 0; 641 int ret; 642 643 ret = mlx5_get_mtu(dev, &kern_mtu); 644 if (ret) 645 return ret; 646 /* Set kernel interface MTU first. */ 647 ret = mlx5_set_mtu(dev, mtu); 648 if (ret) 649 return ret; 650 ret = mlx5_get_mtu(dev, &kern_mtu); 651 if (ret) 652 return ret; 653 if (kern_mtu == mtu) { 654 priv->mtu = mtu; 655 DRV_LOG(DEBUG, "port %u adapter MTU set to %u", 656 dev->data->port_id, mtu); 657 return 0; 658 } 659 rte_errno = EAGAIN; 660 return -rte_errno; 661 } 662 663 /** 664 * Configure the RX function to use. 665 * 666 * @param dev 667 * Pointer to private data structure. 668 * 669 * @return 670 * Pointer to selected Rx burst function. 671 */ 672 eth_rx_burst_t 673 mlx5_select_rx_function(struct rte_eth_dev *dev) 674 { 675 eth_rx_burst_t rx_pkt_burst = mlx5_rx_burst; 676 677 MLX5_ASSERT(dev != NULL); 678 if (mlx5_check_vec_rx_support(dev) > 0) { 679 if (mlx5_mprq_enabled(dev)) { 680 rx_pkt_burst = mlx5_rx_burst_mprq_vec; 681 DRV_LOG(DEBUG, "port %u selected vectorized" 682 " MPRQ Rx function", dev->data->port_id); 683 } else { 684 rx_pkt_burst = mlx5_rx_burst_vec; 685 DRV_LOG(DEBUG, "port %u selected vectorized" 686 " SPRQ Rx function", dev->data->port_id); 687 } 688 } else if (mlx5_mprq_enabled(dev)) { 689 rx_pkt_burst = mlx5_rx_burst_mprq; 690 DRV_LOG(DEBUG, "port %u selected MPRQ Rx function", 691 dev->data->port_id); 692 } else { 693 DRV_LOG(DEBUG, "port %u selected SPRQ Rx function", 694 dev->data->port_id); 695 } 696 return rx_pkt_burst; 697 } 698 699 /** 700 * Get the E-Switch parameters by port id. 701 * 702 * @param[in] port 703 * Device port id. 704 * @param[in] valid 705 * Device port id is valid, skip check. This flag is useful 706 * when trials are performed from probing and device is not 707 * flagged as valid yet (in attaching process). 708 * @param[out] es_domain_id 709 * E-Switch domain id. 710 * @param[out] es_port_id 711 * The port id of the port in the E-Switch. 712 * 713 * @return 714 * pointer to device private data structure containing data needed 715 * on success, NULL otherwise and rte_errno is set. 716 */ 717 struct mlx5_priv * 718 mlx5_port_to_eswitch_info(uint16_t port, bool valid) 719 { 720 struct rte_eth_dev *dev; 721 struct mlx5_priv *priv; 722 723 if (port >= RTE_MAX_ETHPORTS) { 724 rte_errno = EINVAL; 725 return NULL; 726 } 727 if (!valid && !rte_eth_dev_is_valid_port(port)) { 728 rte_errno = ENODEV; 729 return NULL; 730 } 731 dev = &rte_eth_devices[port]; 732 priv = dev->data->dev_private; 733 if (!priv->sh->esw_mode) { 734 rte_errno = EINVAL; 735 return NULL; 736 } 737 return priv; 738 } 739 740 /** 741 * Get the E-Switch parameters by device instance. 742 * 743 * @param[in] port 744 * Device port id. 745 * @param[out] es_domain_id 746 * E-Switch domain id. 747 * @param[out] es_port_id 748 * The port id of the port in the E-Switch. 749 * 750 * @return 751 * pointer to device private data structure containing data needed 752 * on success, NULL otherwise and rte_errno is set. 753 */ 754 struct mlx5_priv * 755 mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev) 756 { 757 struct mlx5_priv *priv; 758 759 priv = dev->data->dev_private; 760 if (!priv->sh->esw_mode) { 761 rte_errno = EINVAL; 762 return NULL; 763 } 764 return priv; 765 } 766 767 /** 768 * DPDK callback to retrieve hairpin capabilities. 769 * 770 * @param dev 771 * Pointer to Ethernet device structure. 772 * @param[out] cap 773 * Storage for hairpin capability data. 774 * 775 * @return 776 * 0 on success, a negative errno value otherwise and rte_errno is set. 777 */ 778 int 779 mlx5_hairpin_cap_get(struct rte_eth_dev *dev, struct rte_eth_hairpin_cap *cap) 780 { 781 struct mlx5_priv *priv = dev->data->dev_private; 782 struct mlx5_hca_attr *hca_attr; 783 784 if (!mlx5_devx_obj_ops_en(priv->sh)) { 785 rte_errno = ENOTSUP; 786 return -rte_errno; 787 } 788 cap->max_nb_queues = UINT16_MAX; 789 cap->max_rx_2_tx = 1; 790 cap->max_tx_2_rx = 1; 791 cap->max_nb_desc = 8192; 792 hca_attr = &priv->sh->cdev->config.hca_attr; 793 cap->rx_cap.locked_device_memory = hca_attr->hairpin_data_buffer_locked; 794 cap->rx_cap.rte_memory = 0; 795 cap->tx_cap.locked_device_memory = 0; 796 cap->tx_cap.rte_memory = hca_attr->hairpin_sq_wq_in_host_mem; 797 return 0; 798 } 799 800 /** 801 * Indicate to ethdev layer, what configuration must be restored. 802 * 803 * @param[in] dev 804 * Pointer to Ethernet device structure. 805 * @param[in] op 806 * Type of operation which might require. 807 * @param[out] flags 808 * Restore flags will be stored here. 809 */ 810 uint64_t 811 mlx5_get_restore_flags(__rte_unused struct rte_eth_dev *dev, 812 __rte_unused enum rte_eth_dev_operation op) 813 { 814 /* mlx5 PMD does not require any configuration restore. */ 815 return 0; 816 } 817