1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <stdint.h> 10 #include <stdlib.h> 11 #include <errno.h> 12 13 #include <ethdev_driver.h> 14 #include <rte_bus_pci.h> 15 #include <rte_mbuf.h> 16 #include <rte_common.h> 17 #include <rte_interrupts.h> 18 #include <rte_malloc.h> 19 #include <rte_string_fns.h> 20 #include <rte_rwlock.h> 21 #include <rte_cycles.h> 22 23 #include <mlx5_malloc.h> 24 25 #include "mlx5_rxtx.h" 26 #include "mlx5_rx.h" 27 #include "mlx5_tx.h" 28 #include "mlx5_autoconf.h" 29 #include "mlx5_devx.h" 30 31 /** 32 * Get the interface index from device name. 33 * 34 * @param[in] dev 35 * Pointer to Ethernet device. 36 * 37 * @return 38 * Nonzero interface index on success, zero otherwise and rte_errno is set. 39 */ 40 unsigned int 41 mlx5_ifindex(const struct rte_eth_dev *dev) 42 { 43 struct mlx5_priv *priv = dev->data->dev_private; 44 unsigned int ifindex; 45 46 MLX5_ASSERT(priv); 47 MLX5_ASSERT(priv->if_index); 48 if (priv->master && priv->sh->bond.ifindex > 0) 49 ifindex = priv->sh->bond.ifindex; 50 else 51 ifindex = priv->if_index; 52 if (!ifindex) 53 rte_errno = ENXIO; 54 return ifindex; 55 } 56 57 /** 58 * DPDK callback for Ethernet device configuration. 59 * 60 * @param dev 61 * Pointer to Ethernet device structure. 62 * 63 * @return 64 * 0 on success, a negative errno value otherwise and rte_errno is set. 65 */ 66 int 67 mlx5_dev_configure(struct rte_eth_dev *dev) 68 { 69 struct mlx5_priv *priv = dev->data->dev_private; 70 unsigned int rxqs_n = dev->data->nb_rx_queues; 71 unsigned int txqs_n = dev->data->nb_tx_queues; 72 const uint8_t use_app_rss_key = 73 !!dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key; 74 int ret = 0; 75 76 if (use_app_rss_key && 77 (dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key_len != 78 MLX5_RSS_HASH_KEY_LEN)) { 79 DRV_LOG(ERR, "port %u RSS key len must be %s Bytes long", 80 dev->data->port_id, RTE_STR(MLX5_RSS_HASH_KEY_LEN)); 81 rte_errno = EINVAL; 82 return -rte_errno; 83 } 84 priv->rss_conf.rss_key = 85 mlx5_realloc(priv->rss_conf.rss_key, MLX5_MEM_RTE, 86 MLX5_RSS_HASH_KEY_LEN, 0, SOCKET_ID_ANY); 87 if (!priv->rss_conf.rss_key) { 88 DRV_LOG(ERR, "port %u cannot allocate RSS hash key memory (%u)", 89 dev->data->port_id, rxqs_n); 90 rte_errno = ENOMEM; 91 return -rte_errno; 92 } 93 94 if ((dev->data->dev_conf.txmode.offloads & 95 RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP) && 96 rte_mbuf_dyn_tx_timestamp_register(NULL, NULL) != 0) { 97 DRV_LOG(ERR, "port %u cannot register Tx timestamp field/flag", 98 dev->data->port_id); 99 return -rte_errno; 100 } 101 memcpy(priv->rss_conf.rss_key, 102 use_app_rss_key ? 103 dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key : 104 rss_hash_default_key, 105 MLX5_RSS_HASH_KEY_LEN); 106 priv->rss_conf.rss_key_len = MLX5_RSS_HASH_KEY_LEN; 107 priv->rss_conf.rss_hf = dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf; 108 priv->rxq_privs = mlx5_realloc(priv->rxq_privs, 109 MLX5_MEM_RTE | MLX5_MEM_ZERO, 110 sizeof(void *) * rxqs_n, 0, 111 SOCKET_ID_ANY); 112 if (priv->rxq_privs == NULL) { 113 DRV_LOG(ERR, "port %u cannot allocate rxq private data", 114 dev->data->port_id); 115 rte_errno = ENOMEM; 116 return -rte_errno; 117 } 118 priv->txqs = (void *)dev->data->tx_queues; 119 if (txqs_n != priv->txqs_n) { 120 DRV_LOG(INFO, "port %u Tx queues number update: %u -> %u", 121 dev->data->port_id, priv->txqs_n, txqs_n); 122 priv->txqs_n = txqs_n; 123 } 124 if (rxqs_n > priv->config.ind_table_max_size) { 125 DRV_LOG(ERR, "port %u cannot handle this many Rx queues (%u)", 126 dev->data->port_id, rxqs_n); 127 rte_errno = EINVAL; 128 return -rte_errno; 129 } 130 if (rxqs_n != priv->rxqs_n) { 131 DRV_LOG(INFO, "port %u Rx queues number update: %u -> %u", 132 dev->data->port_id, priv->rxqs_n, rxqs_n); 133 priv->rxqs_n = rxqs_n; 134 } 135 priv->skip_default_rss_reta = 0; 136 ret = mlx5_proc_priv_init(dev); 137 if (ret) 138 return ret; 139 return 0; 140 } 141 142 /** 143 * Configure default RSS reta. 144 * 145 * @param dev 146 * Pointer to Ethernet device structure. 147 * 148 * @return 149 * 0 on success, a negative errno value otherwise and rte_errno is set. 150 */ 151 int 152 mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev) 153 { 154 struct mlx5_priv *priv = dev->data->dev_private; 155 unsigned int rxqs_n = dev->data->nb_rx_queues; 156 unsigned int i; 157 unsigned int j; 158 unsigned int reta_idx_n; 159 int ret = 0; 160 unsigned int *rss_queue_arr = NULL; 161 unsigned int rss_queue_n = 0; 162 163 if (priv->skip_default_rss_reta) 164 return ret; 165 rss_queue_arr = mlx5_malloc(0, rxqs_n * sizeof(unsigned int), 0, 166 SOCKET_ID_ANY); 167 if (!rss_queue_arr) { 168 DRV_LOG(ERR, "port %u cannot allocate RSS queue list (%u)", 169 dev->data->port_id, rxqs_n); 170 rte_errno = ENOMEM; 171 return -rte_errno; 172 } 173 for (i = 0, j = 0; i < rxqs_n; i++) { 174 struct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_ctrl_get(dev, i); 175 176 if (rxq_ctrl && rxq_ctrl->type == MLX5_RXQ_TYPE_STANDARD) 177 rss_queue_arr[j++] = i; 178 } 179 rss_queue_n = j; 180 if (rss_queue_n > priv->config.ind_table_max_size) { 181 DRV_LOG(ERR, "port %u cannot handle this many Rx queues (%u)", 182 dev->data->port_id, rss_queue_n); 183 rte_errno = EINVAL; 184 mlx5_free(rss_queue_arr); 185 return -rte_errno; 186 } 187 DRV_LOG(INFO, "port %u Rx queues number update: %u -> %u", 188 dev->data->port_id, priv->rxqs_n, rxqs_n); 189 priv->rxqs_n = rxqs_n; 190 /* 191 * If the requested number of RX queues is not a power of two, 192 * use the maximum indirection table size for better balancing. 193 * The result is always rounded to the next power of two. 194 */ 195 reta_idx_n = (1 << log2above((rss_queue_n & (rss_queue_n - 1)) ? 196 priv->config.ind_table_max_size : 197 rss_queue_n)); 198 ret = mlx5_rss_reta_index_resize(dev, reta_idx_n); 199 if (ret) { 200 mlx5_free(rss_queue_arr); 201 return ret; 202 } 203 /* 204 * When the number of RX queues is not a power of two, 205 * the remaining table entries are padded with reused WQs 206 * and hashes are not spread uniformly. 207 */ 208 for (i = 0, j = 0; (i != reta_idx_n); ++i) { 209 (*priv->reta_idx)[i] = rss_queue_arr[j]; 210 if (++j == rss_queue_n) 211 j = 0; 212 } 213 mlx5_free(rss_queue_arr); 214 return ret; 215 } 216 217 /** 218 * Sets default tuning parameters. 219 * 220 * @param dev 221 * Pointer to Ethernet device. 222 * @param[out] info 223 * Info structure output buffer. 224 */ 225 static void 226 mlx5_set_default_params(struct rte_eth_dev *dev, struct rte_eth_dev_info *info) 227 { 228 struct mlx5_priv *priv = dev->data->dev_private; 229 230 /* Minimum CPU utilization. */ 231 info->default_rxportconf.ring_size = 256; 232 info->default_txportconf.ring_size = 256; 233 info->default_rxportconf.burst_size = MLX5_RX_DEFAULT_BURST; 234 info->default_txportconf.burst_size = MLX5_TX_DEFAULT_BURST; 235 if ((priv->link_speed_capa & RTE_ETH_LINK_SPEED_200G) | 236 (priv->link_speed_capa & RTE_ETH_LINK_SPEED_100G)) { 237 info->default_rxportconf.nb_queues = 16; 238 info->default_txportconf.nb_queues = 16; 239 if (dev->data->nb_rx_queues > 2 || 240 dev->data->nb_tx_queues > 2) { 241 /* Max Throughput. */ 242 info->default_rxportconf.ring_size = 2048; 243 info->default_txportconf.ring_size = 2048; 244 } 245 } else { 246 info->default_rxportconf.nb_queues = 8; 247 info->default_txportconf.nb_queues = 8; 248 if (dev->data->nb_rx_queues > 2 || 249 dev->data->nb_tx_queues > 2) { 250 /* Max Throughput. */ 251 info->default_rxportconf.ring_size = 4096; 252 info->default_txportconf.ring_size = 4096; 253 } 254 } 255 } 256 257 /** 258 * Sets tx mbuf limiting parameters. 259 * 260 * @param dev 261 * Pointer to Ethernet device. 262 * @param[out] info 263 * Info structure output buffer. 264 */ 265 static void 266 mlx5_set_txlimit_params(struct rte_eth_dev *dev, struct rte_eth_dev_info *info) 267 { 268 struct mlx5_priv *priv = dev->data->dev_private; 269 struct mlx5_dev_config *config = &priv->config; 270 unsigned int inlen; 271 uint16_t nb_max; 272 273 inlen = (config->txq_inline_max == MLX5_ARG_UNSET) ? 274 MLX5_SEND_DEF_INLINE_LEN : 275 (unsigned int)config->txq_inline_max; 276 MLX5_ASSERT(config->txq_inline_min >= 0); 277 inlen = RTE_MAX(inlen, (unsigned int)config->txq_inline_min); 278 inlen = RTE_MIN(inlen, MLX5_WQE_SIZE_MAX + 279 MLX5_ESEG_MIN_INLINE_SIZE - 280 MLX5_WQE_CSEG_SIZE - 281 MLX5_WQE_ESEG_SIZE - 282 MLX5_WQE_DSEG_SIZE * 2); 283 nb_max = (MLX5_WQE_SIZE_MAX + 284 MLX5_ESEG_MIN_INLINE_SIZE - 285 MLX5_WQE_CSEG_SIZE - 286 MLX5_WQE_ESEG_SIZE - 287 MLX5_WQE_DSEG_SIZE - 288 inlen) / MLX5_WSEG_SIZE; 289 info->tx_desc_lim.nb_seg_max = nb_max; 290 info->tx_desc_lim.nb_mtu_seg_max = nb_max; 291 } 292 293 /** 294 * DPDK callback to get information about the device. 295 * 296 * @param dev 297 * Pointer to Ethernet device structure. 298 * @param[out] info 299 * Info structure output buffer. 300 */ 301 int 302 mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info) 303 { 304 struct mlx5_priv *priv = dev->data->dev_private; 305 struct mlx5_dev_config *config = &priv->config; 306 unsigned int max; 307 308 /* FIXME: we should ask the device for these values. */ 309 info->min_rx_bufsize = 32; 310 info->max_rx_pktlen = 65536; 311 info->max_lro_pkt_size = MLX5_MAX_LRO_SIZE; 312 /* 313 * Since we need one CQ per QP, the limit is the minimum number 314 * between the two values. 315 */ 316 max = RTE_MIN(priv->sh->device_attr.max_cq, 317 priv->sh->device_attr.max_qp); 318 /* max_rx_queues is uint16_t. */ 319 max = RTE_MIN(max, (unsigned int)UINT16_MAX); 320 info->max_rx_queues = max; 321 info->max_tx_queues = max; 322 info->max_mac_addrs = MLX5_MAX_UC_MAC_ADDRESSES; 323 info->rx_queue_offload_capa = mlx5_get_rx_queue_offloads(dev); 324 info->rx_seg_capa.max_nseg = MLX5_MAX_RXQ_NSEG; 325 info->rx_seg_capa.multi_pools = !config->mprq.enabled; 326 info->rx_seg_capa.offset_allowed = !config->mprq.enabled; 327 info->rx_seg_capa.offset_align_log2 = 0; 328 info->rx_offload_capa = (mlx5_get_rx_port_offloads() | 329 info->rx_queue_offload_capa); 330 info->tx_offload_capa = mlx5_get_tx_port_offloads(dev); 331 info->dev_capa = RTE_ETH_DEV_CAPA_FLOW_SHARED_OBJECT_KEEP; 332 info->if_index = mlx5_ifindex(dev); 333 info->reta_size = priv->reta_idx_n ? 334 priv->reta_idx_n : config->ind_table_max_size; 335 info->hash_key_size = MLX5_RSS_HASH_KEY_LEN; 336 info->speed_capa = priv->link_speed_capa; 337 info->flow_type_rss_offloads = ~MLX5_RSS_HF_MASK; 338 mlx5_set_default_params(dev, info); 339 mlx5_set_txlimit_params(dev, info); 340 if (priv->config.hca_attr.mem_rq_rmp && 341 priv->obj_ops.rxq_obj_new == devx_obj_ops.rxq_obj_new) 342 info->dev_capa |= RTE_ETH_DEV_CAPA_RXQ_SHARE; 343 info->switch_info.name = dev->data->name; 344 info->switch_info.domain_id = priv->domain_id; 345 info->switch_info.port_id = priv->representor_id; 346 info->switch_info.rx_domain = 0; /* No sub Rx domains. */ 347 if (priv->representor) { 348 uint16_t port_id; 349 350 MLX5_ETH_FOREACH_DEV(port_id, dev->device) { 351 struct mlx5_priv *opriv = 352 rte_eth_devices[port_id].data->dev_private; 353 354 if (!opriv || 355 opriv->representor || 356 opriv->sh != priv->sh || 357 opriv->domain_id != priv->domain_id) 358 continue; 359 /* 360 * Override switch name with that of the master 361 * device. 362 */ 363 info->switch_info.name = opriv->dev_data->name; 364 break; 365 } 366 } 367 return 0; 368 } 369 370 /** 371 * Calculate representor ID from port switch info. 372 * 373 * Uint16 representor ID bits definition: 374 * pf: 2 375 * type: 2 376 * vf/sf: 12 377 * 378 * @param info 379 * Port switch info. 380 * @param hpf_type 381 * Use this type if port is HPF. 382 * 383 * @return 384 * Encoded representor ID. 385 */ 386 uint16_t 387 mlx5_representor_id_encode(const struct mlx5_switch_info *info, 388 enum rte_eth_representor_type hpf_type) 389 { 390 enum rte_eth_representor_type type = RTE_ETH_REPRESENTOR_VF; 391 uint16_t repr = info->port_name; 392 393 if (info->representor == 0) 394 return UINT16_MAX; 395 if (info->name_type == MLX5_PHYS_PORT_NAME_TYPE_PFSF) 396 type = RTE_ETH_REPRESENTOR_SF; 397 if (info->name_type == MLX5_PHYS_PORT_NAME_TYPE_PFHPF) { 398 type = hpf_type; 399 repr = UINT16_MAX; 400 } 401 return MLX5_REPRESENTOR_ID(info->pf_num, type, repr); 402 } 403 404 /** 405 * DPDK callback to get information about representor. 406 * 407 * Representor ID bits definition: 408 * vf/sf: 12 409 * type: 2 410 * pf: 2 411 * 412 * @param dev 413 * Pointer to Ethernet device structure. 414 * @param[out] info 415 * Nullable info structure output buffer. 416 * 417 * @return 418 * negative on error, or the number of representor ranges. 419 */ 420 int 421 mlx5_representor_info_get(struct rte_eth_dev *dev, 422 struct rte_eth_representor_info *info) 423 { 424 struct mlx5_priv *priv = dev->data->dev_private; 425 int n_type = 4; /* Representor types, VF, HPF@VF, SF and HPF@SF. */ 426 int n_pf = 2; /* Number of PFs. */ 427 int i = 0, pf; 428 int n_entries; 429 430 if (info == NULL) 431 goto out; 432 433 n_entries = n_type * n_pf; 434 if ((uint32_t)n_entries > info->nb_ranges_alloc) 435 n_entries = info->nb_ranges_alloc; 436 437 info->controller = 0; 438 info->pf = priv->pf_bond >= 0 ? priv->pf_bond : 0; 439 for (pf = 0; pf < n_pf; ++pf) { 440 /* VF range. */ 441 info->ranges[i].type = RTE_ETH_REPRESENTOR_VF; 442 info->ranges[i].controller = 0; 443 info->ranges[i].pf = pf; 444 info->ranges[i].vf = 0; 445 info->ranges[i].id_base = 446 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, 0); 447 info->ranges[i].id_end = 448 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1); 449 snprintf(info->ranges[i].name, 450 sizeof(info->ranges[i].name), "pf%dvf", pf); 451 i++; 452 if (i == n_entries) 453 break; 454 /* HPF range of VF type. */ 455 info->ranges[i].type = RTE_ETH_REPRESENTOR_VF; 456 info->ranges[i].controller = 0; 457 info->ranges[i].pf = pf; 458 info->ranges[i].vf = UINT16_MAX; 459 info->ranges[i].id_base = 460 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1); 461 info->ranges[i].id_end = 462 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1); 463 snprintf(info->ranges[i].name, 464 sizeof(info->ranges[i].name), "pf%dvf", pf); 465 i++; 466 if (i == n_entries) 467 break; 468 /* SF range. */ 469 info->ranges[i].type = RTE_ETH_REPRESENTOR_SF; 470 info->ranges[i].controller = 0; 471 info->ranges[i].pf = pf; 472 info->ranges[i].vf = 0; 473 info->ranges[i].id_base = 474 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, 0); 475 info->ranges[i].id_end = 476 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1); 477 snprintf(info->ranges[i].name, 478 sizeof(info->ranges[i].name), "pf%dsf", pf); 479 i++; 480 if (i == n_entries) 481 break; 482 /* HPF range of SF type. */ 483 info->ranges[i].type = RTE_ETH_REPRESENTOR_SF; 484 info->ranges[i].controller = 0; 485 info->ranges[i].pf = pf; 486 info->ranges[i].vf = UINT16_MAX; 487 info->ranges[i].id_base = 488 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1); 489 info->ranges[i].id_end = 490 MLX5_REPRESENTOR_ID(pf, info->ranges[i].type, -1); 491 snprintf(info->ranges[i].name, 492 sizeof(info->ranges[i].name), "pf%dsf", pf); 493 i++; 494 if (i == n_entries) 495 break; 496 } 497 info->nb_ranges = i; 498 out: 499 return n_type * n_pf; 500 } 501 502 /** 503 * Get firmware version of a device. 504 * 505 * @param dev 506 * Ethernet device port. 507 * @param fw_ver 508 * String output allocated by caller. 509 * @param fw_size 510 * Size of the output string, including terminating null byte. 511 * 512 * @return 513 * 0 on success, or the size of the non truncated string if too big. 514 */ 515 int 516 mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size) 517 { 518 struct mlx5_priv *priv = dev->data->dev_private; 519 struct mlx5_dev_attr *attr = &priv->sh->device_attr; 520 size_t size = strnlen(attr->fw_ver, sizeof(attr->fw_ver)) + 1; 521 522 if (fw_size < size) 523 return size; 524 if (fw_ver != NULL) 525 strlcpy(fw_ver, attr->fw_ver, fw_size); 526 return 0; 527 } 528 529 /** 530 * Get supported packet types. 531 * 532 * @param dev 533 * Pointer to Ethernet device structure. 534 * 535 * @return 536 * A pointer to the supported Packet types array. 537 */ 538 const uint32_t * 539 mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev) 540 { 541 static const uint32_t ptypes[] = { 542 /* refers to rxq_cq_to_pkt_type() */ 543 RTE_PTYPE_L2_ETHER, 544 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 545 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 546 RTE_PTYPE_L4_NONFRAG, 547 RTE_PTYPE_L4_FRAG, 548 RTE_PTYPE_L4_TCP, 549 RTE_PTYPE_L4_UDP, 550 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN, 551 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN, 552 RTE_PTYPE_INNER_L4_NONFRAG, 553 RTE_PTYPE_INNER_L4_FRAG, 554 RTE_PTYPE_INNER_L4_TCP, 555 RTE_PTYPE_INNER_L4_UDP, 556 RTE_PTYPE_UNKNOWN 557 }; 558 559 if (dev->rx_pkt_burst == mlx5_rx_burst || 560 dev->rx_pkt_burst == mlx5_rx_burst_mprq || 561 dev->rx_pkt_burst == mlx5_rx_burst_vec || 562 dev->rx_pkt_burst == mlx5_rx_burst_mprq_vec) 563 return ptypes; 564 return NULL; 565 } 566 567 /** 568 * DPDK callback to change the MTU. 569 * 570 * @param dev 571 * Pointer to Ethernet device structure. 572 * @param in_mtu 573 * New MTU. 574 * 575 * @return 576 * 0 on success, a negative errno value otherwise and rte_errno is set. 577 */ 578 int 579 mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu) 580 { 581 struct mlx5_priv *priv = dev->data->dev_private; 582 uint16_t kern_mtu = 0; 583 int ret; 584 585 ret = mlx5_get_mtu(dev, &kern_mtu); 586 if (ret) 587 return ret; 588 /* Set kernel interface MTU first. */ 589 ret = mlx5_set_mtu(dev, mtu); 590 if (ret) 591 return ret; 592 ret = mlx5_get_mtu(dev, &kern_mtu); 593 if (ret) 594 return ret; 595 if (kern_mtu == mtu) { 596 priv->mtu = mtu; 597 DRV_LOG(DEBUG, "port %u adapter MTU set to %u", 598 dev->data->port_id, mtu); 599 return 0; 600 } 601 rte_errno = EAGAIN; 602 return -rte_errno; 603 } 604 605 /** 606 * Configure the RX function to use. 607 * 608 * @param dev 609 * Pointer to private data structure. 610 * 611 * @return 612 * Pointer to selected Rx burst function. 613 */ 614 eth_rx_burst_t 615 mlx5_select_rx_function(struct rte_eth_dev *dev) 616 { 617 eth_rx_burst_t rx_pkt_burst = mlx5_rx_burst; 618 619 MLX5_ASSERT(dev != NULL); 620 if (mlx5_check_vec_rx_support(dev) > 0) { 621 if (mlx5_mprq_enabled(dev)) { 622 rx_pkt_burst = mlx5_rx_burst_mprq_vec; 623 DRV_LOG(DEBUG, "port %u selected vectorized" 624 " MPRQ Rx function", dev->data->port_id); 625 } else { 626 rx_pkt_burst = mlx5_rx_burst_vec; 627 DRV_LOG(DEBUG, "port %u selected vectorized" 628 " SPRQ Rx function", dev->data->port_id); 629 } 630 } else if (mlx5_mprq_enabled(dev)) { 631 rx_pkt_burst = mlx5_rx_burst_mprq; 632 DRV_LOG(DEBUG, "port %u selected MPRQ Rx function", 633 dev->data->port_id); 634 } else { 635 DRV_LOG(DEBUG, "port %u selected SPRQ Rx function", 636 dev->data->port_id); 637 } 638 return rx_pkt_burst; 639 } 640 641 /** 642 * Get the E-Switch parameters by port id. 643 * 644 * @param[in] port 645 * Device port id. 646 * @param[in] valid 647 * Device port id is valid, skip check. This flag is useful 648 * when trials are performed from probing and device is not 649 * flagged as valid yet (in attaching process). 650 * @param[out] es_domain_id 651 * E-Switch domain id. 652 * @param[out] es_port_id 653 * The port id of the port in the E-Switch. 654 * 655 * @return 656 * pointer to device private data structure containing data needed 657 * on success, NULL otherwise and rte_errno is set. 658 */ 659 struct mlx5_priv * 660 mlx5_port_to_eswitch_info(uint16_t port, bool valid) 661 { 662 struct rte_eth_dev *dev; 663 struct mlx5_priv *priv; 664 665 if (port >= RTE_MAX_ETHPORTS) { 666 rte_errno = EINVAL; 667 return NULL; 668 } 669 if (!valid && !rte_eth_dev_is_valid_port(port)) { 670 rte_errno = ENODEV; 671 return NULL; 672 } 673 dev = &rte_eth_devices[port]; 674 priv = dev->data->dev_private; 675 if (!(priv->representor || priv->master)) { 676 rte_errno = EINVAL; 677 return NULL; 678 } 679 return priv; 680 } 681 682 /** 683 * Get the E-Switch parameters by device instance. 684 * 685 * @param[in] port 686 * Device port id. 687 * @param[out] es_domain_id 688 * E-Switch domain id. 689 * @param[out] es_port_id 690 * The port id of the port in the E-Switch. 691 * 692 * @return 693 * pointer to device private data structure containing data needed 694 * on success, NULL otherwise and rte_errno is set. 695 */ 696 struct mlx5_priv * 697 mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev) 698 { 699 struct mlx5_priv *priv; 700 701 priv = dev->data->dev_private; 702 if (!(priv->representor || priv->master)) { 703 rte_errno = EINVAL; 704 return NULL; 705 } 706 return priv; 707 } 708 709 /** 710 * DPDK callback to retrieve hairpin capabilities. 711 * 712 * @param dev 713 * Pointer to Ethernet device structure. 714 * @param[out] cap 715 * Storage for hairpin capability data. 716 * 717 * @return 718 * 0 on success, a negative errno value otherwise and rte_errno is set. 719 */ 720 int 721 mlx5_hairpin_cap_get(struct rte_eth_dev *dev, struct rte_eth_hairpin_cap *cap) 722 { 723 struct mlx5_priv *priv = dev->data->dev_private; 724 struct mlx5_dev_config *config = &priv->config; 725 726 if (!priv->sh->devx || !config->dest_tir || !config->dv_flow_en) { 727 rte_errno = ENOTSUP; 728 return -rte_errno; 729 } 730 cap->max_nb_queues = UINT16_MAX; 731 cap->max_rx_2_tx = 1; 732 cap->max_tx_2_rx = 1; 733 cap->max_nb_desc = 8192; 734 return 0; 735 } 736