1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2022 NVIDIA Corporation & Affiliates 3 */ 4 5 #ifndef MLX5DR_DEBUG_H_ 6 #define MLX5DR_DEBUG_H_ 7 8 #define DEBUG_VERSION "1.0.DPDK" 9 10 enum mlx5dr_debug_res_type { 11 MLX5DR_DEBUG_RES_TYPE_CONTEXT = 4000, 12 MLX5DR_DEBUG_RES_TYPE_CONTEXT_ATTR = 4001, 13 MLX5DR_DEBUG_RES_TYPE_CONTEXT_CAPS = 4002, 14 MLX5DR_DEBUG_RES_TYPE_CONTEXT_SEND_ENGINE = 4003, 15 MLX5DR_DEBUG_RES_TYPE_CONTEXT_SEND_RING = 4004, 16 MLX5DR_DEBUG_RES_TYPE_CONTEXT_STC = 4005, 17 18 MLX5DR_DEBUG_RES_TYPE_TABLE = 4100, 19 20 MLX5DR_DEBUG_RES_TYPE_MATCHER = 4200, 21 MLX5DR_DEBUG_RES_TYPE_MATCHER_ATTR = 4201, 22 MLX5DR_DEBUG_RES_TYPE_MATCHER_MATCH_TEMPLATE = 4202, 23 MLX5DR_DEBUG_RES_TYPE_MATCHER_TEMPLATE_MATCH_DEFINER = 4203, 24 MLX5DR_DEBUG_RES_TYPE_MATCHER_ACTION_TEMPLATE = 4204, 25 MLX5DR_DEBUG_RES_TYPE_MATCHER_TEMPLATE_HASH_DEFINER = 4205, 26 MLX5DR_DEBUG_RES_TYPE_MATCHER_TEMPLATE_RANGE_DEFINER = 4206, 27 }; 28 29 static inline uint64_t 30 mlx5dr_debug_icm_to_idx(uint64_t icm_addr) 31 { 32 return (icm_addr >> 6) & 0xffffffff; 33 } 34 35 const char *mlx5dr_debug_action_type_to_str(enum mlx5dr_action_type action_type); 36 37 #endif /* MLX5DR_DEBUG_H_ */ 38