178580cf4SHamdan Igbaria /* SPDX-License-Identifier: BSD-3-Clause 278580cf4SHamdan Igbaria * Copyright (c) 2022 NVIDIA Corporation & Affiliates 378580cf4SHamdan Igbaria */ 478580cf4SHamdan Igbaria 578580cf4SHamdan Igbaria #ifndef MLX5DR_DEBUG_H_ 678580cf4SHamdan Igbaria #define MLX5DR_DEBUG_H_ 778580cf4SHamdan Igbaria 878580cf4SHamdan Igbaria #define DEBUG_VERSION "1.0.DPDK" 978580cf4SHamdan Igbaria 1078580cf4SHamdan Igbaria enum mlx5dr_debug_res_type { 1178580cf4SHamdan Igbaria MLX5DR_DEBUG_RES_TYPE_CONTEXT = 4000, 1278580cf4SHamdan Igbaria MLX5DR_DEBUG_RES_TYPE_CONTEXT_ATTR = 4001, 1378580cf4SHamdan Igbaria MLX5DR_DEBUG_RES_TYPE_CONTEXT_CAPS = 4002, 1478580cf4SHamdan Igbaria MLX5DR_DEBUG_RES_TYPE_CONTEXT_SEND_ENGINE = 4003, 1578580cf4SHamdan Igbaria MLX5DR_DEBUG_RES_TYPE_CONTEXT_SEND_RING = 4004, 16*a2ea62bcSHamdan Igbaria MLX5DR_DEBUG_RES_TYPE_CONTEXT_STC = 4005, 1778580cf4SHamdan Igbaria 1878580cf4SHamdan Igbaria MLX5DR_DEBUG_RES_TYPE_TABLE = 4100, 1978580cf4SHamdan Igbaria 2078580cf4SHamdan Igbaria MLX5DR_DEBUG_RES_TYPE_MATCHER = 4200, 2178580cf4SHamdan Igbaria MLX5DR_DEBUG_RES_TYPE_MATCHER_ATTR = 4201, 2278580cf4SHamdan Igbaria MLX5DR_DEBUG_RES_TYPE_MATCHER_MATCH_TEMPLATE = 4202, 23d6c69bcaSAlex Vesker MLX5DR_DEBUG_RES_TYPE_MATCHER_TEMPLATE_MATCH_DEFINER = 4203, 2478580cf4SHamdan Igbaria MLX5DR_DEBUG_RES_TYPE_MATCHER_ACTION_TEMPLATE = 4204, 25d6c69bcaSAlex Vesker MLX5DR_DEBUG_RES_TYPE_MATCHER_TEMPLATE_HASH_DEFINER = 4205, 26d6c69bcaSAlex Vesker MLX5DR_DEBUG_RES_TYPE_MATCHER_TEMPLATE_RANGE_DEFINER = 4206, 2778580cf4SHamdan Igbaria }; 2878580cf4SHamdan Igbaria 2978580cf4SHamdan Igbaria const char *mlx5dr_debug_action_type_to_str(enum mlx5dr_action_type action_type); 3078580cf4SHamdan Igbaria 3178580cf4SHamdan Igbaria #endif /* MLX5DR_DEBUG_H_ */ 32