1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 6WIND S.A. 3 * Copyright 2018 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX4_MR_H_ 7 #define RTE_PMD_MLX4_MR_H_ 8 9 #include <stddef.h> 10 #include <stdint.h> 11 #include <sys/queue.h> 12 13 /* Verbs headers do not support -pedantic. */ 14 #ifdef PEDANTIC 15 #pragma GCC diagnostic ignored "-Wpedantic" 16 #endif 17 #include <infiniband/verbs.h> 18 #ifdef PEDANTIC 19 #pragma GCC diagnostic error "-Wpedantic" 20 #endif 21 22 #include <rte_ethdev.h> 23 #include <rte_rwlock.h> 24 #include <rte_bitmap.h> 25 26 /* Size of per-queue MR cache array for linear search. */ 27 #define MLX4_MR_CACHE_N 8 28 29 /* Size of MR cache table for binary search. */ 30 #define MLX4_MR_BTREE_CACHE_N 256 31 32 /* Memory Region object. */ 33 struct mlx4_mr { 34 LIST_ENTRY(mlx4_mr) mr; /**< Pointer to the prev/next entry. */ 35 struct ibv_mr *ibv_mr; /* Verbs Memory Region. */ 36 const struct rte_memseg_list *msl; 37 int ms_base_idx; /* Start index of msl->memseg_arr[]. */ 38 int ms_n; /* Number of memsegs in use. */ 39 uint32_t ms_bmp_n; /* Number of bits in memsegs bit-mask. */ 40 struct rte_bitmap *ms_bmp; /* Bit-mask of memsegs belonged to MR. */ 41 }; 42 43 /* Cache entry for Memory Region. */ 44 struct mlx4_mr_cache { 45 uintptr_t start; /* Start address of MR. */ 46 uintptr_t end; /* End address of MR. */ 47 uint32_t lkey; /* rte_cpu_to_be_32(ibv_mr->lkey). */ 48 } __rte_packed; 49 50 /* MR Cache table for Binary search. */ 51 struct mlx4_mr_btree { 52 uint16_t len; /* Number of entries. */ 53 uint16_t size; /* Total number of entries. */ 54 int overflow; /* Mark failure of table expansion. */ 55 struct mlx4_mr_cache (*table)[]; 56 } __rte_packed; 57 58 /* Per-queue MR control descriptor. */ 59 struct mlx4_mr_ctrl { 60 uint32_t *dev_gen_ptr; /* Generation number of device to poll. */ 61 uint32_t cur_gen; /* Generation number saved to flush caches. */ 62 uint16_t mru; /* Index of last hit entry in top-half cache. */ 63 uint16_t head; /* Index of the oldest entry in top-half cache. */ 64 struct mlx4_mr_cache cache[MLX4_MR_CACHE_N]; /* Cache for top-half. */ 65 struct mlx4_mr_btree cache_bh; /* Cache for bottom-half. */ 66 } __rte_packed; 67 68 extern struct mlx4_dev_list mlx4_mem_event_cb_list; 69 extern rte_rwlock_t mlx4_mem_event_rwlock; 70 71 /* First entry must be NULL for comparison. */ 72 #define mlx4_mr_btree_len(bt) ((bt)->len - 1) 73 74 int mlx4_mr_btree_init(struct mlx4_mr_btree *bt, int n, int socket); 75 void mlx4_mr_btree_free(struct mlx4_mr_btree *bt); 76 void mlx4_mr_btree_dump(struct mlx4_mr_btree *bt); 77 uint32_t mlx4_mr_create_primary(struct rte_eth_dev *dev, 78 struct mlx4_mr_cache *entry, uintptr_t addr); 79 void mlx4_mr_mem_event_cb(enum rte_mem_event event_type, const void *addr, 80 size_t len, void *arg); 81 int mlx4_mr_update_mp(struct rte_eth_dev *dev, struct mlx4_mr_ctrl *mr_ctrl, 82 struct rte_mempool *mp); 83 void mlx4_mr_dump_dev(struct rte_eth_dev *dev); 84 void mlx4_mr_release(struct rte_eth_dev *dev); 85 86 /** 87 * Look up LKey from given lookup table by linear search. Firstly look up the 88 * last-hit entry. If miss, the entire array is searched. If found, update the 89 * last-hit index and return LKey. 90 * 91 * @param lkp_tbl 92 * Pointer to lookup table. 93 * @param[in,out] cached_idx 94 * Pointer to last-hit index. 95 * @param n 96 * Size of lookup table. 97 * @param addr 98 * Search key. 99 * 100 * @return 101 * Searched LKey on success, UINT32_MAX on no match. 102 */ 103 static __rte_always_inline uint32_t 104 mlx4_mr_lookup_cache(struct mlx4_mr_cache *lkp_tbl, uint16_t *cached_idx, 105 uint16_t n, uintptr_t addr) 106 { 107 uint16_t idx; 108 109 if (likely(addr >= lkp_tbl[*cached_idx].start && 110 addr < lkp_tbl[*cached_idx].end)) 111 return lkp_tbl[*cached_idx].lkey; 112 for (idx = 0; idx < n && lkp_tbl[idx].start != 0; ++idx) { 113 if (addr >= lkp_tbl[idx].start && 114 addr < lkp_tbl[idx].end) { 115 /* Found. */ 116 *cached_idx = idx; 117 return lkp_tbl[idx].lkey; 118 } 119 } 120 return UINT32_MAX; 121 } 122 123 #endif /* RTE_PMD_MLX4_MR_H_ */ 124