1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2012 6WIND S.A. 3 * Copyright 2012 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX4_H_ 7 #define RTE_PMD_MLX4_H_ 8 9 #include <net/if.h> 10 #include <stdint.h> 11 #include <sys/queue.h> 12 13 /* Verbs headers do not support -pedantic. */ 14 #ifdef PEDANTIC 15 #pragma GCC diagnostic ignored "-Wpedantic" 16 #endif 17 #include <infiniband/verbs.h> 18 #ifdef PEDANTIC 19 #pragma GCC diagnostic error "-Wpedantic" 20 #endif 21 22 #include <ethdev_driver.h> 23 #include <rte_ether.h> 24 #include <rte_interrupts.h> 25 #include <rte_mempool.h> 26 #include <rte_rwlock.h> 27 28 #include "mlx4_mr.h" 29 30 #ifndef IBV_RX_HASH_INNER 31 /** This is not necessarily defined by supported RDMA core versions. */ 32 #define IBV_RX_HASH_INNER (1ull << 31) 33 #endif /* IBV_RX_HASH_INNER */ 34 35 /** Maximum number of simultaneous MAC addresses. This value is arbitrary. */ 36 #define MLX4_MAX_MAC_ADDRESSES 128 37 38 /** Request send completion once in every 64 sends, might be less. */ 39 #define MLX4_PMD_TX_PER_COMP_REQ 64 40 41 /** Maximum size for inline data. */ 42 #define MLX4_PMD_MAX_INLINE 0 43 44 /** Fixed RSS hash key size in bytes. Cannot be modified. */ 45 #define MLX4_RSS_HASH_KEY_SIZE 40 46 47 /** Interrupt alarm timeout value in microseconds. */ 48 #define MLX4_INTR_ALARM_TIMEOUT 100000 49 50 /* Maximum packet headers size (L2+L3+L4) for TSO. */ 51 #define MLX4_MAX_TSO_HEADER 192 52 53 /** Port parameter. */ 54 #define MLX4_PMD_PORT_KVARG "port" 55 56 /** Enable extending memsegs when creating a MR. */ 57 #define MLX4_MR_EXT_MEMSEG_EN_KVARG "mr_ext_memseg_en" 58 59 enum { 60 PCI_VENDOR_ID_MELLANOX = 0x15b3, 61 }; 62 63 enum { 64 PCI_DEVICE_ID_MELLANOX_CONNECTX3 = 0x1003, 65 PCI_DEVICE_ID_MELLANOX_CONNECTX3VF = 0x1004, 66 PCI_DEVICE_ID_MELLANOX_CONNECTX3PRO = 0x1007, 67 }; 68 69 /* Request types for IPC. */ 70 enum mlx4_mp_req_type { 71 MLX4_MP_REQ_VERBS_CMD_FD = 1, 72 MLX4_MP_REQ_CREATE_MR, 73 MLX4_MP_REQ_START_RXTX, 74 MLX4_MP_REQ_STOP_RXTX, 75 }; 76 77 /* Pameters for IPC. */ 78 struct mlx4_mp_param { 79 enum mlx4_mp_req_type type; 80 int port_id; 81 int result; 82 RTE_STD_C11 83 union { 84 uintptr_t addr; /* MLX4_MP_REQ_CREATE_MR */ 85 } args; 86 }; 87 88 /** Request timeout for IPC. */ 89 #define MLX4_MP_REQ_TIMEOUT_SEC 5 90 91 /** Key string for IPC. */ 92 #define MLX4_MP_NAME "net_mlx4_mp" 93 94 /** Driver name reported to lower layers and used in log output. */ 95 #define MLX4_DRIVER_NAME "net_mlx4" 96 97 struct mlx4_drop; 98 struct mlx4_rss; 99 struct rxq; 100 struct txq; 101 struct rte_flow; 102 103 /** 104 * Type of object being allocated. 105 */ 106 enum mlx4_verbs_alloc_type { 107 MLX4_VERBS_ALLOC_TYPE_NONE, 108 MLX4_VERBS_ALLOC_TYPE_TX_QUEUE, 109 MLX4_VERBS_ALLOC_TYPE_RX_QUEUE, 110 }; 111 112 /** 113 * Verbs allocator needs a context to know in the callback which kind of 114 * resources it is allocating. 115 */ 116 struct mlx4_verbs_alloc_ctx { 117 int enabled; 118 enum mlx4_verbs_alloc_type type; /* Kind of object being allocated. */ 119 const void *obj; /* Pointer to the DPDK object. */ 120 }; 121 122 LIST_HEAD(mlx4_dev_list, mlx4_priv); 123 LIST_HEAD(mlx4_mr_list, mlx4_mr); 124 125 /* Shared data between primary and secondary processes. */ 126 struct mlx4_shared_data { 127 rte_spinlock_t lock; 128 /* Global spinlock for primary and secondary processes. */ 129 int init_done; /* Whether primary has done initialization. */ 130 unsigned int secondary_cnt; /* Number of secondary processes init'd. */ 131 struct mlx4_dev_list mem_event_cb_list; 132 rte_rwlock_t mem_event_rwlock; 133 }; 134 135 /* Per-process data structure, not visible to other processes. */ 136 struct mlx4_local_data { 137 int init_done; /* Whether a secondary has done initialization. */ 138 }; 139 140 extern struct mlx4_shared_data *mlx4_shared_data; 141 142 /* Per-process private structure. */ 143 struct mlx4_proc_priv { 144 size_t uar_table_sz; 145 /* Size of UAR register table. */ 146 void *uar_table[]; 147 /* Table of UAR registers for each process. */ 148 }; 149 150 #define MLX4_PROC_PRIV(port_id) \ 151 ((struct mlx4_proc_priv *)rte_eth_devices[port_id].process_private) 152 153 /** Private data structure. */ 154 struct mlx4_priv { 155 LIST_ENTRY(mlx4_priv) mem_event_cb; 156 /**< Called by memory event callback. */ 157 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */ 158 struct ibv_context *ctx; /**< Verbs context. */ 159 struct ibv_device_attr device_attr; /**< Device properties. */ 160 struct ibv_pd *pd; /**< Protection Domain. */ 161 /* Device properties. */ 162 unsigned int if_index; /**< Associated network device index */ 163 uint16_t mtu; /**< Configured MTU. */ 164 uint8_t port; /**< Physical port number. */ 165 uint32_t started:1; /**< Device started, flows enabled. */ 166 uint32_t vf:1; /**< This is a VF device. */ 167 uint32_t intr_alarm:1; /**< An interrupt alarm is scheduled. */ 168 uint32_t isolated:1; /**< Toggle isolated mode. */ 169 uint32_t rss_init:1; /**< Common RSS context is initialized. */ 170 uint32_t hw_csum:1; /**< Checksum offload is supported. */ 171 uint32_t hw_csum_l2tun:1; /**< Checksum support for L2 tunnels. */ 172 uint32_t hw_fcs_strip:1; /**< FCS stripping toggling is supported. */ 173 uint32_t tso:1; /**< Transmit segmentation offload is supported. */ 174 uint32_t mr_ext_memseg_en:1; 175 /** Whether memseg should be extended for MR creation. */ 176 uint32_t tso_max_payload_sz; /**< Max supported TSO payload size. */ 177 uint32_t hw_rss_max_qps; /**< Max Rx Queues supported by RSS. */ 178 uint64_t hw_rss_sup; /**< Supported RSS hash fields (Verbs format). */ 179 struct rte_intr_handle intr_handle; /**< Port interrupt handle. */ 180 struct mlx4_drop *drop; /**< Shared resources for drop flow rules. */ 181 struct { 182 uint32_t dev_gen; /* Generation number to flush local caches. */ 183 rte_rwlock_t rwlock; /* MR Lock. */ 184 struct mlx4_mr_btree cache; /* Global MR cache table. */ 185 struct mlx4_mr_list mr_list; /* Registered MR list. */ 186 struct mlx4_mr_list mr_free_list; /* Freed MR list. */ 187 } mr; 188 LIST_HEAD(, mlx4_rss) rss; /**< Shared targets for Rx flow rules. */ 189 LIST_HEAD(, rte_flow) flows; /**< Configured flow rule handles. */ 190 struct rte_ether_addr mac[MLX4_MAX_MAC_ADDRESSES]; 191 /**< Configured MAC addresses. Unused entries are zeroed. */ 192 uint32_t mac_mc; /**< Number of trailing multicast entries in mac[]. */ 193 struct mlx4_verbs_alloc_ctx verbs_alloc_ctx; 194 /**< Context for Verbs allocator. */ 195 }; 196 197 #define PORT_ID(priv) ((priv)->dev_data->port_id) 198 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)]) 199 200 int mlx4_proc_priv_init(struct rte_eth_dev *dev); 201 void mlx4_proc_priv_uninit(struct rte_eth_dev *dev); 202 203 204 /* mlx4_ethdev.c */ 205 206 int mlx4_get_ifname(const struct mlx4_priv *priv, char (*ifname)[IF_NAMESIZE]); 207 int mlx4_get_mac(struct mlx4_priv *priv, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]); 208 int mlx4_mtu_get(struct mlx4_priv *priv, uint16_t *mtu); 209 int mlx4_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 210 int mlx4_dev_set_link_down(struct rte_eth_dev *dev); 211 int mlx4_dev_set_link_up(struct rte_eth_dev *dev); 212 int mlx4_promiscuous_enable(struct rte_eth_dev *dev); 213 int mlx4_promiscuous_disable(struct rte_eth_dev *dev); 214 int mlx4_allmulticast_enable(struct rte_eth_dev *dev); 215 int mlx4_allmulticast_disable(struct rte_eth_dev *dev); 216 void mlx4_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index); 217 int mlx4_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr, 218 uint32_t index, uint32_t vmdq); 219 int mlx4_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr); 220 int mlx4_set_mc_addr_list(struct rte_eth_dev *dev, struct rte_ether_addr *list, 221 uint32_t num); 222 int mlx4_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on); 223 int mlx4_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats); 224 int mlx4_stats_reset(struct rte_eth_dev *dev); 225 int mlx4_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size); 226 int mlx4_dev_infos_get(struct rte_eth_dev *dev, 227 struct rte_eth_dev_info *info); 228 int mlx4_link_update(struct rte_eth_dev *dev, int wait_to_complete); 229 int mlx4_flow_ctrl_get(struct rte_eth_dev *dev, 230 struct rte_eth_fc_conf *fc_conf); 231 int mlx4_flow_ctrl_set(struct rte_eth_dev *dev, 232 struct rte_eth_fc_conf *fc_conf); 233 const uint32_t *mlx4_dev_supported_ptypes_get(struct rte_eth_dev *dev); 234 int mlx4_is_removed(struct rte_eth_dev *dev); 235 236 /* mlx4_intr.c */ 237 238 int mlx4_intr_uninstall(struct mlx4_priv *priv); 239 int mlx4_intr_install(struct mlx4_priv *priv); 240 int mlx4_rxq_intr_enable(struct mlx4_priv *priv); 241 void mlx4_rxq_intr_disable(struct mlx4_priv *priv); 242 int mlx4_rx_intr_disable(struct rte_eth_dev *dev, uint16_t idx); 243 int mlx4_rx_intr_enable(struct rte_eth_dev *dev, uint16_t idx); 244 245 /* mlx4_mp.c */ 246 void mlx4_mp_req_start_rxtx(struct rte_eth_dev *dev); 247 void mlx4_mp_req_stop_rxtx(struct rte_eth_dev *dev); 248 int mlx4_mp_req_mr_create(struct rte_eth_dev *dev, uintptr_t addr); 249 int mlx4_mp_req_verbs_cmd_fd(struct rte_eth_dev *dev); 250 int mlx4_mp_init_primary(void); 251 void mlx4_mp_uninit_primary(void); 252 int mlx4_mp_init_secondary(void); 253 void mlx4_mp_uninit_secondary(void); 254 255 #endif /* RTE_PMD_MLX4_H_ */ 256