1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018-2022 Advanced Micro Devices, Inc. 3 */ 4 5 #include <stdio.h> 6 #include <errno.h> 7 #include <stdint.h> 8 #include <assert.h> 9 10 #include <rte_common.h> 11 #include <rte_byteorder.h> 12 #include <rte_atomic.h> 13 #include <rte_mempool.h> 14 #include <rte_mbuf.h> 15 #include <rte_ether.h> 16 #include <rte_prefetch.h> 17 18 #include "ionic.h" 19 #include "ionic_if.h" 20 #include "ionic_dev.h" 21 #include "ionic_lif.h" 22 #include "ionic_rxtx.h" 23 24 static __rte_always_inline void 25 ionic_tx_flush(struct ionic_tx_qcq *txq) 26 { 27 struct ionic_cq *cq = &txq->qcq.cq; 28 struct ionic_queue *q = &txq->qcq.q; 29 struct ionic_tx_stats *stats = &txq->stats; 30 struct rte_mbuf *txm; 31 struct ionic_txq_comp *cq_desc, *cq_desc_base = cq->base; 32 void **info; 33 34 cq_desc = &cq_desc_base[cq->tail_idx]; 35 36 while (color_match(cq_desc->color, cq->done_color)) { 37 cq->tail_idx = Q_NEXT_TO_SRVC(cq, 1); 38 if (cq->tail_idx == 0) 39 cq->done_color = !cq->done_color; 40 41 /* Prefetch 4 x 16B comp at cq->tail_idx + 4 */ 42 if ((cq->tail_idx & 0x3) == 0) 43 rte_prefetch0(&cq_desc_base[Q_NEXT_TO_SRVC(cq, 4)]); 44 45 while (q->tail_idx != rte_le_to_cpu_16(cq_desc->comp_index)) { 46 /* Prefetch 8 mbuf ptrs at q->tail_idx + 2 */ 47 rte_prefetch0(&q->info[Q_NEXT_TO_SRVC(q, 2)]); 48 49 /* Prefetch next mbuf */ 50 void **next_info = 51 &q->info[Q_NEXT_TO_SRVC(q, 1)]; 52 if (next_info[0]) 53 rte_mbuf_prefetch_part2(next_info[0]); 54 55 info = &q->info[q->tail_idx]; 56 { 57 txm = info[0]; 58 59 if (txq->flags & IONIC_QCQ_F_FAST_FREE) 60 rte_mempool_put(txm->pool, txm); 61 else 62 rte_pktmbuf_free_seg(txm); 63 64 info[0] = NULL; 65 } 66 67 q->tail_idx = Q_NEXT_TO_SRVC(q, 1); 68 } 69 70 cq_desc = &cq_desc_base[cq->tail_idx]; 71 stats->comps++; 72 } 73 } 74 75 static __rte_always_inline int 76 ionic_tx(struct ionic_tx_qcq *txq, struct rte_mbuf *txm) 77 { 78 struct ionic_queue *q = &txq->qcq.q; 79 struct ionic_txq_desc *desc, *desc_base = q->base; 80 struct ionic_tx_stats *stats = &txq->stats; 81 void **info; 82 uint64_t ol_flags = txm->ol_flags; 83 uint64_t addr, cmd; 84 uint8_t opcode = IONIC_TXQ_DESC_OPCODE_CSUM_NONE; 85 uint8_t flags = 0; 86 87 if (txm->nb_segs > 1) 88 return -EINVAL; 89 90 desc = &desc_base[q->head_idx]; 91 info = &q->info[q->head_idx]; 92 93 if ((ol_flags & RTE_MBUF_F_TX_IP_CKSUM) && 94 (txq->flags & IONIC_QCQ_F_CSUM_L3)) { 95 opcode = IONIC_TXQ_DESC_OPCODE_CSUM_HW; 96 flags |= IONIC_TXQ_DESC_FLAG_CSUM_L3; 97 } 98 99 if (((ol_flags & RTE_MBUF_F_TX_TCP_CKSUM) && 100 (txq->flags & IONIC_QCQ_F_CSUM_TCP)) || 101 ((ol_flags & RTE_MBUF_F_TX_UDP_CKSUM) && 102 (txq->flags & IONIC_QCQ_F_CSUM_UDP))) { 103 opcode = IONIC_TXQ_DESC_OPCODE_CSUM_HW; 104 flags |= IONIC_TXQ_DESC_FLAG_CSUM_L4; 105 } 106 107 if (opcode == IONIC_TXQ_DESC_OPCODE_CSUM_NONE) 108 stats->no_csum++; 109 110 if (((ol_flags & RTE_MBUF_F_TX_OUTER_IP_CKSUM) || 111 (ol_flags & RTE_MBUF_F_TX_OUTER_UDP_CKSUM)) && 112 ((ol_flags & RTE_MBUF_F_TX_OUTER_IPV4) || 113 (ol_flags & RTE_MBUF_F_TX_OUTER_IPV6))) { 114 flags |= IONIC_TXQ_DESC_FLAG_ENCAP; 115 } 116 117 if (ol_flags & RTE_MBUF_F_TX_VLAN) { 118 flags |= IONIC_TXQ_DESC_FLAG_VLAN; 119 desc->vlan_tci = rte_cpu_to_le_16(txm->vlan_tci); 120 } 121 122 addr = rte_cpu_to_le_64(rte_mbuf_data_iova(txm)); 123 124 cmd = encode_txq_desc_cmd(opcode, flags, 0, addr); 125 desc->cmd = rte_cpu_to_le_64(cmd); 126 desc->len = rte_cpu_to_le_16(txm->data_len); 127 128 info[0] = txm; 129 130 q->head_idx = Q_NEXT_TO_POST(q, 1); 131 132 return 0; 133 } 134 135 uint16_t 136 ionic_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 137 uint16_t nb_pkts) 138 { 139 struct ionic_tx_qcq *txq = tx_queue; 140 struct ionic_queue *q = &txq->qcq.q; 141 struct ionic_tx_stats *stats = &txq->stats; 142 struct rte_mbuf *mbuf; 143 uint32_t bytes_tx = 0; 144 uint16_t nb_avail, nb_tx = 0; 145 uint64_t then, now, hz, delta; 146 int err; 147 148 struct ionic_txq_desc *desc_base = q->base; 149 if (!(txq->flags & IONIC_QCQ_F_CMB)) 150 rte_prefetch0(&desc_base[q->head_idx]); 151 rte_prefetch0(&q->info[q->head_idx]); 152 153 if (nb_pkts) { 154 rte_mbuf_prefetch_part1(tx_pkts[0]); 155 rte_mbuf_prefetch_part2(tx_pkts[0]); 156 } 157 158 if (ionic_q_space_avail(q) < txq->free_thresh) { 159 /* Cleaning old buffers */ 160 ionic_tx_flush(txq); 161 } 162 163 nb_avail = ionic_q_space_avail(q); 164 if (nb_avail < nb_pkts) { 165 stats->stop += nb_pkts - nb_avail; 166 nb_pkts = nb_avail; 167 } 168 169 while (nb_tx < nb_pkts) { 170 uint16_t next_idx = Q_NEXT_TO_POST(q, 1); 171 if (!(txq->flags & IONIC_QCQ_F_CMB)) 172 rte_prefetch0(&desc_base[next_idx]); 173 rte_prefetch0(&q->info[next_idx]); 174 175 if (nb_tx + 1 < nb_pkts) { 176 rte_mbuf_prefetch_part1(tx_pkts[nb_tx + 1]); 177 rte_mbuf_prefetch_part2(tx_pkts[nb_tx + 1]); 178 } 179 180 mbuf = tx_pkts[nb_tx]; 181 182 if (mbuf->ol_flags & RTE_MBUF_F_TX_TCP_SEG) 183 err = ionic_tx_tso(txq, mbuf); 184 else 185 err = ionic_tx(txq, mbuf); 186 if (err) { 187 stats->drop += nb_pkts - nb_tx; 188 break; 189 } 190 191 bytes_tx += mbuf->pkt_len; 192 nb_tx++; 193 } 194 195 if (nb_tx > 0) { 196 rte_wmb(); 197 ionic_q_flush(q); 198 199 txq->last_wdog_cycles = rte_get_timer_cycles(); 200 201 stats->packets += nb_tx; 202 stats->bytes += bytes_tx; 203 } else { 204 /* 205 * Ring the doorbell again if no work could be posted and work 206 * is still pending after the deadline. 207 */ 208 if (q->head_idx != q->tail_idx) { 209 then = txq->last_wdog_cycles; 210 now = rte_get_timer_cycles(); 211 hz = rte_get_timer_hz(); 212 delta = (now - then) * 1000; 213 214 if (delta >= hz * IONIC_Q_WDOG_MS) { 215 ionic_q_flush(q); 216 txq->last_wdog_cycles = now; 217 } 218 } 219 } 220 221 return nb_tx; 222 } 223 224 /* 225 * Cleans one descriptor. Connects the filled mbufs into a chain. 226 * Does not advance the tail index. 227 */ 228 static __rte_always_inline void 229 ionic_rx_clean_one(struct ionic_rx_qcq *rxq, 230 struct ionic_rxq_comp *cq_desc, 231 struct ionic_rx_service *rx_svc) 232 { 233 struct ionic_queue *q = &rxq->qcq.q; 234 struct rte_mbuf *rxm; 235 struct ionic_rx_stats *stats = &rxq->stats; 236 uint64_t pkt_flags = 0; 237 uint32_t pkt_type; 238 uint16_t cq_desc_len; 239 uint8_t ptype, cflags; 240 void **info; 241 242 cq_desc_len = rte_le_to_cpu_16(cq_desc->len); 243 244 info = &q->info[q->tail_idx]; 245 246 rxm = info[0]; 247 248 if (cq_desc->status) { 249 stats->bad_cq_status++; 250 return; 251 } 252 253 if (cq_desc_len > rxq->frame_size || cq_desc_len == 0) { 254 stats->bad_len++; 255 return; 256 } 257 258 info[0] = NULL; 259 260 /* Set the mbuf metadata based on the cq entry */ 261 rxm->rearm_data[0] = rxq->rearm_data; 262 rxm->pkt_len = cq_desc_len; 263 rxm->data_len = cq_desc_len; 264 265 /* RSS */ 266 pkt_flags |= RTE_MBUF_F_RX_RSS_HASH; 267 rxm->hash.rss = rte_le_to_cpu_32(cq_desc->rss_hash); 268 269 /* Vlan Strip */ 270 if (cq_desc->csum_flags & IONIC_RXQ_COMP_CSUM_F_VLAN) { 271 pkt_flags |= RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED; 272 rxm->vlan_tci = rte_le_to_cpu_16(cq_desc->vlan_tci); 273 } 274 275 /* Checksum */ 276 if (cq_desc->csum_flags & IONIC_RXQ_COMP_CSUM_F_CALC) { 277 cflags = cq_desc->csum_flags & IONIC_CSUM_FLAG_MASK; 278 pkt_flags |= ionic_csum_flags[cflags]; 279 } 280 281 rxm->ol_flags = pkt_flags; 282 283 /* Packet Type */ 284 ptype = cq_desc->pkt_type_color & IONIC_RXQ_COMP_PKT_TYPE_MASK; 285 pkt_type = ionic_ptype_table[ptype]; 286 if (pkt_type == RTE_PTYPE_UNKNOWN) { 287 struct rte_ether_hdr *eth_h = rte_pktmbuf_mtod(rxm, 288 struct rte_ether_hdr *); 289 uint16_t ether_type = eth_h->ether_type; 290 if (ether_type == rte_cpu_to_be_16(RTE_ETHER_TYPE_ARP)) 291 pkt_type = RTE_PTYPE_L2_ETHER_ARP; 292 else if (ether_type == rte_cpu_to_be_16(RTE_ETHER_TYPE_LLDP)) 293 pkt_type = RTE_PTYPE_L2_ETHER_LLDP; 294 else if (ether_type == rte_cpu_to_be_16(RTE_ETHER_TYPE_1588)) 295 pkt_type = RTE_PTYPE_L2_ETHER_TIMESYNC; 296 stats->mtods++; 297 } else if (pkt_flags & RTE_MBUF_F_RX_VLAN) { 298 pkt_type |= RTE_PTYPE_L2_ETHER_VLAN; 299 } else { 300 pkt_type |= RTE_PTYPE_L2_ETHER; 301 } 302 303 rxm->packet_type = pkt_type; 304 305 rx_svc->rx_pkts[rx_svc->nb_rx] = rxm; 306 rx_svc->nb_rx++; 307 308 stats->packets++; 309 stats->bytes += rxm->pkt_len; 310 } 311 312 /* 313 * Fills one descriptor with mbufs. Does not advance the head index. 314 */ 315 static __rte_always_inline int 316 ionic_rx_fill_one(struct ionic_rx_qcq *rxq) 317 { 318 struct ionic_queue *q = &rxq->qcq.q; 319 struct rte_mbuf *rxm; 320 struct ionic_rxq_desc *desc, *desc_base = q->base; 321 rte_iova_t data_iova; 322 void **info; 323 int ret; 324 325 info = &q->info[q->head_idx]; 326 desc = &desc_base[q->head_idx]; 327 328 /* mbuf is unused */ 329 if (info[0]) 330 return 0; 331 332 if (rxq->mb_idx == 0) { 333 ret = rte_mempool_get_bulk(rxq->mb_pool, 334 (void **)rxq->mbs, 335 IONIC_MBUF_BULK_ALLOC); 336 if (ret) { 337 assert(0); 338 return -ENOMEM; 339 } 340 341 rxq->mb_idx = IONIC_MBUF_BULK_ALLOC; 342 } 343 344 rxm = rxq->mbs[--rxq->mb_idx]; 345 info[0] = rxm; 346 347 data_iova = rte_mbuf_data_iova_default(rxm); 348 desc->addr = rte_cpu_to_le_64(data_iova); 349 350 return 0; 351 } 352 353 /* 354 * Walk the CQ to find completed receive descriptors. 355 * Any completed descriptor found is refilled. 356 */ 357 static __rte_always_inline void 358 ionic_rxq_service(struct ionic_rx_qcq *rxq, uint32_t work_to_do, 359 struct ionic_rx_service *rx_svc) 360 { 361 struct ionic_cq *cq = &rxq->qcq.cq; 362 struct ionic_queue *q = &rxq->qcq.q; 363 struct ionic_rxq_desc *q_desc_base = q->base; 364 struct ionic_rxq_comp *cq_desc, *cq_desc_base = cq->base; 365 uint32_t work_done = 0; 366 uint64_t then, now, hz, delta; 367 368 cq_desc = &cq_desc_base[cq->tail_idx]; 369 370 while (color_match(cq_desc->pkt_type_color, cq->done_color)) { 371 cq->tail_idx = Q_NEXT_TO_SRVC(cq, 1); 372 if (cq->tail_idx == 0) 373 cq->done_color = !cq->done_color; 374 375 /* Prefetch 8 x 8B bufinfo */ 376 rte_prefetch0(&q->info[Q_NEXT_TO_SRVC(q, 8)]); 377 /* Prefetch 4 x 16B comp */ 378 rte_prefetch0(&cq_desc_base[Q_NEXT_TO_SRVC(cq, 4)]); 379 /* Prefetch 4 x 16B descriptors */ 380 if (!(rxq->flags & IONIC_QCQ_F_CMB)) 381 rte_prefetch0(&q_desc_base[Q_NEXT_TO_POST(q, 4)]); 382 383 /* Clean one descriptor */ 384 ionic_rx_clean_one(rxq, cq_desc, rx_svc); 385 q->tail_idx = Q_NEXT_TO_SRVC(q, 1); 386 387 /* Fill one descriptor */ 388 (void)ionic_rx_fill_one(rxq); 389 390 q->head_idx = Q_NEXT_TO_POST(q, 1); 391 392 if (++work_done == work_to_do) 393 break; 394 395 cq_desc = &cq_desc_base[cq->tail_idx]; 396 } 397 398 /* Update the queue indices and ring the doorbell */ 399 if (work_done) { 400 ionic_q_flush(q); 401 rxq->last_wdog_cycles = rte_get_timer_cycles(); 402 rxq->wdog_ms = IONIC_Q_WDOG_MS; 403 } else { 404 /* 405 * Ring the doorbell again if no recvs were posted and the 406 * recv queue is not empty after the deadline. 407 * 408 * Exponentially back off the deadline to avoid excessive 409 * doorbells when the recv queue is idle. 410 */ 411 if (q->head_idx != q->tail_idx) { 412 then = rxq->last_wdog_cycles; 413 now = rte_get_timer_cycles(); 414 hz = rte_get_timer_hz(); 415 delta = (now - then) * 1000; 416 417 if (delta >= hz * rxq->wdog_ms) { 418 ionic_q_flush(q); 419 rxq->last_wdog_cycles = now; 420 421 delta = 2 * rxq->wdog_ms; 422 if (delta > IONIC_Q_WDOG_MAX_MS) 423 delta = IONIC_Q_WDOG_MAX_MS; 424 425 rxq->wdog_ms = delta; 426 } 427 } 428 } 429 } 430 431 uint16_t 432 ionic_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 433 uint16_t nb_pkts) 434 { 435 struct ionic_rx_qcq *rxq = rx_queue; 436 struct ionic_rx_service rx_svc; 437 438 rx_svc.rx_pkts = rx_pkts; 439 rx_svc.nb_rx = 0; 440 441 ionic_rxq_service(rxq, nb_pkts, &rx_svc); 442 443 return rx_svc.nb_rx; 444 } 445 446 /* 447 * Fills all descriptors with mbufs. 448 */ 449 int __rte_cold 450 ionic_rx_fill(struct ionic_rx_qcq *rxq) 451 { 452 struct ionic_queue *q = &rxq->qcq.q; 453 uint32_t i; 454 int err = 0; 455 456 for (i = 0; i < q->num_descs - 1u; i++) { 457 err = ionic_rx_fill_one(rxq); 458 if (err) 459 break; 460 461 q->head_idx = Q_NEXT_TO_POST(q, 1); 462 } 463 464 ionic_q_flush(q); 465 466 return err; 467 } 468