1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018-2022 Advanced Micro Devices, Inc. 3 */ 4 5 #include <stdio.h> 6 #include <errno.h> 7 #include <stdint.h> 8 #include <assert.h> 9 10 #include <rte_common.h> 11 #include <rte_byteorder.h> 12 #include <rte_atomic.h> 13 #include <rte_mempool.h> 14 #include <rte_mbuf.h> 15 #include <rte_ether.h> 16 #include <rte_prefetch.h> 17 18 #include "ionic.h" 19 #include "ionic_if.h" 20 #include "ionic_dev.h" 21 #include "ionic_lif.h" 22 #include "ionic_rxtx.h" 23 24 static __rte_always_inline void 25 ionic_tx_flush(struct ionic_tx_qcq *txq) 26 { 27 struct ionic_cq *cq = &txq->qcq.cq; 28 struct ionic_queue *q = &txq->qcq.q; 29 struct rte_mbuf *txm; 30 struct ionic_txq_comp *cq_desc, *cq_desc_base = cq->base; 31 void **info; 32 33 cq_desc = &cq_desc_base[cq->tail_idx]; 34 35 while (color_match(cq_desc->color, cq->done_color)) { 36 cq->tail_idx = Q_NEXT_TO_SRVC(cq, 1); 37 if (cq->tail_idx == 0) 38 cq->done_color = !cq->done_color; 39 40 /* Prefetch 4 x 16B comp at cq->tail_idx + 4 */ 41 if ((cq->tail_idx & 0x3) == 0) 42 rte_prefetch0(&cq_desc_base[Q_NEXT_TO_SRVC(cq, 4)]); 43 44 while (q->tail_idx != rte_le_to_cpu_16(cq_desc->comp_index)) { 45 /* Prefetch 8 mbuf ptrs at q->tail_idx + 2 */ 46 rte_prefetch0(&q->info[Q_NEXT_TO_SRVC(q, 2)]); 47 48 /* Prefetch next mbuf */ 49 void **next_info = 50 &q->info[Q_NEXT_TO_SRVC(q, 1)]; 51 if (next_info[0]) 52 rte_mbuf_prefetch_part2(next_info[0]); 53 54 info = &q->info[q->tail_idx]; 55 { 56 txm = info[0]; 57 58 if (txq->flags & IONIC_QCQ_F_FAST_FREE) 59 rte_mempool_put(txm->pool, txm); 60 else 61 rte_pktmbuf_free_seg(txm); 62 63 info[0] = NULL; 64 } 65 66 q->tail_idx = Q_NEXT_TO_SRVC(q, 1); 67 } 68 69 cq_desc = &cq_desc_base[cq->tail_idx]; 70 } 71 } 72 73 static __rte_always_inline int 74 ionic_tx(struct ionic_tx_qcq *txq, struct rte_mbuf *txm) 75 { 76 struct ionic_queue *q = &txq->qcq.q; 77 struct ionic_txq_desc *desc, *desc_base = q->base; 78 struct ionic_tx_stats *stats = &txq->stats; 79 void **info; 80 uint64_t ol_flags = txm->ol_flags; 81 uint64_t addr, cmd; 82 uint8_t opcode = IONIC_TXQ_DESC_OPCODE_CSUM_NONE; 83 uint8_t flags = 0; 84 85 if (txm->nb_segs > 1) 86 return -EINVAL; 87 88 desc = &desc_base[q->head_idx]; 89 info = &q->info[q->head_idx]; 90 91 if ((ol_flags & RTE_MBUF_F_TX_IP_CKSUM) && 92 (txq->flags & IONIC_QCQ_F_CSUM_L3)) { 93 opcode = IONIC_TXQ_DESC_OPCODE_CSUM_HW; 94 flags |= IONIC_TXQ_DESC_FLAG_CSUM_L3; 95 } 96 97 if (((ol_flags & RTE_MBUF_F_TX_TCP_CKSUM) && 98 (txq->flags & IONIC_QCQ_F_CSUM_TCP)) || 99 ((ol_flags & RTE_MBUF_F_TX_UDP_CKSUM) && 100 (txq->flags & IONIC_QCQ_F_CSUM_UDP))) { 101 opcode = IONIC_TXQ_DESC_OPCODE_CSUM_HW; 102 flags |= IONIC_TXQ_DESC_FLAG_CSUM_L4; 103 } 104 105 if (opcode == IONIC_TXQ_DESC_OPCODE_CSUM_NONE) 106 stats->no_csum++; 107 108 if (((ol_flags & RTE_MBUF_F_TX_OUTER_IP_CKSUM) || 109 (ol_flags & RTE_MBUF_F_TX_OUTER_UDP_CKSUM)) && 110 ((ol_flags & RTE_MBUF_F_TX_OUTER_IPV4) || 111 (ol_flags & RTE_MBUF_F_TX_OUTER_IPV6))) { 112 flags |= IONIC_TXQ_DESC_FLAG_ENCAP; 113 } 114 115 if (ol_flags & RTE_MBUF_F_TX_VLAN) { 116 flags |= IONIC_TXQ_DESC_FLAG_VLAN; 117 desc->vlan_tci = rte_cpu_to_le_16(txm->vlan_tci); 118 } 119 120 addr = rte_cpu_to_le_64(rte_mbuf_data_iova(txm)); 121 122 cmd = encode_txq_desc_cmd(opcode, flags, 0, addr); 123 desc->cmd = rte_cpu_to_le_64(cmd); 124 desc->len = rte_cpu_to_le_16(txm->data_len); 125 126 info[0] = txm; 127 128 q->head_idx = Q_NEXT_TO_POST(q, 1); 129 130 return 0; 131 } 132 133 uint16_t 134 ionic_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 135 uint16_t nb_pkts) 136 { 137 struct ionic_tx_qcq *txq = tx_queue; 138 struct ionic_queue *q = &txq->qcq.q; 139 struct ionic_tx_stats *stats = &txq->stats; 140 struct rte_mbuf *mbuf; 141 uint32_t bytes_tx = 0; 142 uint16_t nb_avail, nb_tx = 0; 143 uint64_t then, now, hz, delta; 144 int err; 145 146 struct ionic_txq_desc *desc_base = q->base; 147 if (!(txq->flags & IONIC_QCQ_F_CMB)) 148 rte_prefetch0(&desc_base[q->head_idx]); 149 rte_prefetch0(&q->info[q->head_idx]); 150 151 if (nb_pkts) { 152 rte_mbuf_prefetch_part1(tx_pkts[0]); 153 rte_mbuf_prefetch_part2(tx_pkts[0]); 154 } 155 156 if (ionic_q_space_avail(q) < txq->free_thresh) { 157 /* Cleaning old buffers */ 158 ionic_tx_flush(txq); 159 } 160 161 nb_avail = ionic_q_space_avail(q); 162 if (nb_avail < nb_pkts) { 163 stats->stop += nb_pkts - nb_avail; 164 nb_pkts = nb_avail; 165 } 166 167 while (nb_tx < nb_pkts) { 168 uint16_t next_idx = Q_NEXT_TO_POST(q, 1); 169 if (!(txq->flags & IONIC_QCQ_F_CMB)) 170 rte_prefetch0(&desc_base[next_idx]); 171 rte_prefetch0(&q->info[next_idx]); 172 173 if (nb_tx + 1 < nb_pkts) { 174 rte_mbuf_prefetch_part1(tx_pkts[nb_tx + 1]); 175 rte_mbuf_prefetch_part2(tx_pkts[nb_tx + 1]); 176 } 177 178 mbuf = tx_pkts[nb_tx]; 179 180 if (mbuf->ol_flags & RTE_MBUF_F_TX_TCP_SEG) 181 err = ionic_tx_tso(txq, mbuf); 182 else 183 err = ionic_tx(txq, mbuf); 184 if (err) { 185 stats->drop += nb_pkts - nb_tx; 186 break; 187 } 188 189 bytes_tx += mbuf->pkt_len; 190 nb_tx++; 191 } 192 193 if (nb_tx > 0) { 194 rte_wmb(); 195 ionic_q_flush(q); 196 197 txq->last_wdog_cycles = rte_get_timer_cycles(); 198 199 stats->packets += nb_tx; 200 stats->bytes += bytes_tx; 201 } else { 202 /* 203 * Ring the doorbell again if no work could be posted and work 204 * is still pending after the deadline. 205 */ 206 if (q->head_idx != q->tail_idx) { 207 then = txq->last_wdog_cycles; 208 now = rte_get_timer_cycles(); 209 hz = rte_get_timer_hz(); 210 delta = (now - then) * 1000; 211 212 if (delta >= hz * IONIC_Q_WDOG_MS) { 213 ionic_q_flush(q); 214 txq->last_wdog_cycles = now; 215 } 216 } 217 } 218 219 return nb_tx; 220 } 221 222 /* 223 * Cleans one descriptor. Connects the filled mbufs into a chain. 224 * Does not advance the tail index. 225 */ 226 static __rte_always_inline void 227 ionic_rx_clean_one(struct ionic_rx_qcq *rxq, 228 struct ionic_rxq_comp *cq_desc, 229 struct ionic_rx_service *rx_svc) 230 { 231 struct ionic_queue *q = &rxq->qcq.q; 232 struct rte_mbuf *rxm; 233 struct ionic_rx_stats *stats = &rxq->stats; 234 uint64_t pkt_flags = 0; 235 uint32_t pkt_type; 236 uint16_t cq_desc_len; 237 uint8_t ptype, cflags; 238 void **info; 239 240 cq_desc_len = rte_le_to_cpu_16(cq_desc->len); 241 242 info = &q->info[q->tail_idx]; 243 244 rxm = info[0]; 245 246 if (cq_desc->status) { 247 stats->bad_cq_status++; 248 return; 249 } 250 251 if (cq_desc_len > rxq->frame_size || cq_desc_len == 0) { 252 stats->bad_len++; 253 return; 254 } 255 256 info[0] = NULL; 257 258 /* Set the mbuf metadata based on the cq entry */ 259 rxm->rearm_data[0] = rxq->rearm_data; 260 rxm->pkt_len = cq_desc_len; 261 rxm->data_len = cq_desc_len; 262 263 /* RSS */ 264 pkt_flags |= RTE_MBUF_F_RX_RSS_HASH; 265 rxm->hash.rss = rte_le_to_cpu_32(cq_desc->rss_hash); 266 267 /* Vlan Strip */ 268 if (cq_desc->csum_flags & IONIC_RXQ_COMP_CSUM_F_VLAN) { 269 pkt_flags |= RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED; 270 rxm->vlan_tci = rte_le_to_cpu_16(cq_desc->vlan_tci); 271 } 272 273 /* Checksum */ 274 if (cq_desc->csum_flags & IONIC_RXQ_COMP_CSUM_F_CALC) { 275 cflags = cq_desc->csum_flags & IONIC_CSUM_FLAG_MASK; 276 pkt_flags |= ionic_csum_flags[cflags]; 277 } 278 279 rxm->ol_flags = pkt_flags; 280 281 /* Packet Type */ 282 ptype = cq_desc->pkt_type_color & IONIC_RXQ_COMP_PKT_TYPE_MASK; 283 pkt_type = ionic_ptype_table[ptype]; 284 if (pkt_type == RTE_PTYPE_UNKNOWN) { 285 struct rte_ether_hdr *eth_h = rte_pktmbuf_mtod(rxm, 286 struct rte_ether_hdr *); 287 uint16_t ether_type = eth_h->ether_type; 288 if (ether_type == rte_cpu_to_be_16(RTE_ETHER_TYPE_ARP)) 289 pkt_type = RTE_PTYPE_L2_ETHER_ARP; 290 else if (ether_type == rte_cpu_to_be_16(RTE_ETHER_TYPE_LLDP)) 291 pkt_type = RTE_PTYPE_L2_ETHER_LLDP; 292 else if (ether_type == rte_cpu_to_be_16(RTE_ETHER_TYPE_1588)) 293 pkt_type = RTE_PTYPE_L2_ETHER_TIMESYNC; 294 stats->mtods++; 295 } else if (pkt_flags & RTE_MBUF_F_RX_VLAN) { 296 pkt_type |= RTE_PTYPE_L2_ETHER_VLAN; 297 } else { 298 pkt_type |= RTE_PTYPE_L2_ETHER; 299 } 300 301 rxm->packet_type = pkt_type; 302 303 rx_svc->rx_pkts[rx_svc->nb_rx] = rxm; 304 rx_svc->nb_rx++; 305 306 stats->packets++; 307 stats->bytes += rxm->pkt_len; 308 } 309 310 /* 311 * Fills one descriptor with mbufs. Does not advance the head index. 312 */ 313 static __rte_always_inline int 314 ionic_rx_fill_one(struct ionic_rx_qcq *rxq) 315 { 316 struct ionic_queue *q = &rxq->qcq.q; 317 struct rte_mbuf *rxm; 318 struct ionic_rxq_desc *desc, *desc_base = q->base; 319 rte_iova_t data_iova; 320 void **info; 321 int ret; 322 323 info = &q->info[q->head_idx]; 324 desc = &desc_base[q->head_idx]; 325 326 /* mbuf is unused */ 327 if (info[0]) 328 return 0; 329 330 if (rxq->mb_idx == 0) { 331 ret = rte_mempool_get_bulk(rxq->mb_pool, 332 (void **)rxq->mbs, 333 IONIC_MBUF_BULK_ALLOC); 334 if (ret) { 335 assert(0); 336 return -ENOMEM; 337 } 338 339 rxq->mb_idx = IONIC_MBUF_BULK_ALLOC; 340 } 341 342 rxm = rxq->mbs[--rxq->mb_idx]; 343 info[0] = rxm; 344 345 data_iova = rte_mbuf_data_iova_default(rxm); 346 desc->addr = rte_cpu_to_le_64(data_iova); 347 348 return 0; 349 } 350 351 /* 352 * Walk the CQ to find completed receive descriptors. 353 * Any completed descriptor found is refilled. 354 */ 355 static __rte_always_inline void 356 ionic_rxq_service(struct ionic_rx_qcq *rxq, uint32_t work_to_do, 357 struct ionic_rx_service *rx_svc) 358 { 359 struct ionic_cq *cq = &rxq->qcq.cq; 360 struct ionic_queue *q = &rxq->qcq.q; 361 struct ionic_rxq_desc *q_desc_base = q->base; 362 struct ionic_rxq_comp *cq_desc, *cq_desc_base = cq->base; 363 uint32_t work_done = 0; 364 uint64_t then, now, hz, delta; 365 366 cq_desc = &cq_desc_base[cq->tail_idx]; 367 368 while (color_match(cq_desc->pkt_type_color, cq->done_color)) { 369 cq->tail_idx = Q_NEXT_TO_SRVC(cq, 1); 370 if (cq->tail_idx == 0) 371 cq->done_color = !cq->done_color; 372 373 /* Prefetch 8 x 8B bufinfo */ 374 rte_prefetch0(&q->info[Q_NEXT_TO_SRVC(q, 8)]); 375 /* Prefetch 4 x 16B comp */ 376 rte_prefetch0(&cq_desc_base[Q_NEXT_TO_SRVC(cq, 4)]); 377 /* Prefetch 4 x 16B descriptors */ 378 if (!(rxq->flags & IONIC_QCQ_F_CMB)) 379 rte_prefetch0(&q_desc_base[Q_NEXT_TO_POST(q, 4)]); 380 381 /* Clean one descriptor */ 382 ionic_rx_clean_one(rxq, cq_desc, rx_svc); 383 q->tail_idx = Q_NEXT_TO_SRVC(q, 1); 384 385 /* Fill one descriptor */ 386 (void)ionic_rx_fill_one(rxq); 387 388 q->head_idx = Q_NEXT_TO_POST(q, 1); 389 390 if (++work_done == work_to_do) 391 break; 392 393 cq_desc = &cq_desc_base[cq->tail_idx]; 394 } 395 396 /* Update the queue indices and ring the doorbell */ 397 if (work_done) { 398 ionic_q_flush(q); 399 rxq->last_wdog_cycles = rte_get_timer_cycles(); 400 rxq->wdog_ms = IONIC_Q_WDOG_MS; 401 } else { 402 /* 403 * Ring the doorbell again if no recvs were posted and the 404 * recv queue is not empty after the deadline. 405 * 406 * Exponentially back off the deadline to avoid excessive 407 * doorbells when the recv queue is idle. 408 */ 409 if (q->head_idx != q->tail_idx) { 410 then = rxq->last_wdog_cycles; 411 now = rte_get_timer_cycles(); 412 hz = rte_get_timer_hz(); 413 delta = (now - then) * 1000; 414 415 if (delta >= hz * rxq->wdog_ms) { 416 ionic_q_flush(q); 417 rxq->last_wdog_cycles = now; 418 419 delta = 2 * rxq->wdog_ms; 420 if (delta > IONIC_Q_WDOG_MAX_MS) 421 delta = IONIC_Q_WDOG_MAX_MS; 422 423 rxq->wdog_ms = delta; 424 } 425 } 426 } 427 } 428 429 uint16_t 430 ionic_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 431 uint16_t nb_pkts) 432 { 433 struct ionic_rx_qcq *rxq = rx_queue; 434 struct ionic_rx_service rx_svc; 435 436 rx_svc.rx_pkts = rx_pkts; 437 rx_svc.nb_rx = 0; 438 439 ionic_rxq_service(rxq, nb_pkts, &rx_svc); 440 441 return rx_svc.nb_rx; 442 } 443 444 /* 445 * Fills all descriptors with mbufs. 446 */ 447 int __rte_cold 448 ionic_rx_fill(struct ionic_rx_qcq *rxq) 449 { 450 struct ionic_queue *q = &rxq->qcq.q; 451 uint32_t i; 452 int err = 0; 453 454 for (i = 0; i < q->num_descs - 1u; i++) { 455 err = ionic_rx_fill_one(rxq); 456 if (err) 457 break; 458 459 q->head_idx = Q_NEXT_TO_POST(q, 1); 460 } 461 462 ionic_q_flush(q); 463 464 return err; 465 } 466