1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018-2022 Advanced Micro Devices, Inc. 3 */ 4 5 #include <stdio.h> 6 #include <errno.h> 7 #include <stdint.h> 8 #include <assert.h> 9 10 #include <rte_common.h> 11 #include <rte_byteorder.h> 12 #include <rte_atomic.h> 13 #include <rte_mempool.h> 14 #include <rte_mbuf.h> 15 #include <rte_ether.h> 16 #include <rte_prefetch.h> 17 18 #include "ionic.h" 19 #include "ionic_if.h" 20 #include "ionic_dev.h" 21 #include "ionic_lif.h" 22 #include "ionic_rxtx.h" 23 24 static __rte_always_inline void 25 ionic_tx_flush_sg(struct ionic_tx_qcq *txq) 26 { 27 struct ionic_cq *cq = &txq->qcq.cq; 28 struct ionic_queue *q = &txq->qcq.q; 29 struct ionic_tx_stats *stats = &txq->stats; 30 struct rte_mbuf *txm; 31 struct ionic_txq_comp *cq_desc_base = cq->base; 32 volatile struct ionic_txq_comp *cq_desc; 33 void **info; 34 uint32_t i; 35 36 cq_desc = &cq_desc_base[cq->tail_idx]; 37 38 while (color_match(cq_desc->color, cq->done_color)) { 39 cq->tail_idx = Q_NEXT_TO_SRVC(cq, 1); 40 if (cq->tail_idx == 0) 41 cq->done_color = !cq->done_color; 42 43 /* Prefetch 4 x 16B comp at cq->tail_idx + 4 */ 44 if ((cq->tail_idx & 0x3) == 0) 45 rte_prefetch0(&cq_desc_base[Q_NEXT_TO_SRVC(cq, 4)]); 46 47 while (q->tail_idx != rte_le_to_cpu_16(cq_desc->comp_index)) { 48 /* Prefetch 8 mbuf ptrs at q->tail_idx + 2 */ 49 rte_prefetch0(IONIC_INFO_PTR(q, Q_NEXT_TO_SRVC(q, 2))); 50 51 /* Prefetch next mbuf */ 52 void **next_info = 53 IONIC_INFO_PTR(q, Q_NEXT_TO_SRVC(q, 1)); 54 if (next_info[0]) 55 rte_mbuf_prefetch_part2(next_info[0]); 56 if (next_info[1]) 57 rte_mbuf_prefetch_part2(next_info[1]); 58 59 info = IONIC_INFO_PTR(q, q->tail_idx); 60 for (i = 0; i < q->num_segs; i++) { 61 txm = info[i]; 62 if (!txm) 63 break; 64 65 if (txq->flags & IONIC_QCQ_F_FAST_FREE) 66 rte_mempool_put(txm->pool, txm); 67 else 68 rte_pktmbuf_free_seg(txm); 69 70 info[i] = NULL; 71 } 72 73 q->tail_idx = Q_NEXT_TO_SRVC(q, 1); 74 } 75 76 cq_desc = &cq_desc_base[cq->tail_idx]; 77 stats->comps++; 78 } 79 } 80 81 static __rte_always_inline int 82 ionic_tx_sg(struct ionic_tx_qcq *txq, struct rte_mbuf *txm) 83 { 84 struct ionic_queue *q = &txq->qcq.q; 85 struct ionic_txq_desc *desc, *desc_base = q->base; 86 struct ionic_txq_sg_desc_v1 *sg_desc, *sg_desc_base = q->sg_base; 87 struct ionic_txq_sg_elem *elem; 88 struct ionic_tx_stats *stats = &txq->stats; 89 struct rte_mbuf *txm_seg; 90 rte_iova_t data_iova; 91 void **info; 92 uint64_t ol_flags = txm->ol_flags; 93 uint64_t addr, cmd; 94 uint8_t opcode = IONIC_TXQ_DESC_OPCODE_CSUM_NONE; 95 uint8_t flags = 0; 96 97 desc = &desc_base[q->head_idx]; 98 sg_desc = &sg_desc_base[q->head_idx]; 99 info = IONIC_INFO_PTR(q, q->head_idx); 100 101 if ((ol_flags & RTE_MBUF_F_TX_IP_CKSUM) && 102 (txq->flags & IONIC_QCQ_F_CSUM_L3)) { 103 opcode = IONIC_TXQ_DESC_OPCODE_CSUM_HW; 104 flags |= IONIC_TXQ_DESC_FLAG_CSUM_L3; 105 } 106 107 if (((ol_flags & RTE_MBUF_F_TX_TCP_CKSUM) && 108 (txq->flags & IONIC_QCQ_F_CSUM_TCP)) || 109 ((ol_flags & RTE_MBUF_F_TX_UDP_CKSUM) && 110 (txq->flags & IONIC_QCQ_F_CSUM_UDP))) { 111 opcode = IONIC_TXQ_DESC_OPCODE_CSUM_HW; 112 flags |= IONIC_TXQ_DESC_FLAG_CSUM_L4; 113 } 114 115 if (opcode == IONIC_TXQ_DESC_OPCODE_CSUM_NONE) 116 stats->no_csum++; 117 118 if (((ol_flags & RTE_MBUF_F_TX_OUTER_IP_CKSUM) || 119 (ol_flags & RTE_MBUF_F_TX_OUTER_UDP_CKSUM)) && 120 ((ol_flags & RTE_MBUF_F_TX_OUTER_IPV4) || 121 (ol_flags & RTE_MBUF_F_TX_OUTER_IPV6))) { 122 flags |= IONIC_TXQ_DESC_FLAG_ENCAP; 123 } 124 125 if (ol_flags & RTE_MBUF_F_TX_VLAN) { 126 flags |= IONIC_TXQ_DESC_FLAG_VLAN; 127 desc->vlan_tci = rte_cpu_to_le_16(txm->vlan_tci); 128 } 129 130 addr = rte_cpu_to_le_64(rte_mbuf_data_iova(txm)); 131 132 cmd = encode_txq_desc_cmd(opcode, flags, txm->nb_segs - 1, addr); 133 desc->cmd = rte_cpu_to_le_64(cmd); 134 desc->len = rte_cpu_to_le_16(txm->data_len); 135 136 info[0] = txm; 137 138 if (txm->nb_segs > 1) { 139 txm_seg = txm->next; 140 141 elem = sg_desc->elems; 142 143 while (txm_seg != NULL) { 144 /* Stash the mbuf ptr in the array */ 145 info++; 146 *info = txm_seg; 147 148 /* Configure the SGE */ 149 data_iova = rte_mbuf_data_iova(txm_seg); 150 elem->len = rte_cpu_to_le_16(txm_seg->data_len); 151 elem->addr = rte_cpu_to_le_64(data_iova); 152 elem++; 153 154 txm_seg = txm_seg->next; 155 } 156 } 157 158 q->head_idx = Q_NEXT_TO_POST(q, 1); 159 160 return 0; 161 } 162 163 uint16_t 164 ionic_xmit_pkts_sg(void *tx_queue, struct rte_mbuf **tx_pkts, 165 uint16_t nb_pkts) 166 { 167 struct ionic_tx_qcq *txq = tx_queue; 168 struct ionic_queue *q = &txq->qcq.q; 169 struct ionic_txq_desc *desc_base = q->base; 170 struct ionic_tx_stats *stats = &txq->stats; 171 struct rte_mbuf *mbuf; 172 uint32_t bytes_tx = 0; 173 uint16_t nb_avail, nb_tx = 0; 174 uint64_t then, now, hz, delta; 175 int err; 176 177 rte_prefetch0(&desc_base[q->head_idx]); 178 rte_prefetch0(IONIC_INFO_PTR(q, q->head_idx)); 179 180 if (nb_pkts) { 181 rte_mbuf_prefetch_part1(tx_pkts[0]); 182 rte_mbuf_prefetch_part2(tx_pkts[0]); 183 } 184 185 if (ionic_q_space_avail(q) < txq->free_thresh) { 186 /* Cleaning old buffers */ 187 ionic_tx_flush_sg(txq); 188 } 189 190 nb_avail = ionic_q_space_avail(q); 191 if (nb_avail < nb_pkts) { 192 stats->stop += nb_pkts - nb_avail; 193 nb_pkts = nb_avail; 194 } 195 196 while (nb_tx < nb_pkts) { 197 uint16_t next_idx = Q_NEXT_TO_POST(q, 1); 198 rte_prefetch0(&desc_base[next_idx]); 199 rte_prefetch0(IONIC_INFO_PTR(q, next_idx)); 200 201 if (nb_tx + 1 < nb_pkts) { 202 rte_mbuf_prefetch_part1(tx_pkts[nb_tx + 1]); 203 rte_mbuf_prefetch_part2(tx_pkts[nb_tx + 1]); 204 } 205 206 mbuf = tx_pkts[nb_tx]; 207 208 if (mbuf->ol_flags & RTE_MBUF_F_TX_TCP_SEG) 209 err = ionic_tx_tso(txq, mbuf); 210 else 211 err = ionic_tx_sg(txq, mbuf); 212 if (err) { 213 stats->drop += nb_pkts - nb_tx; 214 break; 215 } 216 217 bytes_tx += mbuf->pkt_len; 218 nb_tx++; 219 } 220 221 if (nb_tx > 0) { 222 rte_wmb(); 223 ionic_txq_flush(q); 224 225 txq->last_wdog_cycles = rte_get_timer_cycles(); 226 227 stats->packets += nb_tx; 228 stats->bytes += bytes_tx; 229 } else { 230 /* 231 * Ring the doorbell again if no work could be posted and work 232 * is still pending after the deadline. 233 */ 234 if (q->head_idx != q->tail_idx) { 235 then = txq->last_wdog_cycles; 236 now = rte_get_timer_cycles(); 237 hz = rte_get_timer_hz(); 238 delta = (now - then) * 1000; 239 240 if (delta >= hz * IONIC_Q_WDOG_MS) { 241 ionic_q_flush(q); 242 txq->last_wdog_cycles = now; 243 } 244 } 245 } 246 247 return nb_tx; 248 } 249 250 /* 251 * Cleans one descriptor. Connects the filled mbufs into a chain. 252 * Does not advance the tail index. 253 */ 254 static __rte_always_inline void 255 ionic_rx_clean_one_sg(struct ionic_rx_qcq *rxq, 256 volatile struct ionic_rxq_comp *cq_desc, 257 struct ionic_rx_service *rx_svc) 258 { 259 struct ionic_queue *q = &rxq->qcq.q; 260 struct rte_mbuf *rxm; 261 struct rte_mbuf *rxm_seg, *prev_rxm; 262 struct ionic_rx_stats *stats = &rxq->stats; 263 uint64_t pkt_flags = 0; 264 uint32_t pkt_type; 265 uint32_t left, i; 266 uint16_t cq_desc_len; 267 uint8_t ptype, cflags; 268 void **info; 269 270 cq_desc_len = rte_le_to_cpu_16(cq_desc->len); 271 272 info = IONIC_INFO_PTR(q, q->tail_idx); 273 274 rxm = info[0]; 275 276 if (cq_desc->status) { 277 stats->bad_cq_status++; 278 return; 279 } 280 281 if (cq_desc_len > rxq->frame_size || cq_desc_len == 0) { 282 stats->bad_len++; 283 return; 284 } 285 286 info[0] = NULL; 287 288 /* Set the mbuf metadata based on the cq entry */ 289 rxm->rearm_data[0] = rxq->rearm_data; 290 rxm->pkt_len = cq_desc_len; 291 rxm->data_len = RTE_MIN(rxq->hdr_seg_size, cq_desc_len); 292 left = cq_desc_len - rxm->data_len; 293 rxm->nb_segs = cq_desc->num_sg_elems + 1; 294 295 prev_rxm = rxm; 296 297 for (i = 1; i < rxm->nb_segs && left; i++) { 298 rxm_seg = info[i]; 299 info[i] = NULL; 300 301 /* Set the chained mbuf metadata */ 302 rxm_seg->rearm_data[0] = rxq->rearm_seg_data; 303 rxm_seg->data_len = RTE_MIN(rxq->seg_size, left); 304 left -= rxm_seg->data_len; 305 306 /* Link the mbuf */ 307 prev_rxm->next = rxm_seg; 308 prev_rxm = rxm_seg; 309 } 310 311 /* Terminate the mbuf chain */ 312 prev_rxm->next = NULL; 313 314 /* RSS */ 315 pkt_flags |= RTE_MBUF_F_RX_RSS_HASH; 316 rxm->hash.rss = rte_le_to_cpu_32(cq_desc->rss_hash); 317 318 /* Vlan Strip */ 319 if (cq_desc->csum_flags & IONIC_RXQ_COMP_CSUM_F_VLAN) { 320 pkt_flags |= RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED; 321 rxm->vlan_tci = rte_le_to_cpu_16(cq_desc->vlan_tci); 322 } 323 324 /* Checksum */ 325 if (cq_desc->csum_flags & IONIC_RXQ_COMP_CSUM_F_CALC) { 326 cflags = cq_desc->csum_flags & IONIC_CSUM_FLAG_MASK; 327 pkt_flags |= ionic_csum_flags[cflags]; 328 } 329 330 rxm->ol_flags = pkt_flags; 331 332 /* Packet Type */ 333 ptype = cq_desc->pkt_type_color & IONIC_RXQ_COMP_PKT_TYPE_MASK; 334 pkt_type = ionic_ptype_table[ptype]; 335 if (pkt_type == RTE_PTYPE_UNKNOWN) { 336 struct rte_ether_hdr *eth_h = rte_pktmbuf_mtod(rxm, 337 struct rte_ether_hdr *); 338 uint16_t ether_type = eth_h->ether_type; 339 if (ether_type == rte_cpu_to_be_16(RTE_ETHER_TYPE_ARP)) 340 pkt_type = RTE_PTYPE_L2_ETHER_ARP; 341 else if (ether_type == rte_cpu_to_be_16(RTE_ETHER_TYPE_LLDP)) 342 pkt_type = RTE_PTYPE_L2_ETHER_LLDP; 343 else if (ether_type == rte_cpu_to_be_16(RTE_ETHER_TYPE_1588)) 344 pkt_type = RTE_PTYPE_L2_ETHER_TIMESYNC; 345 stats->mtods++; 346 } else if (pkt_flags & RTE_MBUF_F_RX_VLAN) { 347 pkt_type |= RTE_PTYPE_L2_ETHER_VLAN; 348 } else { 349 pkt_type |= RTE_PTYPE_L2_ETHER; 350 } 351 352 rxm->packet_type = pkt_type; 353 354 rx_svc->rx_pkts[rx_svc->nb_rx] = rxm; 355 rx_svc->nb_rx++; 356 357 stats->packets++; 358 stats->bytes += rxm->pkt_len; 359 } 360 361 /* 362 * Fills one descriptor with mbufs. Does not advance the head index. 363 */ 364 static __rte_always_inline int 365 ionic_rx_fill_one_sg(struct ionic_rx_qcq *rxq) 366 { 367 struct ionic_queue *q = &rxq->qcq.q; 368 struct rte_mbuf *rxm; 369 struct rte_mbuf *rxm_seg; 370 struct ionic_rxq_desc *desc, *desc_base = q->base; 371 struct ionic_rxq_sg_desc *sg_desc, *sg_desc_base = q->sg_base; 372 rte_iova_t data_iova; 373 uint32_t i; 374 void **info; 375 int ret; 376 377 info = IONIC_INFO_PTR(q, q->head_idx); 378 desc = &desc_base[q->head_idx]; 379 sg_desc = &sg_desc_base[q->head_idx]; 380 381 /* mbuf is unused => whole chain is unused */ 382 if (info[0]) 383 return 0; 384 385 if (rxq->mb_idx == 0) { 386 ret = rte_mempool_get_bulk(rxq->mb_pool, 387 (void **)rxq->mbs, 388 IONIC_MBUF_BULK_ALLOC); 389 if (ret) { 390 assert(0); 391 return -ENOMEM; 392 } 393 394 rxq->mb_idx = IONIC_MBUF_BULK_ALLOC; 395 } 396 397 rxm = rxq->mbs[--rxq->mb_idx]; 398 info[0] = rxm; 399 400 data_iova = rte_mbuf_data_iova_default(rxm); 401 desc->addr = rte_cpu_to_le_64(data_iova); 402 403 for (i = 1; i < q->num_segs; i++) { 404 /* mbuf is unused => rest of the chain is unused */ 405 if (info[i]) 406 return 0; 407 408 if (rxq->mb_idx == 0) { 409 ret = rte_mempool_get_bulk(rxq->mb_pool, 410 (void **)rxq->mbs, 411 IONIC_MBUF_BULK_ALLOC); 412 if (ret) { 413 assert(0); 414 return -ENOMEM; 415 } 416 417 rxq->mb_idx = IONIC_MBUF_BULK_ALLOC; 418 } 419 420 rxm_seg = rxq->mbs[--rxq->mb_idx]; 421 info[i] = rxm_seg; 422 423 /* The data_off does not get set to 0 until later */ 424 data_iova = rxm_seg->buf_iova; 425 sg_desc->elems[i - 1].addr = rte_cpu_to_le_64(data_iova); 426 } 427 428 return 0; 429 } 430 431 /* 432 * Walk the CQ to find completed receive descriptors. 433 * Any completed descriptor found is refilled. 434 */ 435 static __rte_always_inline void 436 ionic_rxq_service_sg(struct ionic_rx_qcq *rxq, uint32_t work_to_do, 437 struct ionic_rx_service *rx_svc) 438 { 439 struct ionic_cq *cq = &rxq->qcq.cq; 440 struct ionic_queue *q = &rxq->qcq.q; 441 struct ionic_rxq_desc *q_desc_base = q->base; 442 struct ionic_rxq_comp *cq_desc_base = cq->base; 443 volatile struct ionic_rxq_comp *cq_desc; 444 uint32_t work_done = 0; 445 uint64_t then, now, hz, delta; 446 447 cq_desc = &cq_desc_base[cq->tail_idx]; 448 449 while (color_match(cq_desc->pkt_type_color, cq->done_color)) { 450 cq->tail_idx = Q_NEXT_TO_SRVC(cq, 1); 451 if (cq->tail_idx == 0) 452 cq->done_color = !cq->done_color; 453 454 /* Prefetch 8 x 8B bufinfo */ 455 rte_prefetch0(IONIC_INFO_PTR(q, Q_NEXT_TO_SRVC(q, 8))); 456 /* Prefetch 4 x 16B comp */ 457 rte_prefetch0(&cq_desc_base[Q_NEXT_TO_SRVC(cq, 4)]); 458 /* Prefetch 4 x 16B descriptors */ 459 rte_prefetch0(&q_desc_base[Q_NEXT_TO_POST(q, 4)]); 460 461 /* Clean one descriptor */ 462 ionic_rx_clean_one_sg(rxq, cq_desc, rx_svc); 463 q->tail_idx = Q_NEXT_TO_SRVC(q, 1); 464 465 /* Fill one descriptor */ 466 (void)ionic_rx_fill_one_sg(rxq); 467 468 q->head_idx = Q_NEXT_TO_POST(q, 1); 469 470 if (++work_done == work_to_do) 471 break; 472 473 cq_desc = &cq_desc_base[cq->tail_idx]; 474 } 475 476 /* Update the queue indices and ring the doorbell */ 477 if (work_done) { 478 ionic_rxq_flush(q); 479 480 rxq->last_wdog_cycles = rte_get_timer_cycles(); 481 rxq->wdog_ms = IONIC_Q_WDOG_MS; 482 } else { 483 /* 484 * Ring the doorbell again if no recvs were posted and the 485 * recv queue is not empty after the deadline. 486 * 487 * Exponentially back off the deadline to avoid excessive 488 * doorbells when the recv queue is idle. 489 */ 490 if (q->head_idx != q->tail_idx) { 491 then = rxq->last_wdog_cycles; 492 now = rte_get_timer_cycles(); 493 hz = rte_get_timer_hz(); 494 delta = (now - then) * 1000; 495 496 if (delta >= hz * rxq->wdog_ms) { 497 ionic_q_flush(q); 498 rxq->last_wdog_cycles = now; 499 500 delta = 2 * rxq->wdog_ms; 501 if (delta > IONIC_Q_WDOG_MAX_MS) 502 delta = IONIC_Q_WDOG_MAX_MS; 503 504 rxq->wdog_ms = delta; 505 } 506 } 507 } 508 } 509 510 uint16_t 511 ionic_recv_pkts_sg(void *rx_queue, struct rte_mbuf **rx_pkts, 512 uint16_t nb_pkts) 513 { 514 struct ionic_rx_qcq *rxq = rx_queue; 515 struct ionic_rx_service rx_svc; 516 517 rx_svc.rx_pkts = rx_pkts; 518 rx_svc.nb_rx = 0; 519 520 ionic_rxq_service_sg(rxq, nb_pkts, &rx_svc); 521 522 return rx_svc.nb_rx; 523 } 524 525 /* 526 * Fills all descriptors with mbufs. 527 */ 528 int __rte_cold 529 ionic_rx_fill_sg(struct ionic_rx_qcq *rxq) 530 { 531 struct ionic_queue *q = &rxq->qcq.q; 532 uint32_t i; 533 int err = 0; 534 535 for (i = 0; i < q->num_descs - 1u; i++) { 536 err = ionic_rx_fill_one_sg(rxq); 537 if (err) 538 break; 539 540 q->head_idx = Q_NEXT_TO_POST(q, 1); 541 } 542 543 ionic_rxq_flush(q); 544 545 return err; 546 } 547