1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) 2 * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved. 3 */ 4 5 #include <sys/queue.h> 6 #include <stdio.h> 7 #include <stdlib.h> 8 #include <string.h> 9 #include <errno.h> 10 #include <stdint.h> 11 #include <stdarg.h> 12 #include <unistd.h> 13 #include <inttypes.h> 14 15 #include <rte_byteorder.h> 16 #include <rte_common.h> 17 #include <rte_cycles.h> 18 #include <rte_log.h> 19 #include <rte_debug.h> 20 #include <rte_interrupts.h> 21 #include <rte_pci.h> 22 #include <rte_memory.h> 23 #include <rte_memzone.h> 24 #include <rte_launch.h> 25 #include <rte_eal.h> 26 #include <rte_per_lcore.h> 27 #include <rte_lcore.h> 28 #include <rte_atomic.h> 29 #include <rte_branch_prediction.h> 30 #include <rte_mempool.h> 31 #include <rte_malloc.h> 32 #include <rte_mbuf.h> 33 #include <rte_ether.h> 34 #include <rte_ethdev_driver.h> 35 #include <rte_prefetch.h> 36 #include <rte_udp.h> 37 #include <rte_tcp.h> 38 #include <rte_sctp.h> 39 #include <rte_string_fns.h> 40 #include <rte_errno.h> 41 #include <rte_ip.h> 42 #include <rte_net.h> 43 44 #include "ionic_logs.h" 45 #include "ionic_mac_api.h" 46 #include "ionic_ethdev.h" 47 #include "ionic_lif.h" 48 #include "ionic_rxtx.h" 49 50 #define IONIC_RX_RING_DOORBELL_STRIDE (32 - 1) 51 52 /********************************************************************* 53 * 54 * TX functions 55 * 56 **********************************************************************/ 57 58 void 59 ionic_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 60 struct rte_eth_txq_info *qinfo) 61 { 62 struct ionic_qcq *txq = dev->data->tx_queues[queue_id]; 63 struct ionic_queue *q = &txq->q; 64 65 qinfo->nb_desc = q->num_descs; 66 qinfo->conf.offloads = txq->offloads; 67 qinfo->conf.tx_deferred_start = txq->flags & IONIC_QCQ_F_DEFERRED; 68 } 69 70 static inline void __rte_cold 71 ionic_tx_flush(struct ionic_cq *cq) 72 { 73 struct ionic_queue *q = cq->bound_q; 74 struct ionic_desc_info *q_desc_info; 75 struct rte_mbuf *txm, *next; 76 struct ionic_txq_comp *cq_desc_base = cq->base; 77 struct ionic_txq_comp *cq_desc; 78 u_int32_t comp_index = (u_int32_t)-1; 79 80 cq_desc = &cq_desc_base[cq->tail_idx]; 81 while (color_match(cq_desc->color, cq->done_color)) { 82 cq->tail_idx = (cq->tail_idx + 1) & (cq->num_descs - 1); 83 84 /* Prefetch the next 4 descriptors (not really useful here) */ 85 if ((cq->tail_idx & 0x3) == 0) 86 rte_prefetch0(&cq_desc_base[cq->tail_idx]); 87 88 if (cq->tail_idx == 0) 89 cq->done_color = !cq->done_color; 90 91 comp_index = cq_desc->comp_index; 92 93 cq_desc = &cq_desc_base[cq->tail_idx]; 94 } 95 96 if (comp_index != (u_int32_t)-1) { 97 while (q->tail_idx != comp_index) { 98 q_desc_info = &q->info[q->tail_idx]; 99 100 q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1); 101 102 /* Prefetch the next 4 descriptors */ 103 if ((q->tail_idx & 0x3) == 0) 104 /* q desc info */ 105 rte_prefetch0(&q->info[q->tail_idx]); 106 107 /* 108 * Note: you can just use rte_pktmbuf_free, 109 * but this loop is faster 110 */ 111 txm = q_desc_info->cb_arg; 112 while (txm != NULL) { 113 next = txm->next; 114 rte_pktmbuf_free_seg(txm); 115 txm = next; 116 } 117 } 118 } 119 } 120 121 void __rte_cold 122 ionic_dev_tx_queue_release(void *tx_queue) 123 { 124 struct ionic_qcq *txq = (struct ionic_qcq *)tx_queue; 125 126 IONIC_PRINT_CALL(); 127 128 ionic_lif_txq_deinit(txq); 129 130 ionic_qcq_free(txq); 131 } 132 133 int __rte_cold 134 ionic_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id) 135 { 136 struct ionic_qcq *txq; 137 138 IONIC_PRINT(DEBUG, "Stopping TX queue %u", tx_queue_id); 139 140 txq = eth_dev->data->tx_queues[tx_queue_id]; 141 142 eth_dev->data->tx_queue_state[tx_queue_id] = 143 RTE_ETH_QUEUE_STATE_STOPPED; 144 145 /* 146 * Note: we should better post NOP Tx desc and wait for its completion 147 * before disabling Tx queue 148 */ 149 150 ionic_qcq_disable(txq); 151 152 ionic_tx_flush(&txq->cq); 153 154 return 0; 155 } 156 157 int __rte_cold 158 ionic_dev_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id, 159 uint16_t nb_desc, uint32_t socket_id, 160 const struct rte_eth_txconf *tx_conf) 161 { 162 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 163 struct ionic_qcq *txq; 164 uint64_t offloads; 165 int err; 166 167 if (tx_queue_id >= lif->ntxqcqs) { 168 IONIC_PRINT(DEBUG, "Queue index %u not available " 169 "(max %u queues)", 170 tx_queue_id, lif->ntxqcqs); 171 return -EINVAL; 172 } 173 174 offloads = tx_conf->offloads | eth_dev->data->dev_conf.txmode.offloads; 175 IONIC_PRINT(DEBUG, 176 "Configuring skt %u TX queue %u with %u buffers, offloads %jx", 177 socket_id, tx_queue_id, nb_desc, offloads); 178 179 /* Validate number of receive descriptors */ 180 if (!rte_is_power_of_2(nb_desc) || nb_desc < IONIC_MIN_RING_DESC) 181 return -EINVAL; /* or use IONIC_DEFAULT_RING_DESC */ 182 183 /* Free memory prior to re-allocation if needed... */ 184 if (eth_dev->data->tx_queues[tx_queue_id] != NULL) { 185 void *tx_queue = eth_dev->data->tx_queues[tx_queue_id]; 186 ionic_dev_tx_queue_release(tx_queue); 187 eth_dev->data->tx_queues[tx_queue_id] = NULL; 188 } 189 190 eth_dev->data->tx_queue_state[tx_queue_id] = 191 RTE_ETH_QUEUE_STATE_STOPPED; 192 193 err = ionic_tx_qcq_alloc(lif, tx_queue_id, nb_desc, &txq); 194 if (err) { 195 IONIC_PRINT(DEBUG, "Queue allocation failure"); 196 return -EINVAL; 197 } 198 199 /* Do not start queue with rte_eth_dev_start() */ 200 if (tx_conf->tx_deferred_start) 201 txq->flags |= IONIC_QCQ_F_DEFERRED; 202 203 txq->offloads = offloads; 204 205 eth_dev->data->tx_queues[tx_queue_id] = txq; 206 207 return 0; 208 } 209 210 /* 211 * Start Transmit Units for specified queue. 212 */ 213 int __rte_cold 214 ionic_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id) 215 { 216 uint8_t *tx_queue_state = eth_dev->data->tx_queue_state; 217 struct ionic_qcq *txq; 218 int err; 219 220 if (tx_queue_state[tx_queue_id] == RTE_ETH_QUEUE_STATE_STARTED) { 221 IONIC_PRINT(DEBUG, "TX queue %u already started", 222 tx_queue_id); 223 return 0; 224 } 225 226 txq = eth_dev->data->tx_queues[tx_queue_id]; 227 228 IONIC_PRINT(DEBUG, "Starting TX queue %u, %u descs", 229 tx_queue_id, txq->q.num_descs); 230 231 if (!(txq->flags & IONIC_QCQ_F_INITED)) { 232 err = ionic_lif_txq_init(txq); 233 if (err) 234 return err; 235 } else { 236 ionic_qcq_enable(txq); 237 } 238 239 tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 240 241 return 0; 242 } 243 244 static void 245 ionic_tx_tcp_pseudo_csum(struct rte_mbuf *txm) 246 { 247 struct ether_hdr *eth_hdr = rte_pktmbuf_mtod(txm, struct ether_hdr *); 248 char *l3_hdr = ((char *)eth_hdr) + txm->l2_len; 249 struct rte_tcp_hdr *tcp_hdr = (struct rte_tcp_hdr *) 250 (l3_hdr + txm->l3_len); 251 252 if (txm->ol_flags & PKT_TX_IP_CKSUM) { 253 struct rte_ipv4_hdr *ipv4_hdr = (struct rte_ipv4_hdr *)l3_hdr; 254 ipv4_hdr->hdr_checksum = 0; 255 tcp_hdr->cksum = 0; 256 tcp_hdr->cksum = rte_ipv4_udptcp_cksum(ipv4_hdr, tcp_hdr); 257 } else { 258 struct rte_ipv6_hdr *ipv6_hdr = (struct rte_ipv6_hdr *)l3_hdr; 259 tcp_hdr->cksum = 0; 260 tcp_hdr->cksum = rte_ipv6_udptcp_cksum(ipv6_hdr, tcp_hdr); 261 } 262 } 263 264 static void 265 ionic_tx_tcp_inner_pseudo_csum(struct rte_mbuf *txm) 266 { 267 struct ether_hdr *eth_hdr = rte_pktmbuf_mtod(txm, struct ether_hdr *); 268 char *l3_hdr = ((char *)eth_hdr) + txm->outer_l2_len + 269 txm->outer_l3_len + txm->l2_len; 270 struct rte_tcp_hdr *tcp_hdr = (struct rte_tcp_hdr *) 271 (l3_hdr + txm->l3_len); 272 273 if (txm->ol_flags & PKT_TX_IPV4) { 274 struct rte_ipv4_hdr *ipv4_hdr = (struct rte_ipv4_hdr *)l3_hdr; 275 ipv4_hdr->hdr_checksum = 0; 276 tcp_hdr->cksum = 0; 277 tcp_hdr->cksum = rte_ipv4_udptcp_cksum(ipv4_hdr, tcp_hdr); 278 } else { 279 struct rte_ipv6_hdr *ipv6_hdr = (struct rte_ipv6_hdr *)l3_hdr; 280 tcp_hdr->cksum = 0; 281 tcp_hdr->cksum = rte_ipv6_udptcp_cksum(ipv6_hdr, tcp_hdr); 282 } 283 } 284 285 static void 286 ionic_tx_tso_post(struct ionic_queue *q, struct ionic_txq_desc *desc, 287 struct rte_mbuf *txm, 288 rte_iova_t addr, uint8_t nsge, uint16_t len, 289 uint32_t hdrlen, uint32_t mss, 290 bool encap, 291 uint16_t vlan_tci, bool has_vlan, 292 bool start, bool done) 293 { 294 uint8_t flags = 0; 295 flags |= has_vlan ? IONIC_TXQ_DESC_FLAG_VLAN : 0; 296 flags |= encap ? IONIC_TXQ_DESC_FLAG_ENCAP : 0; 297 flags |= start ? IONIC_TXQ_DESC_FLAG_TSO_SOT : 0; 298 flags |= done ? IONIC_TXQ_DESC_FLAG_TSO_EOT : 0; 299 300 desc->cmd = encode_txq_desc_cmd(IONIC_TXQ_DESC_OPCODE_TSO, 301 flags, nsge, addr); 302 desc->len = len; 303 desc->vlan_tci = vlan_tci; 304 desc->hdr_len = hdrlen; 305 desc->mss = mss; 306 307 ionic_q_post(q, done, NULL, done ? txm : NULL); 308 } 309 310 static struct ionic_txq_desc * 311 ionic_tx_tso_next(struct ionic_queue *q, struct ionic_txq_sg_elem **elem) 312 { 313 struct ionic_txq_desc *desc_base = q->base; 314 struct ionic_txq_sg_desc *sg_desc_base = q->sg_base; 315 struct ionic_txq_desc *desc = &desc_base[q->head_idx]; 316 struct ionic_txq_sg_desc *sg_desc = &sg_desc_base[q->head_idx]; 317 318 *elem = sg_desc->elems; 319 return desc; 320 } 321 322 static int 323 ionic_tx_tso(struct ionic_queue *q, struct rte_mbuf *txm, 324 uint64_t offloads __rte_unused, bool not_xmit_more) 325 { 326 struct ionic_tx_stats *stats = IONIC_Q_TO_TX_STATS(q); 327 struct ionic_txq_desc *desc; 328 struct ionic_txq_sg_elem *elem; 329 struct rte_mbuf *txm_seg; 330 uint64_t desc_addr = 0; 331 uint16_t desc_len = 0; 332 uint8_t desc_nsge; 333 uint32_t hdrlen; 334 uint32_t mss = txm->tso_segsz; 335 uint32_t frag_left = 0; 336 uint32_t left; 337 uint32_t seglen; 338 uint32_t len; 339 uint32_t offset = 0; 340 bool start, done; 341 bool encap; 342 bool has_vlan = !!(txm->ol_flags & PKT_TX_VLAN_PKT); 343 uint16_t vlan_tci = txm->vlan_tci; 344 uint64_t ol_flags = txm->ol_flags; 345 346 encap = ((ol_flags & PKT_TX_OUTER_IP_CKSUM) || 347 (ol_flags & PKT_TX_OUTER_UDP_CKSUM)) && 348 ((ol_flags & PKT_TX_OUTER_IPV4) || 349 (ol_flags & PKT_TX_OUTER_IPV6)); 350 351 /* Preload inner-most TCP csum field with IP pseudo hdr 352 * calculated with IP length set to zero. HW will later 353 * add in length to each TCP segment resulting from the TSO. 354 */ 355 356 if (encap) { 357 ionic_tx_tcp_inner_pseudo_csum(txm); 358 hdrlen = txm->outer_l2_len + txm->outer_l3_len + 359 txm->l2_len + txm->l3_len + txm->l4_len; 360 } else { 361 ionic_tx_tcp_pseudo_csum(txm); 362 hdrlen = txm->l2_len + txm->l3_len + txm->l4_len; 363 } 364 365 seglen = hdrlen + mss; 366 left = txm->data_len; 367 368 desc = ionic_tx_tso_next(q, &elem); 369 start = true; 370 371 /* Chop data up into desc segments */ 372 373 while (left > 0) { 374 len = RTE_MIN(seglen, left); 375 frag_left = seglen - len; 376 desc_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(txm)); 377 desc_len = len; 378 desc_nsge = 0; 379 left -= len; 380 offset += len; 381 if (txm->nb_segs > 1 && frag_left > 0) 382 continue; 383 done = (txm->nb_segs == 1 && left == 0); 384 ionic_tx_tso_post(q, desc, txm, 385 desc_addr, desc_nsge, desc_len, 386 hdrlen, mss, 387 encap, 388 vlan_tci, has_vlan, 389 start, done && not_xmit_more); 390 desc = ionic_tx_tso_next(q, &elem); 391 start = false; 392 seglen = mss; 393 } 394 395 /* Chop frags into desc segments */ 396 397 txm_seg = txm->next; 398 while (txm_seg != NULL) { 399 offset = 0; 400 left = txm_seg->data_len; 401 stats->frags++; 402 403 while (left > 0) { 404 rte_iova_t data_iova; 405 data_iova = rte_mbuf_data_iova(txm_seg); 406 elem->addr = rte_cpu_to_le_64(data_iova) + offset; 407 if (frag_left > 0) { 408 len = RTE_MIN(frag_left, left); 409 frag_left -= len; 410 elem->len = len; 411 elem++; 412 desc_nsge++; 413 } else { 414 len = RTE_MIN(mss, left); 415 frag_left = mss - len; 416 data_iova = rte_mbuf_data_iova(txm_seg); 417 desc_addr = rte_cpu_to_le_64(data_iova); 418 desc_len = len; 419 desc_nsge = 0; 420 } 421 left -= len; 422 offset += len; 423 if (txm_seg->next != NULL && frag_left > 0) 424 continue; 425 done = (txm_seg->next == NULL && left == 0); 426 ionic_tx_tso_post(q, desc, txm_seg, 427 desc_addr, desc_nsge, desc_len, 428 hdrlen, mss, 429 encap, 430 vlan_tci, has_vlan, 431 start, done && not_xmit_more); 432 desc = ionic_tx_tso_next(q, &elem); 433 start = false; 434 } 435 436 txm_seg = txm_seg->next; 437 } 438 439 stats->tso++; 440 441 return 0; 442 } 443 444 static int 445 ionic_tx(struct ionic_queue *q, struct rte_mbuf *txm, 446 uint64_t offloads, bool not_xmit_more) 447 { 448 struct ionic_txq_desc *desc_base = q->base; 449 struct ionic_txq_sg_desc *sg_desc_base = q->sg_base; 450 struct ionic_txq_desc *desc = &desc_base[q->head_idx]; 451 struct ionic_txq_sg_desc *sg_desc = &sg_desc_base[q->head_idx]; 452 struct ionic_txq_sg_elem *elem = sg_desc->elems; 453 struct ionic_tx_stats *stats = IONIC_Q_TO_TX_STATS(q); 454 struct rte_mbuf *txm_seg; 455 bool encap; 456 bool has_vlan; 457 uint64_t ol_flags = txm->ol_flags; 458 uint64_t addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(txm)); 459 uint8_t opcode = IONIC_TXQ_DESC_OPCODE_CSUM_NONE; 460 uint8_t flags = 0; 461 462 if ((ol_flags & PKT_TX_IP_CKSUM) && 463 (offloads & DEV_TX_OFFLOAD_IPV4_CKSUM)) { 464 opcode = IONIC_TXQ_DESC_OPCODE_CSUM_HW; 465 flags |= IONIC_TXQ_DESC_FLAG_CSUM_L3; 466 if (((ol_flags & PKT_TX_TCP_CKSUM) && 467 (offloads & DEV_TX_OFFLOAD_TCP_CKSUM)) || 468 ((ol_flags & PKT_TX_UDP_CKSUM) && 469 (offloads & DEV_TX_OFFLOAD_UDP_CKSUM))) 470 flags |= IONIC_TXQ_DESC_FLAG_CSUM_L4; 471 } else { 472 stats->no_csum++; 473 } 474 475 has_vlan = (ol_flags & PKT_TX_VLAN_PKT); 476 encap = ((ol_flags & PKT_TX_OUTER_IP_CKSUM) || 477 (ol_flags & PKT_TX_OUTER_UDP_CKSUM)) && 478 ((ol_flags & PKT_TX_OUTER_IPV4) || 479 (ol_flags & PKT_TX_OUTER_IPV6)); 480 481 flags |= has_vlan ? IONIC_TXQ_DESC_FLAG_VLAN : 0; 482 flags |= encap ? IONIC_TXQ_DESC_FLAG_ENCAP : 0; 483 484 desc->cmd = encode_txq_desc_cmd(opcode, flags, txm->nb_segs - 1, addr); 485 desc->len = txm->data_len; 486 desc->vlan_tci = txm->vlan_tci; 487 488 txm_seg = txm->next; 489 while (txm_seg != NULL) { 490 elem->len = txm_seg->data_len; 491 elem->addr = rte_cpu_to_le_64(rte_mbuf_data_iova(txm_seg)); 492 stats->frags++; 493 elem++; 494 txm_seg = txm_seg->next; 495 } 496 497 ionic_q_post(q, not_xmit_more, NULL, txm); 498 499 return 0; 500 } 501 502 uint16_t 503 ionic_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 504 uint16_t nb_pkts) 505 { 506 struct ionic_qcq *txq = (struct ionic_qcq *)tx_queue; 507 struct ionic_queue *q = &txq->q; 508 struct ionic_cq *cq = &txq->cq; 509 struct ionic_tx_stats *stats = IONIC_Q_TO_TX_STATS(q); 510 uint32_t next_q_head_idx; 511 uint32_t bytes_tx = 0; 512 uint16_t nb_tx = 0; 513 int err; 514 bool last; 515 516 /* Cleaning old buffers */ 517 ionic_tx_flush(cq); 518 519 if (unlikely(ionic_q_space_avail(q) < nb_pkts)) { 520 stats->stop += nb_pkts; 521 return 0; 522 } 523 524 while (nb_tx < nb_pkts) { 525 last = (nb_tx == (nb_pkts - 1)); 526 527 next_q_head_idx = (q->head_idx + 1) & (q->num_descs - 1); 528 if ((next_q_head_idx & 0x3) == 0) { 529 struct ionic_txq_desc *desc_base = q->base; 530 rte_prefetch0(&desc_base[next_q_head_idx]); 531 rte_prefetch0(&q->info[next_q_head_idx]); 532 } 533 534 if (tx_pkts[nb_tx]->ol_flags & PKT_TX_TCP_SEG) 535 err = ionic_tx_tso(q, tx_pkts[nb_tx], txq->offloads, 536 last); 537 else 538 err = ionic_tx(q, tx_pkts[nb_tx], txq->offloads, last); 539 if (err) { 540 stats->drop += nb_pkts - nb_tx; 541 if (nb_tx > 0) 542 ionic_q_flush(q); 543 break; 544 } 545 546 bytes_tx += tx_pkts[nb_tx]->pkt_len; 547 nb_tx++; 548 } 549 550 stats->packets += nb_tx; 551 stats->bytes += bytes_tx; 552 553 return nb_tx; 554 } 555 556 /********************************************************************* 557 * 558 * TX prep functions 559 * 560 **********************************************************************/ 561 562 #define IONIC_TX_OFFLOAD_MASK ( \ 563 PKT_TX_IPV4 | \ 564 PKT_TX_IPV6 | \ 565 PKT_TX_VLAN | \ 566 PKT_TX_IP_CKSUM | \ 567 PKT_TX_TCP_SEG | \ 568 PKT_TX_L4_MASK) 569 570 #define IONIC_TX_OFFLOAD_NOTSUP_MASK \ 571 (PKT_TX_OFFLOAD_MASK ^ IONIC_TX_OFFLOAD_MASK) 572 573 uint16_t 574 ionic_prep_pkts(void *tx_queue __rte_unused, struct rte_mbuf **tx_pkts, 575 uint16_t nb_pkts) 576 { 577 struct rte_mbuf *txm; 578 uint64_t offloads; 579 int i = 0; 580 581 for (i = 0; i < nb_pkts; i++) { 582 txm = tx_pkts[i]; 583 584 if (txm->nb_segs > IONIC_TX_MAX_SG_ELEMS) { 585 rte_errno = -EINVAL; 586 break; 587 } 588 589 offloads = txm->ol_flags; 590 591 if (offloads & IONIC_TX_OFFLOAD_NOTSUP_MASK) { 592 rte_errno = -ENOTSUP; 593 break; 594 } 595 } 596 597 return i; 598 } 599 600 /********************************************************************* 601 * 602 * RX functions 603 * 604 **********************************************************************/ 605 606 static void ionic_rx_recycle(struct ionic_queue *q, uint32_t q_desc_index, 607 struct rte_mbuf *mbuf); 608 609 void 610 ionic_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 611 struct rte_eth_rxq_info *qinfo) 612 { 613 struct ionic_qcq *rxq = dev->data->rx_queues[queue_id]; 614 struct ionic_queue *q = &rxq->q; 615 616 qinfo->mp = rxq->mb_pool; 617 qinfo->scattered_rx = dev->data->scattered_rx; 618 qinfo->nb_desc = q->num_descs; 619 qinfo->conf.rx_deferred_start = rxq->flags & IONIC_QCQ_F_DEFERRED; 620 qinfo->conf.offloads = rxq->offloads; 621 } 622 623 static void __rte_cold 624 ionic_rx_empty(struct ionic_queue *q) 625 { 626 struct ionic_qcq *rxq = IONIC_Q_TO_QCQ(q); 627 struct ionic_desc_info *cur; 628 struct rte_mbuf *mbuf; 629 630 while (q->tail_idx != q->head_idx) { 631 cur = &q->info[q->tail_idx]; 632 mbuf = cur->cb_arg; 633 rte_mempool_put(rxq->mb_pool, mbuf); 634 635 q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1); 636 } 637 } 638 639 void __rte_cold 640 ionic_dev_rx_queue_release(void *rx_queue) 641 { 642 struct ionic_qcq *rxq = (struct ionic_qcq *)rx_queue; 643 644 IONIC_PRINT_CALL(); 645 646 ionic_rx_empty(&rxq->q); 647 648 ionic_lif_rxq_deinit(rxq); 649 650 ionic_qcq_free(rxq); 651 } 652 653 int __rte_cold 654 ionic_dev_rx_queue_setup(struct rte_eth_dev *eth_dev, 655 uint16_t rx_queue_id, 656 uint16_t nb_desc, 657 uint32_t socket_id, 658 const struct rte_eth_rxconf *rx_conf, 659 struct rte_mempool *mp) 660 { 661 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 662 struct ionic_qcq *rxq; 663 uint64_t offloads; 664 int err; 665 666 if (rx_queue_id >= lif->nrxqcqs) { 667 IONIC_PRINT(ERR, 668 "Queue index %u not available (max %u queues)", 669 rx_queue_id, lif->nrxqcqs); 670 return -EINVAL; 671 } 672 673 offloads = rx_conf->offloads | eth_dev->data->dev_conf.rxmode.offloads; 674 IONIC_PRINT(DEBUG, 675 "Configuring skt %u RX queue %u with %u buffers, offloads %jx", 676 socket_id, rx_queue_id, nb_desc, offloads); 677 678 if (!rx_conf->rx_drop_en) 679 IONIC_PRINT(WARNING, "No-drop mode is not supported"); 680 681 /* Validate number of receive descriptors */ 682 if (!rte_is_power_of_2(nb_desc) || 683 nb_desc < IONIC_MIN_RING_DESC || 684 nb_desc > IONIC_MAX_RING_DESC) { 685 IONIC_PRINT(ERR, 686 "Bad descriptor count (%u) for queue %u (min: %u)", 687 nb_desc, rx_queue_id, IONIC_MIN_RING_DESC); 688 return -EINVAL; /* or use IONIC_DEFAULT_RING_DESC */ 689 } 690 691 /* Free memory prior to re-allocation if needed... */ 692 if (eth_dev->data->rx_queues[rx_queue_id] != NULL) { 693 void *rx_queue = eth_dev->data->rx_queues[rx_queue_id]; 694 ionic_dev_rx_queue_release(rx_queue); 695 eth_dev->data->rx_queues[rx_queue_id] = NULL; 696 } 697 698 eth_dev->data->rx_queue_state[rx_queue_id] = 699 RTE_ETH_QUEUE_STATE_STOPPED; 700 701 err = ionic_rx_qcq_alloc(lif, rx_queue_id, nb_desc, &rxq); 702 if (err) { 703 IONIC_PRINT(ERR, "Queue %d allocation failure", rx_queue_id); 704 return -EINVAL; 705 } 706 707 rxq->mb_pool = mp; 708 709 /* 710 * Note: the interface does not currently support 711 * DEV_RX_OFFLOAD_KEEP_CRC, please also consider ETHER_CRC_LEN 712 * when the adapter will be able to keep the CRC and subtract 713 * it to the length for all received packets: 714 * if (eth_dev->data->dev_conf.rxmode.offloads & 715 * DEV_RX_OFFLOAD_KEEP_CRC) 716 * rxq->crc_len = ETHER_CRC_LEN; 717 */ 718 719 /* Do not start queue with rte_eth_dev_start() */ 720 if (rx_conf->rx_deferred_start) 721 rxq->flags |= IONIC_QCQ_F_DEFERRED; 722 723 rxq->offloads = offloads; 724 725 eth_dev->data->rx_queues[rx_queue_id] = rxq; 726 727 return 0; 728 } 729 730 static void 731 ionic_rx_clean(struct ionic_queue *q, 732 uint32_t q_desc_index, uint32_t cq_desc_index, 733 void *cb_arg, void *service_cb_arg) 734 { 735 struct ionic_rxq_comp *cq_desc_base = q->bound_cq->base; 736 struct ionic_rxq_comp *cq_desc = &cq_desc_base[cq_desc_index]; 737 struct rte_mbuf *rxm = cb_arg; 738 struct rte_mbuf *rxm_seg; 739 struct ionic_qcq *rxq = IONIC_Q_TO_QCQ(q); 740 uint32_t max_frame_size = 741 rxq->lif->eth_dev->data->dev_conf.rxmode.max_rx_pkt_len; 742 uint64_t pkt_flags = 0; 743 uint32_t pkt_type; 744 struct ionic_rx_stats *stats = IONIC_Q_TO_RX_STATS(q); 745 struct ionic_rx_service *recv_args = (struct ionic_rx_service *) 746 service_cb_arg; 747 uint32_t buf_size = (uint16_t) 748 (rte_pktmbuf_data_room_size(rxq->mb_pool) - 749 RTE_PKTMBUF_HEADROOM); 750 uint32_t left; 751 752 if (!recv_args) { 753 stats->no_cb_arg++; 754 /* Flush */ 755 rte_pktmbuf_free(rxm); 756 /* 757 * Note: rte_mempool_put is faster with no segs 758 * rte_mempool_put(rxq->mb_pool, rxm); 759 */ 760 return; 761 } 762 763 if (cq_desc->status) { 764 stats->bad_cq_status++; 765 ionic_rx_recycle(q, q_desc_index, rxm); 766 return; 767 } 768 769 if (recv_args->nb_rx >= recv_args->nb_pkts) { 770 stats->no_room++; 771 ionic_rx_recycle(q, q_desc_index, rxm); 772 return; 773 } 774 775 if (cq_desc->len > max_frame_size || 776 cq_desc->len == 0) { 777 stats->bad_len++; 778 ionic_rx_recycle(q, q_desc_index, rxm); 779 return; 780 } 781 782 rxm->data_off = RTE_PKTMBUF_HEADROOM; 783 rte_prefetch1((char *)rxm->buf_addr + rxm->data_off); 784 rxm->nb_segs = 1; /* cq_desc->num_sg_elems */ 785 rxm->pkt_len = cq_desc->len; 786 rxm->port = rxq->lif->port_id; 787 788 left = cq_desc->len; 789 790 rxm->data_len = RTE_MIN(buf_size, left); 791 left -= rxm->data_len; 792 793 rxm_seg = rxm->next; 794 while (rxm_seg && left) { 795 rxm_seg->data_len = RTE_MIN(buf_size, left); 796 left -= rxm_seg->data_len; 797 798 rxm_seg = rxm_seg->next; 799 rxm->nb_segs++; 800 } 801 802 /* RSS */ 803 pkt_flags |= PKT_RX_RSS_HASH; 804 rxm->hash.rss = cq_desc->rss_hash; 805 806 /* Vlan Strip */ 807 if (cq_desc->csum_flags & IONIC_RXQ_COMP_CSUM_F_VLAN) { 808 pkt_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED; 809 rxm->vlan_tci = cq_desc->vlan_tci; 810 } 811 812 /* Checksum */ 813 if (cq_desc->csum_flags & IONIC_RXQ_COMP_CSUM_F_CALC) { 814 if (cq_desc->csum_flags & IONIC_RXQ_COMP_CSUM_F_IP_OK) 815 pkt_flags |= PKT_RX_IP_CKSUM_GOOD; 816 else if (cq_desc->csum_flags & IONIC_RXQ_COMP_CSUM_F_IP_BAD) 817 pkt_flags |= PKT_RX_IP_CKSUM_BAD; 818 819 if ((cq_desc->csum_flags & IONIC_RXQ_COMP_CSUM_F_TCP_OK) || 820 (cq_desc->csum_flags & IONIC_RXQ_COMP_CSUM_F_UDP_OK)) 821 pkt_flags |= PKT_RX_L4_CKSUM_GOOD; 822 else if ((cq_desc->csum_flags & 823 IONIC_RXQ_COMP_CSUM_F_TCP_BAD) || 824 (cq_desc->csum_flags & 825 IONIC_RXQ_COMP_CSUM_F_UDP_BAD)) 826 pkt_flags |= PKT_RX_L4_CKSUM_BAD; 827 } 828 829 rxm->ol_flags = pkt_flags; 830 831 /* Packet Type */ 832 switch (cq_desc->pkt_type_color & IONIC_RXQ_COMP_PKT_TYPE_MASK) { 833 case IONIC_PKT_TYPE_IPV4: 834 pkt_type = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4; 835 break; 836 case IONIC_PKT_TYPE_IPV6: 837 pkt_type = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6; 838 break; 839 case IONIC_PKT_TYPE_IPV4_TCP: 840 pkt_type = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4 | 841 RTE_PTYPE_L4_TCP; 842 break; 843 case IONIC_PKT_TYPE_IPV6_TCP: 844 pkt_type = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6 | 845 RTE_PTYPE_L4_TCP; 846 break; 847 case IONIC_PKT_TYPE_IPV4_UDP: 848 pkt_type = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4 | 849 RTE_PTYPE_L4_UDP; 850 break; 851 case IONIC_PKT_TYPE_IPV6_UDP: 852 pkt_type = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6 | 853 RTE_PTYPE_L4_UDP; 854 break; 855 default: 856 { 857 struct rte_ether_hdr *eth_h = rte_pktmbuf_mtod(rxm, 858 struct rte_ether_hdr *); 859 uint16_t ether_type = eth_h->ether_type; 860 if (ether_type == rte_cpu_to_be_16(RTE_ETHER_TYPE_ARP)) 861 pkt_type = RTE_PTYPE_L2_ETHER_ARP; 862 else 863 pkt_type = RTE_PTYPE_UNKNOWN; 864 break; 865 } 866 } 867 868 rxm->packet_type = pkt_type; 869 870 recv_args->rx_pkts[recv_args->nb_rx] = rxm; 871 recv_args->nb_rx++; 872 873 stats->packets++; 874 stats->bytes += rxm->pkt_len; 875 } 876 877 static void 878 ionic_rx_recycle(struct ionic_queue *q, uint32_t q_desc_index, 879 struct rte_mbuf *mbuf) 880 { 881 struct ionic_rxq_desc *desc_base = q->base; 882 struct ionic_rxq_desc *old = &desc_base[q_desc_index]; 883 struct ionic_rxq_desc *new = &desc_base[q->head_idx]; 884 885 new->addr = old->addr; 886 new->len = old->len; 887 888 ionic_q_post(q, true, ionic_rx_clean, mbuf); 889 } 890 891 static int __rte_cold 892 ionic_rx_fill(struct ionic_qcq *rxq, uint32_t len) 893 { 894 struct ionic_queue *q = &rxq->q; 895 struct ionic_rxq_desc *desc_base = q->base; 896 struct ionic_rxq_sg_desc *sg_desc_base = q->sg_base; 897 struct ionic_rxq_desc *desc; 898 struct ionic_rxq_sg_desc *sg_desc; 899 struct ionic_rxq_sg_elem *elem; 900 rte_iova_t dma_addr; 901 uint32_t i, j, nsegs, buf_size, size; 902 bool ring_doorbell; 903 904 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) - 905 RTE_PKTMBUF_HEADROOM); 906 907 /* Initialize software ring entries */ 908 for (i = ionic_q_space_avail(q); i; i--) { 909 struct rte_mbuf *rxm = rte_mbuf_raw_alloc(rxq->mb_pool); 910 struct rte_mbuf *prev_rxm_seg; 911 912 if (rxm == NULL) { 913 IONIC_PRINT(ERR, "RX mbuf alloc failed"); 914 return -ENOMEM; 915 } 916 917 nsegs = (len + buf_size - 1) / buf_size; 918 919 desc = &desc_base[q->head_idx]; 920 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(rxm)); 921 desc->addr = dma_addr; 922 desc->len = buf_size; 923 size = buf_size; 924 desc->opcode = (nsegs > 1) ? IONIC_RXQ_DESC_OPCODE_SG : 925 IONIC_RXQ_DESC_OPCODE_SIMPLE; 926 rxm->next = NULL; 927 928 prev_rxm_seg = rxm; 929 sg_desc = &sg_desc_base[q->head_idx]; 930 elem = sg_desc->elems; 931 for (j = 0; j < nsegs - 1 && j < IONIC_RX_MAX_SG_ELEMS; j++) { 932 struct rte_mbuf *rxm_seg; 933 rte_iova_t data_iova; 934 935 rxm_seg = rte_mbuf_raw_alloc(rxq->mb_pool); 936 if (rxm_seg == NULL) { 937 IONIC_PRINT(ERR, "RX mbuf alloc failed"); 938 return -ENOMEM; 939 } 940 941 data_iova = rte_mbuf_data_iova(rxm_seg); 942 dma_addr = rte_cpu_to_le_64(data_iova); 943 elem->addr = dma_addr; 944 elem->len = buf_size; 945 size += buf_size; 946 elem++; 947 rxm_seg->next = NULL; 948 prev_rxm_seg->next = rxm_seg; 949 prev_rxm_seg = rxm_seg; 950 } 951 952 if (size < len) 953 IONIC_PRINT(ERR, "Rx SG size is not sufficient (%d < %d)", 954 size, len); 955 956 ring_doorbell = ((q->head_idx + 1) & 957 IONIC_RX_RING_DOORBELL_STRIDE) == 0; 958 959 ionic_q_post(q, ring_doorbell, ionic_rx_clean, rxm); 960 } 961 962 return 0; 963 } 964 965 /* 966 * Start Receive Units for specified queue. 967 */ 968 int __rte_cold 969 ionic_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id) 970 { 971 uint32_t frame_size = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len; 972 uint8_t *rx_queue_state = eth_dev->data->rx_queue_state; 973 struct ionic_qcq *rxq; 974 int err; 975 976 if (rx_queue_state[rx_queue_id] == RTE_ETH_QUEUE_STATE_STARTED) { 977 IONIC_PRINT(DEBUG, "RX queue %u already started", 978 rx_queue_id); 979 return 0; 980 } 981 982 rxq = eth_dev->data->rx_queues[rx_queue_id]; 983 984 IONIC_PRINT(DEBUG, "Starting RX queue %u, %u descs (size: %u)", 985 rx_queue_id, rxq->q.num_descs, frame_size); 986 987 if (!(rxq->flags & IONIC_QCQ_F_INITED)) { 988 err = ionic_lif_rxq_init(rxq); 989 if (err) 990 return err; 991 } else { 992 ionic_qcq_enable(rxq); 993 } 994 995 /* Allocate buffers for descriptor rings */ 996 if (ionic_rx_fill(rxq, frame_size) != 0) { 997 IONIC_PRINT(ERR, "Could not alloc mbuf for queue:%d", 998 rx_queue_id); 999 return -1; 1000 } 1001 1002 rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 1003 1004 return 0; 1005 } 1006 1007 static inline void __rte_cold 1008 ionic_rxq_service(struct ionic_cq *cq, uint32_t work_to_do, 1009 void *service_cb_arg) 1010 { 1011 struct ionic_queue *q = cq->bound_q; 1012 struct ionic_desc_info *q_desc_info; 1013 struct ionic_rxq_comp *cq_desc_base = cq->base; 1014 struct ionic_rxq_comp *cq_desc; 1015 bool more; 1016 uint32_t curr_q_tail_idx, curr_cq_tail_idx; 1017 uint32_t work_done = 0; 1018 1019 if (work_to_do == 0) 1020 return; 1021 1022 cq_desc = &cq_desc_base[cq->tail_idx]; 1023 while (color_match(cq_desc->pkt_type_color, cq->done_color)) { 1024 curr_cq_tail_idx = cq->tail_idx; 1025 cq->tail_idx = (cq->tail_idx + 1) & (cq->num_descs - 1); 1026 1027 if (cq->tail_idx == 0) 1028 cq->done_color = !cq->done_color; 1029 1030 /* Prefetch the next 4 descriptors */ 1031 if ((cq->tail_idx & 0x3) == 0) 1032 rte_prefetch0(&cq_desc_base[cq->tail_idx]); 1033 1034 do { 1035 more = (q->tail_idx != cq_desc->comp_index); 1036 1037 q_desc_info = &q->info[q->tail_idx]; 1038 1039 curr_q_tail_idx = q->tail_idx; 1040 q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1); 1041 1042 /* Prefetch the next 4 descriptors */ 1043 if ((q->tail_idx & 0x3) == 0) 1044 /* q desc info */ 1045 rte_prefetch0(&q->info[q->tail_idx]); 1046 1047 ionic_rx_clean(q, curr_q_tail_idx, curr_cq_tail_idx, 1048 q_desc_info->cb_arg, service_cb_arg); 1049 1050 } while (more); 1051 1052 if (++work_done == work_to_do) 1053 break; 1054 1055 cq_desc = &cq_desc_base[cq->tail_idx]; 1056 } 1057 } 1058 1059 /* 1060 * Stop Receive Units for specified queue. 1061 */ 1062 int __rte_cold 1063 ionic_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id) 1064 { 1065 struct ionic_qcq *rxq; 1066 1067 IONIC_PRINT(DEBUG, "Stopping RX queue %u", rx_queue_id); 1068 1069 rxq = eth_dev->data->rx_queues[rx_queue_id]; 1070 1071 eth_dev->data->rx_queue_state[rx_queue_id] = 1072 RTE_ETH_QUEUE_STATE_STOPPED; 1073 1074 ionic_qcq_disable(rxq); 1075 1076 /* Flush */ 1077 ionic_rxq_service(&rxq->cq, -1, NULL); 1078 1079 return 0; 1080 } 1081 1082 uint16_t 1083 ionic_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 1084 uint16_t nb_pkts) 1085 { 1086 struct ionic_qcq *rxq = (struct ionic_qcq *)rx_queue; 1087 uint32_t frame_size = 1088 rxq->lif->eth_dev->data->dev_conf.rxmode.max_rx_pkt_len; 1089 struct ionic_cq *cq = &rxq->cq; 1090 struct ionic_rx_service service_cb_arg; 1091 1092 service_cb_arg.rx_pkts = rx_pkts; 1093 service_cb_arg.nb_pkts = nb_pkts; 1094 service_cb_arg.nb_rx = 0; 1095 1096 ionic_rxq_service(cq, nb_pkts, &service_cb_arg); 1097 1098 ionic_rx_fill(rxq, frame_size); 1099 1100 return service_cb_arg.nb_rx; 1101 } 1102