1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) 2 * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved. 3 */ 4 5 #include <stdbool.h> 6 7 #include <rte_memzone.h> 8 9 #include "ionic.h" 10 #include "ionic_ethdev.h" 11 #include "ionic_lif.h" 12 13 static const char * 14 ionic_error_to_str(enum ionic_status_code code) 15 { 16 switch (code) { 17 case IONIC_RC_SUCCESS: 18 return "IONIC_RC_SUCCESS"; 19 case IONIC_RC_EVERSION: 20 return "IONIC_RC_EVERSION"; 21 case IONIC_RC_EOPCODE: 22 return "IONIC_RC_EOPCODE"; 23 case IONIC_RC_EIO: 24 return "IONIC_RC_EIO"; 25 case IONIC_RC_EPERM: 26 return "IONIC_RC_EPERM"; 27 case IONIC_RC_EQID: 28 return "IONIC_RC_EQID"; 29 case IONIC_RC_EQTYPE: 30 return "IONIC_RC_EQTYPE"; 31 case IONIC_RC_ENOENT: 32 return "IONIC_RC_ENOENT"; 33 case IONIC_RC_EINTR: 34 return "IONIC_RC_EINTR"; 35 case IONIC_RC_EAGAIN: 36 return "IONIC_RC_EAGAIN"; 37 case IONIC_RC_ENOMEM: 38 return "IONIC_RC_ENOMEM"; 39 case IONIC_RC_EFAULT: 40 return "IONIC_RC_EFAULT"; 41 case IONIC_RC_EBUSY: 42 return "IONIC_RC_EBUSY"; 43 case IONIC_RC_EEXIST: 44 return "IONIC_RC_EEXIST"; 45 case IONIC_RC_EINVAL: 46 return "IONIC_RC_EINVAL"; 47 case IONIC_RC_ENOSPC: 48 return "IONIC_RC_ENOSPC"; 49 case IONIC_RC_ERANGE: 50 return "IONIC_RC_ERANGE"; 51 case IONIC_RC_BAD_ADDR: 52 return "IONIC_RC_BAD_ADDR"; 53 case IONIC_RC_DEV_CMD: 54 return "IONIC_RC_DEV_CMD"; 55 case IONIC_RC_ERROR: 56 return "IONIC_RC_ERROR"; 57 case IONIC_RC_ERDMA: 58 return "IONIC_RC_ERDMA"; 59 default: 60 return "IONIC_RC_UNKNOWN"; 61 } 62 } 63 64 const char * 65 ionic_opcode_to_str(enum ionic_cmd_opcode opcode) 66 { 67 switch (opcode) { 68 case IONIC_CMD_NOP: 69 return "IONIC_CMD_NOP"; 70 case IONIC_CMD_INIT: 71 return "IONIC_CMD_INIT"; 72 case IONIC_CMD_RESET: 73 return "IONIC_CMD_RESET"; 74 case IONIC_CMD_IDENTIFY: 75 return "IONIC_CMD_IDENTIFY"; 76 case IONIC_CMD_GETATTR: 77 return "IONIC_CMD_GETATTR"; 78 case IONIC_CMD_SETATTR: 79 return "IONIC_CMD_SETATTR"; 80 case IONIC_CMD_PORT_IDENTIFY: 81 return "IONIC_CMD_PORT_IDENTIFY"; 82 case IONIC_CMD_PORT_INIT: 83 return "IONIC_CMD_PORT_INIT"; 84 case IONIC_CMD_PORT_RESET: 85 return "IONIC_CMD_PORT_RESET"; 86 case IONIC_CMD_PORT_GETATTR: 87 return "IONIC_CMD_PORT_GETATTR"; 88 case IONIC_CMD_PORT_SETATTR: 89 return "IONIC_CMD_PORT_SETATTR"; 90 case IONIC_CMD_LIF_INIT: 91 return "IONIC_CMD_LIF_INIT"; 92 case IONIC_CMD_LIF_RESET: 93 return "IONIC_CMD_LIF_RESET"; 94 case IONIC_CMD_LIF_IDENTIFY: 95 return "IONIC_CMD_LIF_IDENTIFY"; 96 case IONIC_CMD_LIF_SETATTR: 97 return "IONIC_CMD_LIF_SETATTR"; 98 case IONIC_CMD_LIF_GETATTR: 99 return "IONIC_CMD_LIF_GETATTR"; 100 case IONIC_CMD_RX_MODE_SET: 101 return "IONIC_CMD_RX_MODE_SET"; 102 case IONIC_CMD_RX_FILTER_ADD: 103 return "IONIC_CMD_RX_FILTER_ADD"; 104 case IONIC_CMD_RX_FILTER_DEL: 105 return "IONIC_CMD_RX_FILTER_DEL"; 106 case IONIC_CMD_Q_INIT: 107 return "IONIC_CMD_Q_INIT"; 108 case IONIC_CMD_Q_CONTROL: 109 return "IONIC_CMD_Q_CONTROL"; 110 case IONIC_CMD_Q_IDENTIFY: 111 return "IONIC_CMD_Q_IDENTIFY"; 112 case IONIC_CMD_RDMA_RESET_LIF: 113 return "IONIC_CMD_RDMA_RESET_LIF"; 114 case IONIC_CMD_RDMA_CREATE_EQ: 115 return "IONIC_CMD_RDMA_CREATE_EQ"; 116 case IONIC_CMD_RDMA_CREATE_CQ: 117 return "IONIC_CMD_RDMA_CREATE_CQ"; 118 case IONIC_CMD_RDMA_CREATE_ADMINQ: 119 return "IONIC_CMD_RDMA_CREATE_ADMINQ"; 120 default: 121 return "DEVCMD_UNKNOWN"; 122 } 123 } 124 125 static int 126 ionic_adminq_check_err(struct ionic_admin_ctx *ctx, bool timeout) 127 { 128 const char *name; 129 const char *status; 130 131 name = ionic_opcode_to_str(ctx->cmd.cmd.opcode); 132 133 if (ctx->comp.comp.status || timeout) { 134 status = ionic_error_to_str(ctx->comp.comp.status); 135 IONIC_PRINT(ERR, "%s (%d) failed: %s (%d)", 136 name, 137 ctx->cmd.cmd.opcode, 138 timeout ? "TIMEOUT" : status, 139 timeout ? -1 : ctx->comp.comp.status); 140 return -EIO; 141 } 142 143 IONIC_PRINT(DEBUG, "%s (%d) succeeded", name, ctx->cmd.cmd.opcode); 144 145 return 0; 146 } 147 148 static bool 149 ionic_adminq_service(struct ionic_cq *cq, uint32_t cq_desc_index, 150 void *cb_arg __rte_unused) 151 { 152 struct ionic_admin_comp *cq_desc_base = cq->base; 153 struct ionic_admin_comp *cq_desc = &cq_desc_base[cq_desc_index]; 154 struct ionic_qcq *qcq = IONIC_CQ_TO_QCQ(cq); 155 struct ionic_queue *q = &qcq->q; 156 struct ionic_admin_ctx *ctx; 157 struct ionic_desc_info *desc_info; 158 uint16_t curr_q_tail_idx; 159 uint16_t stop_index; 160 161 if (!color_match(cq_desc->color, cq->done_color)) 162 return false; 163 164 stop_index = rte_le_to_cpu_16(cq_desc->comp_index); 165 166 do { 167 desc_info = &q->info[q->tail_idx]; 168 169 ctx = desc_info->cb_arg; 170 if (ctx) { 171 memcpy(&ctx->comp, cq_desc, sizeof(*cq_desc)); 172 173 ctx->pending_work = false; /* done */ 174 } 175 176 curr_q_tail_idx = q->tail_idx; 177 q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1); 178 } while (curr_q_tail_idx != stop_index); 179 180 return true; 181 } 182 183 /** ionic_adminq_post - Post an admin command. 184 * @lif: Handle to lif. 185 * @cmd_ctx: Api admin command context. 186 * 187 * Post the command to an admin queue in the ethernet driver. If this command 188 * succeeds, then the command has been posted, but that does not indicate a 189 * completion. If this command returns success, then the completion callback 190 * will eventually be called. 191 * 192 * Return: zero or negative error status. 193 */ 194 static int 195 ionic_adminq_post(struct ionic_lif *lif, struct ionic_admin_ctx *ctx) 196 { 197 struct ionic_queue *q = &lif->adminqcq->q; 198 struct ionic_admin_cmd *q_desc_base = q->base; 199 struct ionic_admin_cmd *q_desc; 200 int err = 0; 201 202 rte_spinlock_lock(&lif->adminq_lock); 203 204 if (ionic_q_space_avail(q) < 1) { 205 err = -ENOSPC; 206 goto err_out; 207 } 208 209 q_desc = &q_desc_base[q->head_idx]; 210 211 memcpy(q_desc, &ctx->cmd, sizeof(ctx->cmd)); 212 213 ionic_q_post(q, true, NULL, ctx); 214 215 err_out: 216 rte_spinlock_unlock(&lif->adminq_lock); 217 218 return err; 219 } 220 221 static int 222 ionic_adminq_wait_for_completion(struct ionic_lif *lif, 223 struct ionic_admin_ctx *ctx, unsigned long max_wait) 224 { 225 unsigned long step_usec = IONIC_DEVCMD_CHECK_PERIOD_US; 226 unsigned long max_wait_usec = max_wait * 1000000L; 227 unsigned long elapsed_usec = 0; 228 int budget = 8; 229 230 while (ctx->pending_work && elapsed_usec < max_wait_usec) { 231 /* 232 * Locking here as adminq is served inline and could be 233 * called from multiple places 234 */ 235 rte_spinlock_lock(&lif->adminq_service_lock); 236 237 ionic_qcq_service(lif->adminqcq, budget, 238 ionic_adminq_service, NULL); 239 240 rte_spinlock_unlock(&lif->adminq_service_lock); 241 242 rte_delay_us_block(step_usec); 243 elapsed_usec += step_usec; 244 } 245 246 return (!ctx->pending_work); 247 } 248 249 int 250 ionic_adminq_post_wait(struct ionic_lif *lif, struct ionic_admin_ctx *ctx) 251 { 252 bool done; 253 int err; 254 255 IONIC_PRINT(DEBUG, "Sending %s (%d) via the admin queue", 256 ionic_opcode_to_str(ctx->cmd.cmd.opcode), ctx->cmd.cmd.opcode); 257 258 err = ionic_adminq_post(lif, ctx); 259 if (err) { 260 IONIC_PRINT(ERR, "Failure posting %d to the admin queue (%d)", 261 ctx->cmd.cmd.opcode, err); 262 return err; 263 } 264 265 done = ionic_adminq_wait_for_completion(lif, ctx, 266 IONIC_DEVCMD_TIMEOUT); 267 268 return ionic_adminq_check_err(ctx, !done /* timed out */); 269 } 270 271 static int 272 ionic_dev_cmd_wait(struct ionic_dev *idev, unsigned long max_wait) 273 { 274 unsigned long step_usec = IONIC_DEVCMD_CHECK_PERIOD_US; 275 unsigned long max_wait_usec = max_wait * 1000000L; 276 unsigned long elapsed_usec = 0; 277 int done; 278 279 /* Wait for dev cmd to complete.. but no more than max_wait sec */ 280 281 do { 282 done = ionic_dev_cmd_done(idev); 283 if (done) { 284 IONIC_PRINT(DEBUG, "DEVCMD %d done took %ld usecs", 285 ioread8(&idev->dev_cmd->cmd.cmd.opcode), 286 elapsed_usec); 287 return 0; 288 } 289 290 rte_delay_us_block(step_usec); 291 292 elapsed_usec += step_usec; 293 } while (elapsed_usec < max_wait_usec); 294 295 IONIC_PRINT(ERR, "DEVCMD %d timeout after %ld usecs", 296 ioread8(&idev->dev_cmd->cmd.cmd.opcode), 297 elapsed_usec); 298 299 return -ETIMEDOUT; 300 } 301 302 static int 303 ionic_dev_cmd_check_error(struct ionic_dev *idev) 304 { 305 uint8_t status; 306 307 status = ionic_dev_cmd_status(idev); 308 if (status == 0) 309 return 0; 310 311 return -EIO; 312 } 313 314 int 315 ionic_dev_cmd_wait_check(struct ionic_dev *idev, unsigned long max_wait) 316 { 317 int err; 318 319 err = ionic_dev_cmd_wait(idev, max_wait); 320 321 if (!err) 322 err = ionic_dev_cmd_check_error(idev); 323 324 IONIC_PRINT(DEBUG, "dev_cmd returned %d", err); 325 return err; 326 } 327 328 int 329 ionic_setup(struct ionic_adapter *adapter) 330 { 331 return ionic_dev_setup(adapter); 332 } 333 334 int 335 ionic_identify(struct ionic_adapter *adapter) 336 { 337 struct ionic_dev *idev = &adapter->idev; 338 struct ionic_identity *ident = &adapter->ident; 339 uint32_t drv_size = RTE_DIM(ident->drv.words); 340 uint32_t cmd_size = RTE_DIM(idev->dev_cmd->data); 341 uint32_t dev_size = RTE_DIM(ident->dev.words); 342 uint32_t i, nwords; 343 int err; 344 345 memset(ident, 0, sizeof(*ident)); 346 347 ident->drv.os_type = IONIC_OS_TYPE_LINUX; 348 ident->drv.os_dist = 0; 349 snprintf(ident->drv.os_dist_str, 350 sizeof(ident->drv.os_dist_str), "Unknown"); 351 ident->drv.kernel_ver = 0; 352 snprintf(ident->drv.kernel_ver_str, 353 sizeof(ident->drv.kernel_ver_str), "DPDK"); 354 strncpy(ident->drv.driver_ver_str, IONIC_DRV_VERSION, 355 sizeof(ident->drv.driver_ver_str) - 1); 356 357 nwords = RTE_MIN(drv_size, cmd_size); 358 for (i = 0; i < nwords; i++) 359 iowrite32(ident->drv.words[i], &idev->dev_cmd->data[i]); 360 361 ionic_dev_cmd_identify(idev, IONIC_IDENTITY_VERSION_1); 362 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 363 if (!err) { 364 nwords = RTE_MIN(dev_size, cmd_size); 365 for (i = 0; i < nwords; i++) 366 ident->dev.words[i] = ioread32(&idev->dev_cmd->data[i]); 367 } 368 369 return err; 370 } 371 372 int 373 ionic_init(struct ionic_adapter *adapter) 374 { 375 struct ionic_dev *idev = &adapter->idev; 376 377 ionic_dev_cmd_init(idev); 378 return ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 379 } 380 381 int 382 ionic_reset(struct ionic_adapter *adapter) 383 { 384 struct ionic_dev *idev = &adapter->idev; 385 386 ionic_dev_cmd_reset(idev); 387 return ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 388 } 389 390 int 391 ionic_port_identify(struct ionic_adapter *adapter) 392 { 393 struct ionic_dev *idev = &adapter->idev; 394 struct ionic_identity *ident = &adapter->ident; 395 uint32_t port_words = RTE_DIM(ident->port.words); 396 uint32_t cmd_words = RTE_DIM(idev->dev_cmd->data); 397 uint32_t i, nwords; 398 int err; 399 400 ionic_dev_cmd_port_identify(idev); 401 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 402 if (!err) { 403 nwords = RTE_MIN(port_words, cmd_words); 404 for (i = 0; i < nwords; i++) 405 ident->port.words[i] = 406 ioread32(&idev->dev_cmd->data[i]); 407 } 408 409 IONIC_PRINT(INFO, "speed %d", 410 rte_le_to_cpu_32(ident->port.config.speed)); 411 IONIC_PRINT(INFO, "mtu %d", 412 rte_le_to_cpu_32(ident->port.config.mtu)); 413 IONIC_PRINT(INFO, "state %d", ident->port.config.state); 414 IONIC_PRINT(INFO, "an_enable %d", ident->port.config.an_enable); 415 IONIC_PRINT(INFO, "fec_type %d", ident->port.config.fec_type); 416 IONIC_PRINT(INFO, "pause_type %d", ident->port.config.pause_type); 417 IONIC_PRINT(INFO, "loopback_mode %d", 418 ident->port.config.loopback_mode); 419 420 return err; 421 } 422 423 static const struct rte_memzone * 424 ionic_memzone_reserve(const char *name, uint32_t len, int socket_id) 425 { 426 const struct rte_memzone *mz; 427 428 mz = rte_memzone_lookup(name); 429 if (mz) 430 return mz; 431 432 mz = rte_memzone_reserve_aligned(name, len, socket_id, 433 RTE_MEMZONE_IOVA_CONTIG, IONIC_ALIGN); 434 return mz; 435 } 436 437 int 438 ionic_port_init(struct ionic_adapter *adapter) 439 { 440 struct ionic_dev *idev = &adapter->idev; 441 struct ionic_identity *ident = &adapter->ident; 442 char z_name[RTE_MEMZONE_NAMESIZE]; 443 uint32_t config_words = RTE_DIM(ident->port.config.words); 444 uint32_t cmd_words = RTE_DIM(idev->dev_cmd->data); 445 uint32_t i, nwords; 446 int err; 447 448 if (idev->port_info) 449 return 0; 450 451 idev->port_info_sz = RTE_ALIGN(sizeof(*idev->port_info), PAGE_SIZE); 452 453 snprintf(z_name, sizeof(z_name), "%s_port_%s_info", 454 IONIC_DRV_NAME, adapter->name); 455 456 idev->port_info_z = ionic_memzone_reserve(z_name, idev->port_info_sz, 457 SOCKET_ID_ANY); 458 if (!idev->port_info_z) { 459 IONIC_PRINT(ERR, "Cannot reserve port info DMA memory"); 460 return -ENOMEM; 461 } 462 463 idev->port_info = idev->port_info_z->addr; 464 idev->port_info_pa = idev->port_info_z->iova; 465 466 nwords = RTE_MIN(config_words, cmd_words); 467 468 for (i = 0; i < nwords; i++) 469 iowrite32(ident->port.config.words[i], &idev->dev_cmd->data[i]); 470 471 idev->port_info->config.state = IONIC_PORT_ADMIN_STATE_UP; 472 ionic_dev_cmd_port_init(idev); 473 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 474 if (err) 475 IONIC_PRINT(ERR, "Failed to init port"); 476 477 return err; 478 } 479 480 int 481 ionic_port_reset(struct ionic_adapter *adapter) 482 { 483 struct ionic_dev *idev = &adapter->idev; 484 int err; 485 486 if (!idev->port_info) 487 return 0; 488 489 ionic_dev_cmd_port_reset(idev); 490 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 491 if (err) { 492 IONIC_PRINT(ERR, "Failed to reset port"); 493 return err; 494 } 495 496 idev->port_info = NULL; 497 idev->port_info_pa = 0; 498 499 return 0; 500 } 501