1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) 2 * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved. 3 */ 4 5 #include <rte_malloc.h> 6 #include <ethdev_driver.h> 7 8 #include "ionic.h" 9 #include "ionic_logs.h" 10 #include "ionic_lif.h" 11 #include "ionic_ethdev.h" 12 #include "ionic_rx_filter.h" 13 #include "ionic_rxtx.h" 14 15 /* queuetype support level */ 16 static const uint8_t ionic_qtype_vers[IONIC_QTYPE_MAX] = { 17 [IONIC_QTYPE_ADMINQ] = 0, /* 0 = Base version with CQ support */ 18 [IONIC_QTYPE_NOTIFYQ] = 0, /* 0 = Base version */ 19 [IONIC_QTYPE_RXQ] = 2, /* 0 = Base version with CQ+SG support 20 * 1 = ... with EQ 21 * 2 = ... with CMB 22 */ 23 [IONIC_QTYPE_TXQ] = 3, /* 0 = Base version with CQ+SG support 24 * 1 = ... with Tx SG version 1 25 * 2 = ... with EQ 26 * 3 = ... with CMB 27 */ 28 }; 29 30 static int ionic_lif_addr_add(struct ionic_lif *lif, const uint8_t *addr); 31 static int ionic_lif_addr_del(struct ionic_lif *lif, const uint8_t *addr); 32 33 int 34 ionic_qcq_enable(struct ionic_qcq *qcq) 35 { 36 struct ionic_queue *q = &qcq->q; 37 struct ionic_lif *lif = qcq->lif; 38 struct ionic_admin_ctx ctx = { 39 .pending_work = true, 40 .cmd.q_control = { 41 .opcode = IONIC_CMD_Q_CONTROL, 42 .type = q->type, 43 .index = rte_cpu_to_le_32(q->index), 44 .oper = IONIC_Q_ENABLE, 45 }, 46 }; 47 48 return ionic_adminq_post_wait(lif, &ctx); 49 } 50 51 int 52 ionic_qcq_disable(struct ionic_qcq *qcq) 53 { 54 struct ionic_queue *q = &qcq->q; 55 struct ionic_lif *lif = qcq->lif; 56 struct ionic_admin_ctx ctx = { 57 .pending_work = true, 58 .cmd.q_control = { 59 .opcode = IONIC_CMD_Q_CONTROL, 60 .type = q->type, 61 .index = rte_cpu_to_le_32(q->index), 62 .oper = IONIC_Q_DISABLE, 63 }, 64 }; 65 66 return ionic_adminq_post_wait(lif, &ctx); 67 } 68 69 void 70 ionic_lif_stop(struct ionic_lif *lif) 71 { 72 uint32_t i; 73 74 IONIC_PRINT_CALL(); 75 76 lif->state &= ~IONIC_LIF_F_UP; 77 78 for (i = 0; i < lif->nrxqcqs; i++) { 79 struct ionic_rx_qcq *rxq = lif->rxqcqs[i]; 80 if (rxq->flags & IONIC_QCQ_F_INITED) 81 (void)ionic_dev_rx_queue_stop(lif->eth_dev, i); 82 } 83 84 for (i = 0; i < lif->ntxqcqs; i++) { 85 struct ionic_tx_qcq *txq = lif->txqcqs[i]; 86 if (txq->flags & IONIC_QCQ_F_INITED) 87 (void)ionic_dev_tx_queue_stop(lif->eth_dev, i); 88 } 89 } 90 91 void 92 ionic_lif_reset(struct ionic_lif *lif) 93 { 94 struct ionic_dev *idev = &lif->adapter->idev; 95 int err; 96 97 IONIC_PRINT_CALL(); 98 99 ionic_dev_cmd_lif_reset(idev); 100 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 101 if (err) 102 IONIC_PRINT(WARNING, "Failed to reset %s", lif->name); 103 } 104 105 static void 106 ionic_lif_get_abs_stats(const struct ionic_lif *lif, struct rte_eth_stats *stats) 107 { 108 struct ionic_lif_stats *ls = &lif->info->stats; 109 uint32_t i; 110 uint32_t num_rx_q_counters = RTE_MIN(lif->nrxqcqs, (uint32_t) 111 RTE_ETHDEV_QUEUE_STAT_CNTRS); 112 uint32_t num_tx_q_counters = RTE_MIN(lif->ntxqcqs, (uint32_t) 113 RTE_ETHDEV_QUEUE_STAT_CNTRS); 114 115 memset(stats, 0, sizeof(*stats)); 116 117 if (ls == NULL) { 118 IONIC_PRINT(DEBUG, "Stats on port %u not yet initialized", 119 lif->port_id); 120 return; 121 } 122 123 /* RX */ 124 125 stats->ipackets = ls->rx_ucast_packets + 126 ls->rx_mcast_packets + 127 ls->rx_bcast_packets; 128 129 stats->ibytes = ls->rx_ucast_bytes + 130 ls->rx_mcast_bytes + 131 ls->rx_bcast_bytes; 132 133 for (i = 0; i < lif->nrxqcqs; i++) { 134 struct ionic_rx_stats *rx_stats = &lif->rxqcqs[i]->stats; 135 stats->imissed += 136 rx_stats->no_cb_arg + 137 rx_stats->bad_cq_status + 138 rx_stats->no_room + 139 rx_stats->bad_len; 140 } 141 142 stats->imissed += 143 ls->rx_ucast_drop_packets + 144 ls->rx_mcast_drop_packets + 145 ls->rx_bcast_drop_packets; 146 147 stats->imissed += 148 ls->rx_queue_empty + 149 ls->rx_dma_error + 150 ls->rx_queue_disabled + 151 ls->rx_desc_fetch_error + 152 ls->rx_desc_data_error; 153 154 for (i = 0; i < num_rx_q_counters; i++) { 155 struct ionic_rx_stats *rx_stats = &lif->rxqcqs[i]->stats; 156 stats->q_ipackets[i] = rx_stats->packets; 157 stats->q_ibytes[i] = rx_stats->bytes; 158 stats->q_errors[i] = 159 rx_stats->no_cb_arg + 160 rx_stats->bad_cq_status + 161 rx_stats->no_room + 162 rx_stats->bad_len; 163 } 164 165 /* TX */ 166 167 stats->opackets = ls->tx_ucast_packets + 168 ls->tx_mcast_packets + 169 ls->tx_bcast_packets; 170 171 stats->obytes = ls->tx_ucast_bytes + 172 ls->tx_mcast_bytes + 173 ls->tx_bcast_bytes; 174 175 for (i = 0; i < lif->ntxqcqs; i++) { 176 struct ionic_tx_stats *tx_stats = &lif->txqcqs[i]->stats; 177 stats->oerrors += tx_stats->drop; 178 } 179 180 stats->oerrors += 181 ls->tx_ucast_drop_packets + 182 ls->tx_mcast_drop_packets + 183 ls->tx_bcast_drop_packets; 184 185 stats->oerrors += 186 ls->tx_dma_error + 187 ls->tx_queue_disabled + 188 ls->tx_desc_fetch_error + 189 ls->tx_desc_data_error; 190 191 for (i = 0; i < num_tx_q_counters; i++) { 192 struct ionic_tx_stats *tx_stats = &lif->txqcqs[i]->stats; 193 stats->q_opackets[i] = tx_stats->packets; 194 stats->q_obytes[i] = tx_stats->bytes; 195 } 196 } 197 198 void 199 ionic_lif_get_stats(const struct ionic_lif *lif, 200 struct rte_eth_stats *stats) 201 { 202 ionic_lif_get_abs_stats(lif, stats); 203 204 stats->ipackets -= lif->stats_base.ipackets; 205 stats->opackets -= lif->stats_base.opackets; 206 stats->ibytes -= lif->stats_base.ibytes; 207 stats->obytes -= lif->stats_base.obytes; 208 stats->imissed -= lif->stats_base.imissed; 209 stats->ierrors -= lif->stats_base.ierrors; 210 stats->oerrors -= lif->stats_base.oerrors; 211 stats->rx_nombuf -= lif->stats_base.rx_nombuf; 212 } 213 214 void 215 ionic_lif_reset_stats(struct ionic_lif *lif) 216 { 217 uint32_t i; 218 219 for (i = 0; i < lif->nrxqcqs; i++) { 220 memset(&lif->rxqcqs[i]->stats, 0, 221 sizeof(struct ionic_rx_stats)); 222 memset(&lif->txqcqs[i]->stats, 0, 223 sizeof(struct ionic_tx_stats)); 224 } 225 226 ionic_lif_get_abs_stats(lif, &lif->stats_base); 227 } 228 229 void 230 ionic_lif_get_hw_stats(struct ionic_lif *lif, struct ionic_lif_stats *stats) 231 { 232 uint16_t i, count = sizeof(struct ionic_lif_stats) / sizeof(uint64_t); 233 uint64_t *stats64 = (uint64_t *)stats; 234 uint64_t *lif_stats64 = (uint64_t *)&lif->info->stats; 235 uint64_t *lif_stats64_base = (uint64_t *)&lif->lif_stats_base; 236 237 for (i = 0; i < count; i++) 238 stats64[i] = lif_stats64[i] - lif_stats64_base[i]; 239 } 240 241 void 242 ionic_lif_reset_hw_stats(struct ionic_lif *lif) 243 { 244 uint16_t i, count = sizeof(struct ionic_lif_stats) / sizeof(uint64_t); 245 uint64_t *lif_stats64 = (uint64_t *)&lif->info->stats; 246 uint64_t *lif_stats64_base = (uint64_t *)&lif->lif_stats_base; 247 248 for (i = 0; i < count; i++) 249 lif_stats64_base[i] = lif_stats64[i]; 250 } 251 252 static int 253 ionic_lif_addr_add(struct ionic_lif *lif, const uint8_t *addr) 254 { 255 struct ionic_admin_ctx ctx = { 256 .pending_work = true, 257 .cmd.rx_filter_add = { 258 .opcode = IONIC_CMD_RX_FILTER_ADD, 259 .match = rte_cpu_to_le_16(IONIC_RX_FILTER_MATCH_MAC), 260 }, 261 }; 262 int err; 263 264 memcpy(ctx.cmd.rx_filter_add.mac.addr, addr, RTE_ETHER_ADDR_LEN); 265 266 err = ionic_adminq_post_wait(lif, &ctx); 267 if (err) 268 return err; 269 270 IONIC_PRINT(INFO, "rx_filter add (id %d)", 271 rte_le_to_cpu_32(ctx.comp.rx_filter_add.filter_id)); 272 273 return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, &ctx); 274 } 275 276 static int 277 ionic_lif_addr_del(struct ionic_lif *lif, const uint8_t *addr) 278 { 279 struct ionic_admin_ctx ctx = { 280 .pending_work = true, 281 .cmd.rx_filter_del = { 282 .opcode = IONIC_CMD_RX_FILTER_DEL, 283 }, 284 }; 285 struct ionic_rx_filter *f; 286 int err; 287 288 IONIC_PRINT_CALL(); 289 290 rte_spinlock_lock(&lif->rx_filters.lock); 291 292 f = ionic_rx_filter_by_addr(lif, addr); 293 if (!f) { 294 rte_spinlock_unlock(&lif->rx_filters.lock); 295 return -ENOENT; 296 } 297 298 ctx.cmd.rx_filter_del.filter_id = rte_cpu_to_le_32(f->filter_id); 299 ionic_rx_filter_free(f); 300 301 rte_spinlock_unlock(&lif->rx_filters.lock); 302 303 err = ionic_adminq_post_wait(lif, &ctx); 304 if (err) 305 return err; 306 307 IONIC_PRINT(INFO, "rx_filter del (id %d)", 308 rte_le_to_cpu_32(ctx.cmd.rx_filter_del.filter_id)); 309 310 return 0; 311 } 312 313 int 314 ionic_dev_add_mac(struct rte_eth_dev *eth_dev, 315 struct rte_ether_addr *mac_addr, 316 uint32_t index __rte_unused, uint32_t pool __rte_unused) 317 { 318 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 319 320 IONIC_PRINT_CALL(); 321 322 return ionic_lif_addr_add(lif, (const uint8_t *)mac_addr); 323 } 324 325 void 326 ionic_dev_remove_mac(struct rte_eth_dev *eth_dev, uint32_t index) 327 { 328 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 329 struct ionic_adapter *adapter = lif->adapter; 330 struct rte_ether_addr *mac_addr; 331 332 IONIC_PRINT_CALL(); 333 334 if (index >= adapter->max_mac_addrs) { 335 IONIC_PRINT(WARNING, 336 "Index %u is above MAC filter limit %u", 337 index, adapter->max_mac_addrs); 338 return; 339 } 340 341 mac_addr = ð_dev->data->mac_addrs[index]; 342 343 if (!rte_is_valid_assigned_ether_addr(mac_addr)) 344 return; 345 346 ionic_lif_addr_del(lif, (const uint8_t *)mac_addr); 347 } 348 349 int 350 ionic_dev_set_mac(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr) 351 { 352 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 353 354 IONIC_PRINT_CALL(); 355 356 if (mac_addr == NULL) { 357 IONIC_PRINT(NOTICE, "New mac is null"); 358 return -1; 359 } 360 361 if (!rte_is_zero_ether_addr((struct rte_ether_addr *)lif->mac_addr)) { 362 IONIC_PRINT(INFO, "Deleting mac addr %pM", 363 lif->mac_addr); 364 ionic_lif_addr_del(lif, lif->mac_addr); 365 memset(lif->mac_addr, 0, RTE_ETHER_ADDR_LEN); 366 } 367 368 IONIC_PRINT(INFO, "Updating mac addr"); 369 370 rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)lif->mac_addr); 371 372 return ionic_lif_addr_add(lif, (const uint8_t *)mac_addr); 373 } 374 375 static int 376 ionic_vlan_rx_add_vid(struct ionic_lif *lif, uint16_t vid) 377 { 378 struct ionic_admin_ctx ctx = { 379 .pending_work = true, 380 .cmd.rx_filter_add = { 381 .opcode = IONIC_CMD_RX_FILTER_ADD, 382 .match = rte_cpu_to_le_16(IONIC_RX_FILTER_MATCH_VLAN), 383 .vlan.vlan = rte_cpu_to_le_16(vid), 384 }, 385 }; 386 int err; 387 388 err = ionic_adminq_post_wait(lif, &ctx); 389 if (err) 390 return err; 391 392 IONIC_PRINT(INFO, "rx_filter add VLAN %d (id %d)", vid, 393 rte_le_to_cpu_32(ctx.comp.rx_filter_add.filter_id)); 394 395 return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, &ctx); 396 } 397 398 static int 399 ionic_vlan_rx_kill_vid(struct ionic_lif *lif, uint16_t vid) 400 { 401 struct ionic_admin_ctx ctx = { 402 .pending_work = true, 403 .cmd.rx_filter_del = { 404 .opcode = IONIC_CMD_RX_FILTER_DEL, 405 }, 406 }; 407 struct ionic_rx_filter *f; 408 int err; 409 410 IONIC_PRINT_CALL(); 411 412 rte_spinlock_lock(&lif->rx_filters.lock); 413 414 f = ionic_rx_filter_by_vlan(lif, vid); 415 if (!f) { 416 rte_spinlock_unlock(&lif->rx_filters.lock); 417 return -ENOENT; 418 } 419 420 ctx.cmd.rx_filter_del.filter_id = rte_cpu_to_le_32(f->filter_id); 421 ionic_rx_filter_free(f); 422 rte_spinlock_unlock(&lif->rx_filters.lock); 423 424 err = ionic_adminq_post_wait(lif, &ctx); 425 if (err) 426 return err; 427 428 IONIC_PRINT(INFO, "rx_filter del VLAN %d (id %d)", vid, 429 rte_le_to_cpu_32(ctx.cmd.rx_filter_del.filter_id)); 430 431 return 0; 432 } 433 434 int 435 ionic_dev_vlan_filter_set(struct rte_eth_dev *eth_dev, uint16_t vlan_id, 436 int on) 437 { 438 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 439 int err; 440 441 if (on) 442 err = ionic_vlan_rx_add_vid(lif, vlan_id); 443 else 444 err = ionic_vlan_rx_kill_vid(lif, vlan_id); 445 446 return err; 447 } 448 449 static void 450 ionic_lif_rx_mode(struct ionic_lif *lif, uint32_t rx_mode) 451 { 452 struct ionic_admin_ctx ctx = { 453 .pending_work = true, 454 .cmd.rx_mode_set = { 455 .opcode = IONIC_CMD_RX_MODE_SET, 456 .rx_mode = rte_cpu_to_le_16(rx_mode), 457 }, 458 }; 459 int err; 460 461 if (rx_mode & IONIC_RX_MODE_F_UNICAST) 462 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_UNICAST"); 463 if (rx_mode & IONIC_RX_MODE_F_MULTICAST) 464 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_MULTICAST"); 465 if (rx_mode & IONIC_RX_MODE_F_BROADCAST) 466 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_BROADCAST"); 467 if (rx_mode & IONIC_RX_MODE_F_PROMISC) 468 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_PROMISC"); 469 if (rx_mode & IONIC_RX_MODE_F_ALLMULTI) 470 IONIC_PRINT(DEBUG, "rx_mode IONIC_RX_MODE_F_ALLMULTI"); 471 472 err = ionic_adminq_post_wait(lif, &ctx); 473 if (err) 474 IONIC_PRINT(ERR, "Failure setting RX mode"); 475 } 476 477 static void 478 ionic_set_rx_mode(struct ionic_lif *lif, uint32_t rx_mode) 479 { 480 if (lif->rx_mode != rx_mode) { 481 lif->rx_mode = rx_mode; 482 ionic_lif_rx_mode(lif, rx_mode); 483 } 484 } 485 486 int 487 ionic_dev_promiscuous_enable(struct rte_eth_dev *eth_dev) 488 { 489 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 490 uint32_t rx_mode = lif->rx_mode; 491 492 IONIC_PRINT_CALL(); 493 494 rx_mode |= IONIC_RX_MODE_F_PROMISC; 495 496 ionic_set_rx_mode(lif, rx_mode); 497 498 return 0; 499 } 500 501 int 502 ionic_dev_promiscuous_disable(struct rte_eth_dev *eth_dev) 503 { 504 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 505 uint32_t rx_mode = lif->rx_mode; 506 507 rx_mode &= ~IONIC_RX_MODE_F_PROMISC; 508 509 ionic_set_rx_mode(lif, rx_mode); 510 511 return 0; 512 } 513 514 int 515 ionic_dev_allmulticast_enable(struct rte_eth_dev *eth_dev) 516 { 517 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 518 uint32_t rx_mode = lif->rx_mode; 519 520 rx_mode |= IONIC_RX_MODE_F_ALLMULTI; 521 522 ionic_set_rx_mode(lif, rx_mode); 523 524 return 0; 525 } 526 527 int 528 ionic_dev_allmulticast_disable(struct rte_eth_dev *eth_dev) 529 { 530 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 531 uint32_t rx_mode = lif->rx_mode; 532 533 rx_mode &= ~IONIC_RX_MODE_F_ALLMULTI; 534 535 ionic_set_rx_mode(lif, rx_mode); 536 537 return 0; 538 } 539 540 int 541 ionic_lif_change_mtu(struct ionic_lif *lif, int new_mtu) 542 { 543 struct ionic_admin_ctx ctx = { 544 .pending_work = true, 545 .cmd.lif_setattr = { 546 .opcode = IONIC_CMD_LIF_SETATTR, 547 .attr = IONIC_LIF_ATTR_MTU, 548 .mtu = rte_cpu_to_le_32(new_mtu), 549 }, 550 }; 551 int err; 552 553 err = ionic_adminq_post_wait(lif, &ctx); 554 if (err) 555 return err; 556 557 return 0; 558 } 559 560 int 561 ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr) 562 { 563 struct ionic_adapter *adapter = lif->adapter; 564 struct ionic_dev *idev = &adapter->idev; 565 unsigned long index; 566 567 /* 568 * Note: interrupt handler is called for index = 0 only 569 * (we use interrupts for the notifyq only anyway, 570 * which has index = 0) 571 */ 572 573 for (index = 0; index < adapter->nintrs; index++) 574 if (!adapter->intrs[index]) 575 break; 576 577 if (index == adapter->nintrs) 578 return -ENOSPC; 579 580 adapter->intrs[index] = true; 581 582 ionic_intr_init(idev, intr, index); 583 584 return 0; 585 } 586 587 static int 588 ionic_qcq_alloc(struct ionic_lif *lif, 589 uint8_t type, 590 size_t struct_size, 591 uint32_t socket_id, 592 uint32_t index, 593 const char *type_name, 594 uint16_t flags, 595 uint16_t num_descs, 596 uint16_t desc_size, 597 uint16_t cq_desc_size, 598 uint16_t sg_desc_size, 599 struct ionic_qcq **qcq) 600 { 601 struct ionic_qcq *new; 602 uint32_t q_size, cq_size, sg_size, total_size; 603 void *q_base, *cq_base, *sg_base; 604 rte_iova_t q_base_pa = 0; 605 rte_iova_t cq_base_pa = 0; 606 rte_iova_t sg_base_pa = 0; 607 int err; 608 609 *qcq = NULL; 610 611 q_size = num_descs * desc_size; 612 cq_size = num_descs * cq_desc_size; 613 sg_size = num_descs * sg_desc_size; 614 615 total_size = RTE_ALIGN(q_size, PAGE_SIZE) + 616 RTE_ALIGN(cq_size, PAGE_SIZE); 617 /* 618 * Note: aligning q_size/cq_size is not enough due to cq_base address 619 * aligning as q_base could be not aligned to the page. 620 * Adding PAGE_SIZE. 621 */ 622 total_size += PAGE_SIZE; 623 624 if (flags & IONIC_QCQ_F_SG) { 625 total_size += RTE_ALIGN(sg_size, PAGE_SIZE); 626 total_size += PAGE_SIZE; 627 } 628 629 new = rte_zmalloc("ionic", struct_size, 0); 630 if (!new) { 631 IONIC_PRINT(ERR, "Cannot allocate queue structure"); 632 return -ENOMEM; 633 } 634 635 new->lif = lif; 636 637 new->q.info = rte_calloc_socket("ionic", 638 num_descs, sizeof(void *), 639 PAGE_SIZE, socket_id); 640 if (!new->q.info) { 641 IONIC_PRINT(ERR, "Cannot allocate queue info"); 642 err = -ENOMEM; 643 goto err_out_free_qcq; 644 } 645 646 new->q.type = type; 647 648 err = ionic_q_init(&new->q, index, num_descs); 649 if (err) { 650 IONIC_PRINT(ERR, "Queue initialization failed"); 651 goto err_out_free_info; 652 } 653 654 err = ionic_cq_init(&new->cq, num_descs); 655 if (err) { 656 IONIC_PRINT(ERR, "Completion queue initialization failed"); 657 goto err_out_free_info; 658 } 659 660 new->base_z = rte_eth_dma_zone_reserve(lif->eth_dev, 661 type_name, index /* queue_idx */, 662 total_size, IONIC_ALIGN, socket_id); 663 664 if (!new->base_z) { 665 IONIC_PRINT(ERR, "Cannot reserve queue DMA memory"); 666 err = -ENOMEM; 667 goto err_out_free_info; 668 } 669 670 new->base = new->base_z->addr; 671 new->base_pa = new->base_z->iova; 672 673 q_base = new->base; 674 q_base_pa = new->base_pa; 675 676 cq_base = (void *)RTE_ALIGN((uintptr_t)q_base + q_size, PAGE_SIZE); 677 cq_base_pa = RTE_ALIGN(q_base_pa + q_size, PAGE_SIZE); 678 679 if (flags & IONIC_QCQ_F_SG) { 680 sg_base = (void *)RTE_ALIGN((uintptr_t)cq_base + cq_size, 681 PAGE_SIZE); 682 sg_base_pa = RTE_ALIGN(cq_base_pa + cq_size, PAGE_SIZE); 683 ionic_q_sg_map(&new->q, sg_base, sg_base_pa); 684 } 685 686 IONIC_PRINT(DEBUG, "Q-Base-PA = %#jx CQ-Base-PA = %#jx " 687 "SG-base-PA = %#jx", 688 q_base_pa, cq_base_pa, sg_base_pa); 689 690 ionic_q_map(&new->q, q_base, q_base_pa); 691 ionic_cq_map(&new->cq, cq_base, cq_base_pa); 692 693 *qcq = new; 694 695 return 0; 696 697 err_out_free_info: 698 rte_free(new->q.info); 699 err_out_free_qcq: 700 rte_free(new); 701 702 return err; 703 } 704 705 void 706 ionic_qcq_free(struct ionic_qcq *qcq) 707 { 708 if (qcq->base_z) { 709 qcq->base = NULL; 710 qcq->base_pa = 0; 711 rte_memzone_free(qcq->base_z); 712 qcq->base_z = NULL; 713 } 714 715 if (qcq->q.info) { 716 rte_free(qcq->q.info); 717 qcq->q.info = NULL; 718 } 719 720 rte_free(qcq); 721 } 722 723 int 724 ionic_rx_qcq_alloc(struct ionic_lif *lif, uint32_t socket_id, uint32_t index, 725 uint16_t nrxq_descs, struct ionic_rx_qcq **rxq_out) 726 { 727 struct ionic_rx_qcq *rxq; 728 uint16_t flags; 729 int err; 730 731 flags = IONIC_QCQ_F_SG; 732 err = ionic_qcq_alloc(lif, 733 IONIC_QTYPE_RXQ, 734 sizeof(struct ionic_rx_qcq), 735 socket_id, 736 index, 737 "rx", 738 flags, 739 nrxq_descs, 740 sizeof(struct ionic_rxq_desc), 741 sizeof(struct ionic_rxq_comp), 742 sizeof(struct ionic_rxq_sg_desc), 743 (struct ionic_qcq **)&rxq); 744 if (err) 745 return err; 746 747 rxq->flags = flags; 748 749 lif->rxqcqs[index] = rxq; 750 *rxq_out = rxq; 751 752 return 0; 753 } 754 755 int 756 ionic_tx_qcq_alloc(struct ionic_lif *lif, uint32_t socket_id, uint32_t index, 757 uint16_t ntxq_descs, struct ionic_tx_qcq **txq_out) 758 { 759 struct ionic_tx_qcq *txq; 760 uint16_t flags, num_segs_fw; 761 int err; 762 763 flags = IONIC_QCQ_F_SG; 764 765 num_segs_fw = IONIC_TX_MAX_SG_ELEMS_V1 + 1; 766 767 err = ionic_qcq_alloc(lif, 768 IONIC_QTYPE_TXQ, 769 sizeof(struct ionic_tx_qcq), 770 socket_id, 771 index, 772 "tx", 773 flags, 774 ntxq_descs, 775 sizeof(struct ionic_txq_desc), 776 sizeof(struct ionic_txq_comp), 777 sizeof(struct ionic_txq_sg_desc_v1), 778 (struct ionic_qcq **)&txq); 779 if (err) 780 return err; 781 782 txq->flags = flags; 783 txq->num_segs_fw = num_segs_fw; 784 785 lif->txqcqs[index] = txq; 786 *txq_out = txq; 787 788 return 0; 789 } 790 791 static int 792 ionic_admin_qcq_alloc(struct ionic_lif *lif) 793 { 794 uint16_t flags = 0; 795 int err; 796 797 err = ionic_qcq_alloc(lif, 798 IONIC_QTYPE_ADMINQ, 799 sizeof(struct ionic_admin_qcq), 800 rte_socket_id(), 801 0, 802 "admin", 803 flags, 804 IONIC_ADMINQ_LENGTH, 805 sizeof(struct ionic_admin_cmd), 806 sizeof(struct ionic_admin_comp), 807 0, 808 (struct ionic_qcq **)&lif->adminqcq); 809 if (err) 810 return err; 811 812 return 0; 813 } 814 815 static int 816 ionic_notify_qcq_alloc(struct ionic_lif *lif) 817 { 818 struct ionic_notify_qcq *nqcq; 819 struct ionic_dev *idev = &lif->adapter->idev; 820 uint16_t flags = 0; 821 int err; 822 823 err = ionic_qcq_alloc(lif, 824 IONIC_QTYPE_NOTIFYQ, 825 sizeof(struct ionic_notify_qcq), 826 rte_socket_id(), 827 0, 828 "notify", 829 flags, 830 IONIC_NOTIFYQ_LENGTH, 831 sizeof(struct ionic_notifyq_cmd), 832 sizeof(union ionic_notifyq_comp), 833 0, 834 (struct ionic_qcq **)&nqcq); 835 if (err) 836 return err; 837 838 err = ionic_intr_alloc(lif, &nqcq->intr); 839 if (err) { 840 ionic_qcq_free(&nqcq->qcq); 841 return err; 842 } 843 844 ionic_intr_mask_assert(idev->intr_ctrl, nqcq->intr.index, 845 IONIC_INTR_MASK_SET); 846 847 lif->notifyqcq = nqcq; 848 849 return 0; 850 } 851 852 static void * 853 ionic_bus_map_dbpage(struct ionic_adapter *adapter, int page_num) 854 { 855 char *vaddr = adapter->bars[IONIC_PCI_BAR_DBELL].vaddr; 856 857 if (adapter->num_bars <= IONIC_PCI_BAR_DBELL) 858 return NULL; 859 860 return (void *)&vaddr[page_num << PAGE_SHIFT]; 861 } 862 863 static void 864 ionic_lif_queue_identify(struct ionic_lif *lif) 865 { 866 struct ionic_adapter *adapter = lif->adapter; 867 struct ionic_dev *idev = &adapter->idev; 868 union ionic_q_identity *q_ident = &adapter->ident.txq; 869 uint32_t q_words = RTE_DIM(q_ident->words); 870 uint32_t cmd_words = RTE_DIM(idev->dev_cmd->data); 871 uint32_t i, nwords, qtype; 872 int err; 873 874 for (qtype = 0; qtype < RTE_DIM(ionic_qtype_vers); qtype++) { 875 struct ionic_qtype_info *qti = &lif->qtype_info[qtype]; 876 877 /* Filter out the types this driver knows about */ 878 switch (qtype) { 879 case IONIC_QTYPE_ADMINQ: 880 case IONIC_QTYPE_NOTIFYQ: 881 case IONIC_QTYPE_RXQ: 882 case IONIC_QTYPE_TXQ: 883 break; 884 default: 885 continue; 886 } 887 888 memset(qti, 0, sizeof(*qti)); 889 890 ionic_dev_cmd_queue_identify(idev, IONIC_LIF_TYPE_CLASSIC, 891 qtype, ionic_qtype_vers[qtype]); 892 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 893 if (err == -EINVAL) { 894 IONIC_PRINT(ERR, "qtype %d not supported\n", qtype); 895 continue; 896 } else if (err == -EIO) { 897 IONIC_PRINT(ERR, "q_ident failed, older FW\n"); 898 return; 899 } else if (err) { 900 IONIC_PRINT(ERR, "q_ident failed, qtype %d: %d\n", 901 qtype, err); 902 return; 903 } 904 905 nwords = RTE_MIN(q_words, cmd_words); 906 for (i = 0; i < nwords; i++) 907 q_ident->words[i] = ioread32(&idev->dev_cmd->data[i]); 908 909 qti->version = q_ident->version; 910 qti->supported = q_ident->supported; 911 qti->features = rte_le_to_cpu_64(q_ident->features); 912 qti->desc_sz = rte_le_to_cpu_16(q_ident->desc_sz); 913 qti->comp_sz = rte_le_to_cpu_16(q_ident->comp_sz); 914 qti->sg_desc_sz = rte_le_to_cpu_16(q_ident->sg_desc_sz); 915 qti->max_sg_elems = rte_le_to_cpu_16(q_ident->max_sg_elems); 916 qti->sg_desc_stride = 917 rte_le_to_cpu_16(q_ident->sg_desc_stride); 918 919 IONIC_PRINT(DEBUG, " qtype[%d].version = %d", 920 qtype, qti->version); 921 IONIC_PRINT(DEBUG, " qtype[%d].supported = %#x", 922 qtype, qti->supported); 923 IONIC_PRINT(DEBUG, " qtype[%d].features = %#jx", 924 qtype, qti->features); 925 IONIC_PRINT(DEBUG, " qtype[%d].desc_sz = %d", 926 qtype, qti->desc_sz); 927 IONIC_PRINT(DEBUG, " qtype[%d].comp_sz = %d", 928 qtype, qti->comp_sz); 929 IONIC_PRINT(DEBUG, " qtype[%d].sg_desc_sz = %d", 930 qtype, qti->sg_desc_sz); 931 IONIC_PRINT(DEBUG, " qtype[%d].max_sg_elems = %d", 932 qtype, qti->max_sg_elems); 933 IONIC_PRINT(DEBUG, " qtype[%d].sg_desc_stride = %d", 934 qtype, qti->sg_desc_stride); 935 } 936 } 937 938 int 939 ionic_lif_alloc(struct ionic_lif *lif) 940 { 941 struct ionic_adapter *adapter = lif->adapter; 942 uint32_t socket_id = rte_socket_id(); 943 int err; 944 945 /* 946 * lif->name was zeroed on allocation. 947 * Copy (sizeof() - 1) bytes to ensure that it is NULL terminated. 948 */ 949 memcpy(lif->name, lif->eth_dev->data->name, sizeof(lif->name) - 1); 950 951 IONIC_PRINT(DEBUG, "LIF: %s", lif->name); 952 953 ionic_lif_queue_identify(lif); 954 955 if (lif->qtype_info[IONIC_QTYPE_TXQ].version < 1) { 956 IONIC_PRINT(ERR, "FW too old, please upgrade"); 957 return -ENXIO; 958 } 959 960 IONIC_PRINT(DEBUG, "Allocating Lif Info"); 961 962 rte_spinlock_init(&lif->adminq_lock); 963 rte_spinlock_init(&lif->adminq_service_lock); 964 965 lif->kern_dbpage = ionic_bus_map_dbpage(adapter, 0); 966 if (!lif->kern_dbpage) { 967 IONIC_PRINT(ERR, "Cannot map dbpage, aborting"); 968 return -ENOMEM; 969 } 970 971 lif->txqcqs = rte_zmalloc("ionic", sizeof(*lif->txqcqs) * 972 adapter->max_ntxqs_per_lif, 0); 973 974 if (!lif->txqcqs) { 975 IONIC_PRINT(ERR, "Cannot allocate tx queues array"); 976 return -ENOMEM; 977 } 978 979 lif->rxqcqs = rte_zmalloc("ionic", sizeof(*lif->rxqcqs) * 980 adapter->max_nrxqs_per_lif, 0); 981 982 if (!lif->rxqcqs) { 983 IONIC_PRINT(ERR, "Cannot allocate rx queues array"); 984 return -ENOMEM; 985 } 986 987 IONIC_PRINT(DEBUG, "Allocating Notify Queue"); 988 989 err = ionic_notify_qcq_alloc(lif); 990 if (err) { 991 IONIC_PRINT(ERR, "Cannot allocate notify queue"); 992 return err; 993 } 994 995 IONIC_PRINT(DEBUG, "Allocating Admin Queue"); 996 997 err = ionic_admin_qcq_alloc(lif); 998 if (err) { 999 IONIC_PRINT(ERR, "Cannot allocate admin queue"); 1000 return err; 1001 } 1002 1003 IONIC_PRINT(DEBUG, "Allocating Lif Info"); 1004 1005 lif->info_sz = RTE_ALIGN(sizeof(*lif->info), PAGE_SIZE); 1006 1007 lif->info_z = rte_eth_dma_zone_reserve(lif->eth_dev, 1008 "lif_info", 0 /* queue_idx*/, 1009 lif->info_sz, IONIC_ALIGN, socket_id); 1010 if (!lif->info_z) { 1011 IONIC_PRINT(ERR, "Cannot allocate lif info memory"); 1012 return -ENOMEM; 1013 } 1014 1015 lif->info = lif->info_z->addr; 1016 lif->info_pa = lif->info_z->iova; 1017 1018 return 0; 1019 } 1020 1021 void 1022 ionic_lif_free(struct ionic_lif *lif) 1023 { 1024 if (lif->notifyqcq) { 1025 ionic_qcq_free(&lif->notifyqcq->qcq); 1026 lif->notifyqcq = NULL; 1027 } 1028 1029 if (lif->adminqcq) { 1030 ionic_qcq_free(&lif->adminqcq->qcq); 1031 lif->adminqcq = NULL; 1032 } 1033 1034 if (lif->txqcqs) { 1035 rte_free(lif->txqcqs); 1036 lif->txqcqs = NULL; 1037 } 1038 1039 if (lif->rxqcqs) { 1040 rte_free(lif->rxqcqs); 1041 lif->rxqcqs = NULL; 1042 } 1043 1044 if (lif->info) { 1045 rte_memzone_free(lif->info_z); 1046 lif->info = NULL; 1047 } 1048 } 1049 1050 void 1051 ionic_lif_free_queues(struct ionic_lif *lif) 1052 { 1053 uint32_t i; 1054 1055 for (i = 0; i < lif->ntxqcqs; i++) { 1056 ionic_dev_tx_queue_release(lif->eth_dev->data->tx_queues[i]); 1057 lif->eth_dev->data->tx_queues[i] = NULL; 1058 } 1059 for (i = 0; i < lif->nrxqcqs; i++) { 1060 ionic_dev_rx_queue_release(lif->eth_dev->data->rx_queues[i]); 1061 lif->eth_dev->data->rx_queues[i] = NULL; 1062 } 1063 } 1064 1065 int 1066 ionic_lif_rss_config(struct ionic_lif *lif, 1067 const uint16_t types, const uint8_t *key, const uint32_t *indir) 1068 { 1069 struct ionic_adapter *adapter = lif->adapter; 1070 struct ionic_admin_ctx ctx = { 1071 .pending_work = true, 1072 .cmd.lif_setattr = { 1073 .opcode = IONIC_CMD_LIF_SETATTR, 1074 .attr = IONIC_LIF_ATTR_RSS, 1075 .rss.types = rte_cpu_to_le_16(types), 1076 .rss.addr = rte_cpu_to_le_64(lif->rss_ind_tbl_pa), 1077 }, 1078 }; 1079 unsigned int i; 1080 uint16_t tbl_sz = 1081 rte_le_to_cpu_16(adapter->ident.lif.eth.rss_ind_tbl_sz); 1082 1083 IONIC_PRINT_CALL(); 1084 1085 lif->rss_types = types; 1086 1087 if (key) 1088 memcpy(lif->rss_hash_key, key, IONIC_RSS_HASH_KEY_SIZE); 1089 1090 if (indir) 1091 for (i = 0; i < tbl_sz; i++) 1092 lif->rss_ind_tbl[i] = indir[i]; 1093 1094 memcpy(ctx.cmd.lif_setattr.rss.key, lif->rss_hash_key, 1095 IONIC_RSS_HASH_KEY_SIZE); 1096 1097 return ionic_adminq_post_wait(lif, &ctx); 1098 } 1099 1100 static int 1101 ionic_lif_rss_setup(struct ionic_lif *lif) 1102 { 1103 struct ionic_adapter *adapter = lif->adapter; 1104 static const uint8_t toeplitz_symmetric_key[] = { 1105 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 1106 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 1107 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 1108 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 1109 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 0x6D, 0x5A, 1110 }; 1111 uint32_t i; 1112 uint16_t tbl_sz = 1113 rte_le_to_cpu_16(adapter->ident.lif.eth.rss_ind_tbl_sz); 1114 1115 IONIC_PRINT_CALL(); 1116 1117 if (!lif->rss_ind_tbl_z) { 1118 lif->rss_ind_tbl_z = rte_eth_dma_zone_reserve(lif->eth_dev, 1119 "rss_ind_tbl", 0 /* queue_idx */, 1120 sizeof(*lif->rss_ind_tbl) * tbl_sz, 1121 IONIC_ALIGN, rte_socket_id()); 1122 if (!lif->rss_ind_tbl_z) { 1123 IONIC_PRINT(ERR, "OOM"); 1124 return -ENOMEM; 1125 } 1126 1127 lif->rss_ind_tbl = lif->rss_ind_tbl_z->addr; 1128 lif->rss_ind_tbl_pa = lif->rss_ind_tbl_z->iova; 1129 } 1130 1131 if (lif->rss_ind_tbl_nrxqcqs != lif->nrxqcqs) { 1132 lif->rss_ind_tbl_nrxqcqs = lif->nrxqcqs; 1133 1134 /* Fill indirection table with 'default' values */ 1135 for (i = 0; i < tbl_sz; i++) 1136 lif->rss_ind_tbl[i] = i % lif->nrxqcqs; 1137 } 1138 1139 return ionic_lif_rss_config(lif, IONIC_RSS_OFFLOAD_ALL, 1140 toeplitz_symmetric_key, NULL); 1141 } 1142 1143 static void 1144 ionic_lif_rss_teardown(struct ionic_lif *lif) 1145 { 1146 if (!lif->rss_ind_tbl) 1147 return; 1148 1149 if (lif->rss_ind_tbl_z) { 1150 /* Disable RSS on the NIC */ 1151 ionic_lif_rss_config(lif, 0x0, NULL, NULL); 1152 1153 lif->rss_ind_tbl = NULL; 1154 lif->rss_ind_tbl_pa = 0; 1155 rte_memzone_free(lif->rss_ind_tbl_z); 1156 lif->rss_ind_tbl_z = NULL; 1157 } 1158 } 1159 1160 void 1161 ionic_lif_txq_deinit(struct ionic_tx_qcq *txq) 1162 { 1163 txq->flags &= ~IONIC_QCQ_F_INITED; 1164 } 1165 1166 void 1167 ionic_lif_rxq_deinit(struct ionic_rx_qcq *rxq) 1168 { 1169 rxq->flags &= ~IONIC_QCQ_F_INITED; 1170 } 1171 1172 static void 1173 ionic_lif_adminq_deinit(struct ionic_lif *lif) 1174 { 1175 lif->adminqcq->flags &= ~IONIC_QCQ_F_INITED; 1176 } 1177 1178 static void 1179 ionic_lif_notifyq_deinit(struct ionic_lif *lif) 1180 { 1181 struct ionic_notify_qcq *nqcq = lif->notifyqcq; 1182 struct ionic_dev *idev = &lif->adapter->idev; 1183 1184 if (!(nqcq->flags & IONIC_QCQ_F_INITED)) 1185 return; 1186 1187 ionic_intr_mask(idev->intr_ctrl, nqcq->intr.index, 1188 IONIC_INTR_MASK_SET); 1189 1190 nqcq->flags &= ~IONIC_QCQ_F_INITED; 1191 } 1192 1193 /* This acts like ionic_napi */ 1194 int 1195 ionic_qcq_service(struct ionic_qcq *qcq, int budget, ionic_cq_cb cb, 1196 void *cb_arg) 1197 { 1198 struct ionic_cq *cq = &qcq->cq; 1199 uint32_t work_done; 1200 1201 work_done = ionic_cq_service(cq, budget, cb, cb_arg); 1202 1203 return work_done; 1204 } 1205 1206 static void 1207 ionic_link_status_check(struct ionic_lif *lif) 1208 { 1209 struct ionic_adapter *adapter = lif->adapter; 1210 bool link_up; 1211 1212 lif->state &= ~IONIC_LIF_F_LINK_CHECK_NEEDED; 1213 1214 if (!lif->info) 1215 return; 1216 1217 link_up = (lif->info->status.link_status == IONIC_PORT_OPER_STATUS_UP); 1218 1219 if ((link_up && adapter->link_up) || 1220 (!link_up && !adapter->link_up)) 1221 return; 1222 1223 if (link_up) { 1224 adapter->link_speed = 1225 rte_le_to_cpu_32(lif->info->status.link_speed); 1226 IONIC_PRINT(DEBUG, "Link up - %d Gbps", 1227 adapter->link_speed); 1228 } else { 1229 IONIC_PRINT(DEBUG, "Link down"); 1230 } 1231 1232 adapter->link_up = link_up; 1233 ionic_dev_link_update(lif->eth_dev, 0); 1234 } 1235 1236 static void 1237 ionic_lif_handle_fw_down(struct ionic_lif *lif) 1238 { 1239 if (lif->state & IONIC_LIF_F_FW_RESET) 1240 return; 1241 1242 lif->state |= IONIC_LIF_F_FW_RESET; 1243 1244 if (lif->state & IONIC_LIF_F_UP) { 1245 IONIC_PRINT(NOTICE, 1246 "Surprise FW stop, stopping %s\n", lif->name); 1247 ionic_lif_stop(lif); 1248 } 1249 1250 IONIC_PRINT(NOTICE, "FW down, %s stopped", lif->name); 1251 } 1252 1253 static bool 1254 ionic_notifyq_cb(struct ionic_cq *cq, uint16_t cq_desc_index, void *cb_arg) 1255 { 1256 union ionic_notifyq_comp *cq_desc_base = cq->base; 1257 union ionic_notifyq_comp *cq_desc = &cq_desc_base[cq_desc_index]; 1258 struct ionic_lif *lif = cb_arg; 1259 1260 IONIC_PRINT(DEBUG, "Notifyq callback eid = %jd ecode = %d", 1261 cq_desc->event.eid, cq_desc->event.ecode); 1262 1263 /* Have we run out of new completions to process? */ 1264 if (!(cq_desc->event.eid > lif->last_eid)) 1265 return false; 1266 1267 lif->last_eid = cq_desc->event.eid; 1268 1269 switch (cq_desc->event.ecode) { 1270 case IONIC_EVENT_LINK_CHANGE: 1271 IONIC_PRINT(DEBUG, 1272 "Notifyq IONIC_EVENT_LINK_CHANGE %s " 1273 "eid=%jd link_status=%d link_speed=%d", 1274 lif->name, 1275 cq_desc->event.eid, 1276 cq_desc->link_change.link_status, 1277 cq_desc->link_change.link_speed); 1278 1279 lif->state |= IONIC_LIF_F_LINK_CHECK_NEEDED; 1280 break; 1281 1282 case IONIC_EVENT_RESET: 1283 IONIC_PRINT(NOTICE, 1284 "Notifyq IONIC_EVENT_RESET %s " 1285 "eid=%jd, reset_code=%d state=%d", 1286 lif->name, 1287 cq_desc->event.eid, 1288 cq_desc->reset.reset_code, 1289 cq_desc->reset.state); 1290 ionic_lif_handle_fw_down(lif); 1291 break; 1292 1293 default: 1294 IONIC_PRINT(WARNING, "Notifyq bad event ecode=%d eid=%jd", 1295 cq_desc->event.ecode, cq_desc->event.eid); 1296 break; 1297 } 1298 1299 return true; 1300 } 1301 1302 int 1303 ionic_notifyq_handler(struct ionic_lif *lif, int budget) 1304 { 1305 struct ionic_dev *idev = &lif->adapter->idev; 1306 struct ionic_notify_qcq *nqcq = lif->notifyqcq; 1307 uint32_t work_done; 1308 1309 if (!(nqcq->flags & IONIC_QCQ_F_INITED)) { 1310 IONIC_PRINT(DEBUG, "Notifyq not yet initialized"); 1311 return -1; 1312 } 1313 1314 ionic_intr_mask(idev->intr_ctrl, nqcq->intr.index, 1315 IONIC_INTR_MASK_SET); 1316 1317 work_done = ionic_qcq_service(&nqcq->qcq, budget, 1318 ionic_notifyq_cb, lif); 1319 1320 if (lif->state & IONIC_LIF_F_LINK_CHECK_NEEDED) 1321 ionic_link_status_check(lif); 1322 1323 ionic_intr_credits(idev->intr_ctrl, nqcq->intr.index, 1324 work_done, IONIC_INTR_CRED_RESET_COALESCE); 1325 1326 ionic_intr_mask(idev->intr_ctrl, nqcq->intr.index, 1327 IONIC_INTR_MASK_CLEAR); 1328 1329 return 0; 1330 } 1331 1332 static int 1333 ionic_lif_adminq_init(struct ionic_lif *lif) 1334 { 1335 struct ionic_dev *idev = &lif->adapter->idev; 1336 struct ionic_admin_qcq *aqcq = lif->adminqcq; 1337 struct ionic_queue *q = &aqcq->qcq.q; 1338 struct ionic_q_init_comp comp; 1339 int err; 1340 1341 ionic_dev_cmd_adminq_init(idev, &aqcq->qcq); 1342 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 1343 if (err) 1344 return err; 1345 1346 ionic_dev_cmd_comp(idev, &comp); 1347 1348 q->hw_type = comp.hw_type; 1349 q->hw_index = rte_le_to_cpu_32(comp.hw_index); 1350 q->db = ionic_db_map(lif, q); 1351 1352 IONIC_PRINT(DEBUG, "adminq->hw_type %d", q->hw_type); 1353 IONIC_PRINT(DEBUG, "adminq->hw_index %d", q->hw_index); 1354 IONIC_PRINT(DEBUG, "adminq->db %p", q->db); 1355 1356 aqcq->flags |= IONIC_QCQ_F_INITED; 1357 1358 return 0; 1359 } 1360 1361 static int 1362 ionic_lif_notifyq_init(struct ionic_lif *lif) 1363 { 1364 struct ionic_dev *idev = &lif->adapter->idev; 1365 struct ionic_notify_qcq *nqcq = lif->notifyqcq; 1366 struct ionic_queue *q = &nqcq->qcq.q; 1367 int err; 1368 1369 struct ionic_admin_ctx ctx = { 1370 .pending_work = true, 1371 .cmd.q_init = { 1372 .opcode = IONIC_CMD_Q_INIT, 1373 .type = q->type, 1374 .ver = lif->qtype_info[q->type].version, 1375 .index = rte_cpu_to_le_32(q->index), 1376 .intr_index = rte_cpu_to_le_16(nqcq->intr.index), 1377 .flags = rte_cpu_to_le_16(IONIC_QINIT_F_IRQ | 1378 IONIC_QINIT_F_ENA), 1379 .ring_size = rte_log2_u32(q->num_descs), 1380 .ring_base = rte_cpu_to_le_64(q->base_pa), 1381 } 1382 }; 1383 1384 IONIC_PRINT(DEBUG, "notifyq_init.index %d", q->index); 1385 IONIC_PRINT(DEBUG, "notifyq_init.ring_base 0x%" PRIx64 "", q->base_pa); 1386 IONIC_PRINT(DEBUG, "notifyq_init.ring_size %d", 1387 ctx.cmd.q_init.ring_size); 1388 IONIC_PRINT(DEBUG, "notifyq_init.ver %u", ctx.cmd.q_init.ver); 1389 1390 err = ionic_adminq_post_wait(lif, &ctx); 1391 if (err) 1392 return err; 1393 1394 q->hw_type = ctx.comp.q_init.hw_type; 1395 q->hw_index = rte_le_to_cpu_32(ctx.comp.q_init.hw_index); 1396 q->db = NULL; 1397 1398 IONIC_PRINT(DEBUG, "notifyq->hw_type %d", q->hw_type); 1399 IONIC_PRINT(DEBUG, "notifyq->hw_index %d", q->hw_index); 1400 IONIC_PRINT(DEBUG, "notifyq->db %p", q->db); 1401 1402 ionic_intr_mask(idev->intr_ctrl, nqcq->intr.index, 1403 IONIC_INTR_MASK_CLEAR); 1404 1405 nqcq->flags |= IONIC_QCQ_F_INITED; 1406 1407 return 0; 1408 } 1409 1410 int 1411 ionic_lif_set_features(struct ionic_lif *lif) 1412 { 1413 struct ionic_admin_ctx ctx = { 1414 .pending_work = true, 1415 .cmd.lif_setattr = { 1416 .opcode = IONIC_CMD_LIF_SETATTR, 1417 .attr = IONIC_LIF_ATTR_FEATURES, 1418 .features = rte_cpu_to_le_64(lif->features), 1419 }, 1420 }; 1421 int err; 1422 1423 err = ionic_adminq_post_wait(lif, &ctx); 1424 if (err) 1425 return err; 1426 1427 lif->hw_features = rte_le_to_cpu_64(ctx.cmd.lif_setattr.features & 1428 ctx.comp.lif_setattr.features); 1429 1430 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG) 1431 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_TX_TAG"); 1432 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP) 1433 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_RX_STRIP"); 1434 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER) 1435 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_VLAN_RX_FILTER"); 1436 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) 1437 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_HASH"); 1438 if (lif->hw_features & IONIC_ETH_HW_TX_SG) 1439 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TX_SG"); 1440 if (lif->hw_features & IONIC_ETH_HW_RX_SG) 1441 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_SG"); 1442 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM) 1443 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TX_CSUM"); 1444 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM) 1445 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_RX_CSUM"); 1446 if (lif->hw_features & IONIC_ETH_HW_TSO) 1447 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO"); 1448 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6) 1449 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPV6"); 1450 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN) 1451 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_ECN"); 1452 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE) 1453 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_GRE"); 1454 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM) 1455 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_GRE_CSUM"); 1456 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4) 1457 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPXIP4"); 1458 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6) 1459 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_IPXIP6"); 1460 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP) 1461 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_UDP"); 1462 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM) 1463 IONIC_PRINT(DEBUG, "feature IONIC_ETH_HW_TSO_UDP_CSUM"); 1464 1465 return 0; 1466 } 1467 1468 int 1469 ionic_lif_txq_init(struct ionic_tx_qcq *txq) 1470 { 1471 struct ionic_qcq *qcq = &txq->qcq; 1472 struct ionic_queue *q = &qcq->q; 1473 struct ionic_lif *lif = qcq->lif; 1474 struct ionic_cq *cq = &qcq->cq; 1475 struct ionic_admin_ctx ctx = { 1476 .pending_work = true, 1477 .cmd.q_init = { 1478 .opcode = IONIC_CMD_Q_INIT, 1479 .type = q->type, 1480 .ver = lif->qtype_info[q->type].version, 1481 .index = rte_cpu_to_le_32(q->index), 1482 .flags = rte_cpu_to_le_16(IONIC_QINIT_F_SG | 1483 IONIC_QINIT_F_ENA), 1484 .intr_index = rte_cpu_to_le_16(IONIC_INTR_NONE), 1485 .ring_size = rte_log2_u32(q->num_descs), 1486 .ring_base = rte_cpu_to_le_64(q->base_pa), 1487 .cq_ring_base = rte_cpu_to_le_64(cq->base_pa), 1488 .sg_ring_base = rte_cpu_to_le_64(q->sg_base_pa), 1489 }, 1490 }; 1491 int err; 1492 1493 IONIC_PRINT(DEBUG, "txq_init.index %d", q->index); 1494 IONIC_PRINT(DEBUG, "txq_init.ring_base 0x%" PRIx64 "", q->base_pa); 1495 IONIC_PRINT(DEBUG, "txq_init.ring_size %d", 1496 ctx.cmd.q_init.ring_size); 1497 IONIC_PRINT(DEBUG, "txq_init.ver %u", ctx.cmd.q_init.ver); 1498 1499 err = ionic_adminq_post_wait(lif, &ctx); 1500 if (err) 1501 return err; 1502 1503 q->hw_type = ctx.comp.q_init.hw_type; 1504 q->hw_index = rte_le_to_cpu_32(ctx.comp.q_init.hw_index); 1505 q->db = ionic_db_map(lif, q); 1506 1507 IONIC_PRINT(DEBUG, "txq->hw_type %d", q->hw_type); 1508 IONIC_PRINT(DEBUG, "txq->hw_index %d", q->hw_index); 1509 IONIC_PRINT(DEBUG, "txq->db %p", q->db); 1510 1511 txq->flags |= IONIC_QCQ_F_INITED; 1512 1513 return 0; 1514 } 1515 1516 int 1517 ionic_lif_rxq_init(struct ionic_rx_qcq *rxq) 1518 { 1519 struct ionic_qcq *qcq = &rxq->qcq; 1520 struct ionic_queue *q = &qcq->q; 1521 struct ionic_lif *lif = qcq->lif; 1522 struct ionic_cq *cq = &qcq->cq; 1523 struct ionic_admin_ctx ctx = { 1524 .pending_work = true, 1525 .cmd.q_init = { 1526 .opcode = IONIC_CMD_Q_INIT, 1527 .type = q->type, 1528 .ver = lif->qtype_info[q->type].version, 1529 .index = rte_cpu_to_le_32(q->index), 1530 .flags = rte_cpu_to_le_16(IONIC_QINIT_F_SG | 1531 IONIC_QINIT_F_ENA), 1532 .intr_index = rte_cpu_to_le_16(IONIC_INTR_NONE), 1533 .ring_size = rte_log2_u32(q->num_descs), 1534 .ring_base = rte_cpu_to_le_64(q->base_pa), 1535 .cq_ring_base = rte_cpu_to_le_64(cq->base_pa), 1536 .sg_ring_base = rte_cpu_to_le_64(q->sg_base_pa), 1537 }, 1538 }; 1539 int err; 1540 1541 IONIC_PRINT(DEBUG, "rxq_init.index %d", q->index); 1542 IONIC_PRINT(DEBUG, "rxq_init.ring_base 0x%" PRIx64 "", q->base_pa); 1543 IONIC_PRINT(DEBUG, "rxq_init.ring_size %d", 1544 ctx.cmd.q_init.ring_size); 1545 IONIC_PRINT(DEBUG, "rxq_init.ver %u", ctx.cmd.q_init.ver); 1546 1547 err = ionic_adminq_post_wait(lif, &ctx); 1548 if (err) 1549 return err; 1550 1551 q->hw_type = ctx.comp.q_init.hw_type; 1552 q->hw_index = rte_le_to_cpu_32(ctx.comp.q_init.hw_index); 1553 q->db = ionic_db_map(lif, q); 1554 1555 rxq->flags |= IONIC_QCQ_F_INITED; 1556 1557 IONIC_PRINT(DEBUG, "rxq->hw_type %d", q->hw_type); 1558 IONIC_PRINT(DEBUG, "rxq->hw_index %d", q->hw_index); 1559 IONIC_PRINT(DEBUG, "rxq->db %p", q->db); 1560 1561 return 0; 1562 } 1563 1564 static int 1565 ionic_station_set(struct ionic_lif *lif) 1566 { 1567 struct ionic_admin_ctx ctx = { 1568 .pending_work = true, 1569 .cmd.lif_getattr = { 1570 .opcode = IONIC_CMD_LIF_GETATTR, 1571 .attr = IONIC_LIF_ATTR_MAC, 1572 }, 1573 }; 1574 int err; 1575 1576 IONIC_PRINT_CALL(); 1577 1578 err = ionic_adminq_post_wait(lif, &ctx); 1579 if (err) 1580 return err; 1581 1582 memcpy(lif->mac_addr, ctx.comp.lif_getattr.mac, RTE_ETHER_ADDR_LEN); 1583 1584 return 0; 1585 } 1586 1587 static void 1588 ionic_lif_set_name(struct ionic_lif *lif) 1589 { 1590 struct ionic_admin_ctx ctx = { 1591 .pending_work = true, 1592 .cmd.lif_setattr = { 1593 .opcode = IONIC_CMD_LIF_SETATTR, 1594 .attr = IONIC_LIF_ATTR_NAME, 1595 }, 1596 }; 1597 1598 memcpy(ctx.cmd.lif_setattr.name, lif->name, 1599 sizeof(ctx.cmd.lif_setattr.name) - 1); 1600 1601 ionic_adminq_post_wait(lif, &ctx); 1602 } 1603 1604 int 1605 ionic_lif_init(struct ionic_lif *lif) 1606 { 1607 struct ionic_dev *idev = &lif->adapter->idev; 1608 struct ionic_lif_init_comp comp; 1609 int err; 1610 1611 memset(&lif->stats_base, 0, sizeof(lif->stats_base)); 1612 1613 ionic_dev_cmd_lif_init(idev, lif->info_pa); 1614 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 1615 if (err) 1616 return err; 1617 1618 ionic_dev_cmd_comp(idev, &comp); 1619 1620 lif->hw_index = rte_cpu_to_le_16(comp.hw_index); 1621 1622 err = ionic_lif_adminq_init(lif); 1623 if (err) 1624 return err; 1625 1626 err = ionic_lif_notifyq_init(lif); 1627 if (err) 1628 goto err_out_adminq_deinit; 1629 1630 /* 1631 * Configure initial feature set 1632 * This will be updated later by the dev_configure() step 1633 */ 1634 lif->features = IONIC_ETH_HW_RX_HASH | IONIC_ETH_HW_VLAN_RX_FILTER; 1635 1636 err = ionic_lif_set_features(lif); 1637 if (err) 1638 goto err_out_notifyq_deinit; 1639 1640 err = ionic_rx_filters_init(lif); 1641 if (err) 1642 goto err_out_notifyq_deinit; 1643 1644 err = ionic_station_set(lif); 1645 if (err) 1646 goto err_out_rx_filter_deinit; 1647 1648 ionic_lif_set_name(lif); 1649 1650 lif->state |= IONIC_LIF_F_INITED; 1651 1652 return 0; 1653 1654 err_out_rx_filter_deinit: 1655 ionic_rx_filters_deinit(lif); 1656 1657 err_out_notifyq_deinit: 1658 ionic_lif_notifyq_deinit(lif); 1659 1660 err_out_adminq_deinit: 1661 ionic_lif_adminq_deinit(lif); 1662 1663 return err; 1664 } 1665 1666 void 1667 ionic_lif_deinit(struct ionic_lif *lif) 1668 { 1669 if (!(lif->state & IONIC_LIF_F_INITED)) 1670 return; 1671 1672 ionic_rx_filters_deinit(lif); 1673 ionic_lif_rss_teardown(lif); 1674 ionic_lif_notifyq_deinit(lif); 1675 ionic_lif_adminq_deinit(lif); 1676 1677 lif->state &= ~IONIC_LIF_F_INITED; 1678 } 1679 1680 void 1681 ionic_lif_configure_vlan_offload(struct ionic_lif *lif, int mask) 1682 { 1683 struct rte_eth_dev *eth_dev = lif->eth_dev; 1684 struct rte_eth_rxmode *rxmode = ð_dev->data->dev_conf.rxmode; 1685 1686 /* 1687 * IONIC_ETH_HW_VLAN_RX_FILTER cannot be turned off, so 1688 * set DEV_RX_OFFLOAD_VLAN_FILTER and ignore ETH_VLAN_FILTER_MASK 1689 */ 1690 rxmode->offloads |= DEV_RX_OFFLOAD_VLAN_FILTER; 1691 1692 if (mask & ETH_VLAN_STRIP_MASK) { 1693 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 1694 lif->features |= IONIC_ETH_HW_VLAN_RX_STRIP; 1695 else 1696 lif->features &= ~IONIC_ETH_HW_VLAN_RX_STRIP; 1697 } 1698 } 1699 1700 void 1701 ionic_lif_configure(struct ionic_lif *lif) 1702 { 1703 struct rte_eth_rxmode *rxmode = &lif->eth_dev->data->dev_conf.rxmode; 1704 struct rte_eth_txmode *txmode = &lif->eth_dev->data->dev_conf.txmode; 1705 struct ionic_identity *ident = &lif->adapter->ident; 1706 union ionic_lif_config *cfg = &ident->lif.eth.config; 1707 uint32_t ntxqs_per_lif = 1708 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ]); 1709 uint32_t nrxqs_per_lif = 1710 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_RXQ]); 1711 uint32_t nrxqs = lif->eth_dev->data->nb_rx_queues; 1712 uint32_t ntxqs = lif->eth_dev->data->nb_tx_queues; 1713 1714 lif->port_id = lif->eth_dev->data->port_id; 1715 1716 IONIC_PRINT(DEBUG, "Configuring LIF on port %u", 1717 lif->port_id); 1718 1719 if (nrxqs > 0) 1720 nrxqs_per_lif = RTE_MIN(nrxqs_per_lif, nrxqs); 1721 1722 if (ntxqs > 0) 1723 ntxqs_per_lif = RTE_MIN(ntxqs_per_lif, ntxqs); 1724 1725 lif->nrxqcqs = nrxqs_per_lif; 1726 lif->ntxqcqs = ntxqs_per_lif; 1727 1728 /* Update the LIF configuration based on the eth_dev */ 1729 1730 /* 1731 * NB: While it is true that RSS_HASH is always enabled on ionic, 1732 * setting this flag unconditionally causes problems in DTS. 1733 * rxmode->offloads |= DEV_RX_OFFLOAD_RSS_HASH; 1734 */ 1735 1736 /* RX per-port */ 1737 1738 if (rxmode->offloads & DEV_RX_OFFLOAD_IPV4_CKSUM || 1739 rxmode->offloads & DEV_RX_OFFLOAD_UDP_CKSUM || 1740 rxmode->offloads & DEV_RX_OFFLOAD_TCP_CKSUM) 1741 lif->features |= IONIC_ETH_HW_RX_CSUM; 1742 else 1743 lif->features &= ~IONIC_ETH_HW_RX_CSUM; 1744 1745 if (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER) { 1746 lif->features |= IONIC_ETH_HW_RX_SG; 1747 lif->eth_dev->data->scattered_rx = 1; 1748 } else { 1749 lif->features &= ~IONIC_ETH_HW_RX_SG; 1750 lif->eth_dev->data->scattered_rx = 0; 1751 } 1752 1753 /* Covers VLAN_STRIP */ 1754 ionic_lif_configure_vlan_offload(lif, ETH_VLAN_STRIP_MASK); 1755 1756 /* TX per-port */ 1757 1758 if (txmode->offloads & DEV_TX_OFFLOAD_IPV4_CKSUM || 1759 txmode->offloads & DEV_TX_OFFLOAD_UDP_CKSUM || 1760 txmode->offloads & DEV_TX_OFFLOAD_TCP_CKSUM || 1761 txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM || 1762 txmode->offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM) 1763 lif->features |= IONIC_ETH_HW_TX_CSUM; 1764 else 1765 lif->features &= ~IONIC_ETH_HW_TX_CSUM; 1766 1767 if (txmode->offloads & DEV_TX_OFFLOAD_VLAN_INSERT) 1768 lif->features |= IONIC_ETH_HW_VLAN_TX_TAG; 1769 else 1770 lif->features &= ~IONIC_ETH_HW_VLAN_TX_TAG; 1771 1772 if (txmode->offloads & DEV_TX_OFFLOAD_MULTI_SEGS) 1773 lif->features |= IONIC_ETH_HW_TX_SG; 1774 else 1775 lif->features &= ~IONIC_ETH_HW_TX_SG; 1776 1777 if (txmode->offloads & DEV_TX_OFFLOAD_TCP_TSO) { 1778 lif->features |= IONIC_ETH_HW_TSO; 1779 lif->features |= IONIC_ETH_HW_TSO_IPV6; 1780 lif->features |= IONIC_ETH_HW_TSO_ECN; 1781 } else { 1782 lif->features &= ~IONIC_ETH_HW_TSO; 1783 lif->features &= ~IONIC_ETH_HW_TSO_IPV6; 1784 lif->features &= ~IONIC_ETH_HW_TSO_ECN; 1785 } 1786 } 1787 1788 int 1789 ionic_lif_start(struct ionic_lif *lif) 1790 { 1791 uint32_t rx_mode; 1792 uint32_t i; 1793 int err; 1794 1795 err = ionic_lif_rss_setup(lif); 1796 if (err) 1797 return err; 1798 1799 if (!lif->rx_mode) { 1800 IONIC_PRINT(DEBUG, "Setting RX mode on %s", 1801 lif->name); 1802 1803 rx_mode = IONIC_RX_MODE_F_UNICAST; 1804 rx_mode |= IONIC_RX_MODE_F_MULTICAST; 1805 rx_mode |= IONIC_RX_MODE_F_BROADCAST; 1806 1807 ionic_set_rx_mode(lif, rx_mode); 1808 } 1809 1810 IONIC_PRINT(DEBUG, "Starting %u RX queues and %u TX queues " 1811 "on port %u", 1812 lif->nrxqcqs, lif->ntxqcqs, lif->port_id); 1813 1814 for (i = 0; i < lif->nrxqcqs; i++) { 1815 struct ionic_rx_qcq *rxq = lif->rxqcqs[i]; 1816 if (!(rxq->flags & IONIC_QCQ_F_DEFERRED)) { 1817 err = ionic_dev_rx_queue_start(lif->eth_dev, i); 1818 1819 if (err) 1820 return err; 1821 } 1822 } 1823 1824 for (i = 0; i < lif->ntxqcqs; i++) { 1825 struct ionic_tx_qcq *txq = lif->txqcqs[i]; 1826 if (!(txq->flags & IONIC_QCQ_F_DEFERRED)) { 1827 err = ionic_dev_tx_queue_start(lif->eth_dev, i); 1828 1829 if (err) 1830 return err; 1831 } 1832 } 1833 1834 /* Carrier ON here */ 1835 lif->state |= IONIC_LIF_F_UP; 1836 1837 ionic_link_status_check(lif); 1838 1839 return 0; 1840 } 1841 1842 int 1843 ionic_lif_identify(struct ionic_adapter *adapter) 1844 { 1845 struct ionic_dev *idev = &adapter->idev; 1846 struct ionic_identity *ident = &adapter->ident; 1847 union ionic_lif_config *cfg = &ident->lif.eth.config; 1848 uint32_t lif_words = RTE_DIM(ident->lif.words); 1849 uint32_t cmd_words = RTE_DIM(idev->dev_cmd->data); 1850 uint32_t i, nwords; 1851 int err; 1852 1853 ionic_dev_cmd_lif_identify(idev, IONIC_LIF_TYPE_CLASSIC, 1854 IONIC_IDENTITY_VERSION_1); 1855 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 1856 if (err) 1857 return (err); 1858 1859 nwords = RTE_MIN(lif_words, cmd_words); 1860 for (i = 0; i < nwords; i++) 1861 ident->lif.words[i] = ioread32(&idev->dev_cmd->data[i]); 1862 1863 IONIC_PRINT(INFO, "capabilities 0x%" PRIx64 " ", 1864 rte_le_to_cpu_64(ident->lif.capabilities)); 1865 1866 IONIC_PRINT(INFO, "eth.max_ucast_filters 0x%" PRIx32 " ", 1867 rte_le_to_cpu_32(ident->lif.eth.max_ucast_filters)); 1868 IONIC_PRINT(INFO, "eth.max_mcast_filters 0x%" PRIx32 " ", 1869 rte_le_to_cpu_32(ident->lif.eth.max_mcast_filters)); 1870 1871 IONIC_PRINT(INFO, "eth.features 0x%" PRIx64 " ", 1872 rte_le_to_cpu_64(cfg->features)); 1873 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_ADMINQ] 0x%" PRIx32 " ", 1874 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_ADMINQ])); 1875 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_NOTIFYQ] 0x%" PRIx32 " ", 1876 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_NOTIFYQ])); 1877 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_RXQ] 0x%" PRIx32 " ", 1878 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_RXQ])); 1879 IONIC_PRINT(INFO, "eth.queue_count[IONIC_QTYPE_TXQ] 0x%" PRIx32 " ", 1880 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ])); 1881 1882 return 0; 1883 } 1884 1885 int 1886 ionic_lifs_size(struct ionic_adapter *adapter) 1887 { 1888 struct ionic_identity *ident = &adapter->ident; 1889 union ionic_lif_config *cfg = &ident->lif.eth.config; 1890 uint32_t nintrs, dev_nintrs = rte_le_to_cpu_32(ident->dev.nintrs); 1891 1892 adapter->max_ntxqs_per_lif = 1893 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ]); 1894 adapter->max_nrxqs_per_lif = 1895 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_RXQ]); 1896 1897 nintrs = 1 /* notifyq */; 1898 1899 if (nintrs > dev_nintrs) { 1900 IONIC_PRINT(ERR, 1901 "At most %d intr supported, minimum req'd is %u", 1902 dev_nintrs, nintrs); 1903 return -ENOSPC; 1904 } 1905 1906 adapter->nintrs = nintrs; 1907 1908 return 0; 1909 } 1910