1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) 2 * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved. 3 */ 4 5 #include <rte_pci.h> 6 #include <rte_bus_pci.h> 7 #include <rte_ethdev.h> 8 #include <rte_ethdev_driver.h> 9 #include <rte_malloc.h> 10 #include <rte_ethdev_pci.h> 11 12 #include "ionic_logs.h" 13 #include "ionic.h" 14 #include "ionic_dev.h" 15 #include "ionic_mac_api.h" 16 #include "ionic_lif.h" 17 #include "ionic_ethdev.h" 18 #include "ionic_rxtx.h" 19 20 static int eth_ionic_dev_init(struct rte_eth_dev *eth_dev, void *init_params); 21 static int eth_ionic_dev_uninit(struct rte_eth_dev *eth_dev); 22 static int ionic_dev_info_get(struct rte_eth_dev *eth_dev, 23 struct rte_eth_dev_info *dev_info); 24 static int ionic_dev_configure(struct rte_eth_dev *dev); 25 static int ionic_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 26 static int ionic_dev_start(struct rte_eth_dev *dev); 27 static int ionic_dev_stop(struct rte_eth_dev *dev); 28 static int ionic_dev_close(struct rte_eth_dev *dev); 29 static int ionic_dev_set_link_up(struct rte_eth_dev *dev); 30 static int ionic_dev_set_link_down(struct rte_eth_dev *dev); 31 static int ionic_dev_link_update(struct rte_eth_dev *eth_dev, 32 int wait_to_complete); 33 static int ionic_flow_ctrl_get(struct rte_eth_dev *eth_dev, 34 struct rte_eth_fc_conf *fc_conf); 35 static int ionic_flow_ctrl_set(struct rte_eth_dev *eth_dev, 36 struct rte_eth_fc_conf *fc_conf); 37 static int ionic_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask); 38 static int ionic_dev_rss_reta_update(struct rte_eth_dev *eth_dev, 39 struct rte_eth_rss_reta_entry64 *reta_conf, uint16_t reta_size); 40 static int ionic_dev_rss_reta_query(struct rte_eth_dev *eth_dev, 41 struct rte_eth_rss_reta_entry64 *reta_conf, uint16_t reta_size); 42 static int ionic_dev_rss_hash_conf_get(struct rte_eth_dev *eth_dev, 43 struct rte_eth_rss_conf *rss_conf); 44 static int ionic_dev_rss_hash_update(struct rte_eth_dev *eth_dev, 45 struct rte_eth_rss_conf *rss_conf); 46 static int ionic_dev_stats_get(struct rte_eth_dev *eth_dev, 47 struct rte_eth_stats *stats); 48 static int ionic_dev_stats_reset(struct rte_eth_dev *eth_dev); 49 static int ionic_dev_xstats_get(struct rte_eth_dev *dev, 50 struct rte_eth_xstat *xstats, unsigned int n); 51 static int ionic_dev_xstats_get_by_id(struct rte_eth_dev *dev, 52 const uint64_t *ids, uint64_t *values, unsigned int n); 53 static int ionic_dev_xstats_reset(struct rte_eth_dev *dev); 54 static int ionic_dev_xstats_get_names(struct rte_eth_dev *dev, 55 struct rte_eth_xstat_name *xstats_names, unsigned int size); 56 static int ionic_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, 57 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids, 58 unsigned int limit); 59 static int ionic_dev_fw_version_get(struct rte_eth_dev *eth_dev, 60 char *fw_version, size_t fw_size); 61 62 static const struct rte_pci_id pci_id_ionic_map[] = { 63 { RTE_PCI_DEVICE(IONIC_PENSANDO_VENDOR_ID, IONIC_DEV_ID_ETH_PF) }, 64 { RTE_PCI_DEVICE(IONIC_PENSANDO_VENDOR_ID, IONIC_DEV_ID_ETH_VF) }, 65 { RTE_PCI_DEVICE(IONIC_PENSANDO_VENDOR_ID, IONIC_DEV_ID_ETH_MGMT) }, 66 { .vendor_id = 0, /* sentinel */ }, 67 }; 68 69 static const struct rte_eth_desc_lim rx_desc_lim = { 70 .nb_max = IONIC_MAX_RING_DESC, 71 .nb_min = IONIC_MIN_RING_DESC, 72 .nb_align = 1, 73 }; 74 75 static const struct rte_eth_desc_lim tx_desc_lim = { 76 .nb_max = IONIC_MAX_RING_DESC, 77 .nb_min = IONIC_MIN_RING_DESC, 78 .nb_align = 1, 79 .nb_seg_max = IONIC_TX_MAX_SG_ELEMS, 80 .nb_mtu_seg_max = IONIC_TX_MAX_SG_ELEMS, 81 }; 82 83 static const struct eth_dev_ops ionic_eth_dev_ops = { 84 .dev_infos_get = ionic_dev_info_get, 85 .dev_configure = ionic_dev_configure, 86 .mtu_set = ionic_dev_mtu_set, 87 .dev_start = ionic_dev_start, 88 .dev_stop = ionic_dev_stop, 89 .dev_close = ionic_dev_close, 90 .link_update = ionic_dev_link_update, 91 .dev_set_link_up = ionic_dev_set_link_up, 92 .dev_set_link_down = ionic_dev_set_link_down, 93 .mac_addr_add = ionic_dev_add_mac, 94 .mac_addr_remove = ionic_dev_remove_mac, 95 .mac_addr_set = ionic_dev_set_mac, 96 .vlan_filter_set = ionic_dev_vlan_filter_set, 97 .promiscuous_enable = ionic_dev_promiscuous_enable, 98 .promiscuous_disable = ionic_dev_promiscuous_disable, 99 .allmulticast_enable = ionic_dev_allmulticast_enable, 100 .allmulticast_disable = ionic_dev_allmulticast_disable, 101 .flow_ctrl_get = ionic_flow_ctrl_get, 102 .flow_ctrl_set = ionic_flow_ctrl_set, 103 .rxq_info_get = ionic_rxq_info_get, 104 .txq_info_get = ionic_txq_info_get, 105 .rx_queue_setup = ionic_dev_rx_queue_setup, 106 .rx_queue_release = ionic_dev_rx_queue_release, 107 .rx_queue_start = ionic_dev_rx_queue_start, 108 .rx_queue_stop = ionic_dev_rx_queue_stop, 109 .tx_queue_setup = ionic_dev_tx_queue_setup, 110 .tx_queue_release = ionic_dev_tx_queue_release, 111 .tx_queue_start = ionic_dev_tx_queue_start, 112 .tx_queue_stop = ionic_dev_tx_queue_stop, 113 .vlan_offload_set = ionic_vlan_offload_set, 114 .reta_update = ionic_dev_rss_reta_update, 115 .reta_query = ionic_dev_rss_reta_query, 116 .rss_hash_conf_get = ionic_dev_rss_hash_conf_get, 117 .rss_hash_update = ionic_dev_rss_hash_update, 118 .stats_get = ionic_dev_stats_get, 119 .stats_reset = ionic_dev_stats_reset, 120 .xstats_get = ionic_dev_xstats_get, 121 .xstats_get_by_id = ionic_dev_xstats_get_by_id, 122 .xstats_reset = ionic_dev_xstats_reset, 123 .xstats_get_names = ionic_dev_xstats_get_names, 124 .xstats_get_names_by_id = ionic_dev_xstats_get_names_by_id, 125 .fw_version_get = ionic_dev_fw_version_get, 126 }; 127 128 struct rte_ionic_xstats_name_off { 129 char name[RTE_ETH_XSTATS_NAME_SIZE]; 130 unsigned int offset; 131 }; 132 133 static const struct rte_ionic_xstats_name_off rte_ionic_xstats_strings[] = { 134 /* RX */ 135 {"rx_ucast_bytes", offsetof(struct ionic_lif_stats, 136 rx_ucast_bytes)}, 137 {"rx_ucast_packets", offsetof(struct ionic_lif_stats, 138 rx_ucast_packets)}, 139 {"rx_mcast_bytes", offsetof(struct ionic_lif_stats, 140 rx_mcast_bytes)}, 141 {"rx_mcast_packets", offsetof(struct ionic_lif_stats, 142 rx_mcast_packets)}, 143 {"rx_bcast_bytes", offsetof(struct ionic_lif_stats, 144 rx_bcast_bytes)}, 145 {"rx_bcast_packets", offsetof(struct ionic_lif_stats, 146 rx_bcast_packets)}, 147 /* RX drops */ 148 {"rx_ucast_drop_bytes", offsetof(struct ionic_lif_stats, 149 rx_ucast_drop_bytes)}, 150 {"rx_ucast_drop_packets", offsetof(struct ionic_lif_stats, 151 rx_ucast_drop_packets)}, 152 {"rx_mcast_drop_bytes", offsetof(struct ionic_lif_stats, 153 rx_mcast_drop_bytes)}, 154 {"rx_mcast_drop_packets", offsetof(struct ionic_lif_stats, 155 rx_mcast_drop_packets)}, 156 {"rx_bcast_drop_bytes", offsetof(struct ionic_lif_stats, 157 rx_bcast_drop_bytes)}, 158 {"rx_bcast_drop_packets", offsetof(struct ionic_lif_stats, 159 rx_bcast_drop_packets)}, 160 {"rx_dma_error", offsetof(struct ionic_lif_stats, 161 rx_dma_error)}, 162 /* TX */ 163 {"tx_ucast_bytes", offsetof(struct ionic_lif_stats, 164 tx_ucast_bytes)}, 165 {"tx_ucast_packets", offsetof(struct ionic_lif_stats, 166 tx_ucast_packets)}, 167 {"tx_mcast_bytes", offsetof(struct ionic_lif_stats, 168 tx_mcast_bytes)}, 169 {"tx_mcast_packets", offsetof(struct ionic_lif_stats, 170 tx_mcast_packets)}, 171 {"tx_bcast_bytes", offsetof(struct ionic_lif_stats, 172 tx_bcast_bytes)}, 173 {"tx_bcast_packets", offsetof(struct ionic_lif_stats, 174 tx_bcast_packets)}, 175 /* TX drops */ 176 {"tx_ucast_drop_bytes", offsetof(struct ionic_lif_stats, 177 tx_ucast_drop_bytes)}, 178 {"tx_ucast_drop_packets", offsetof(struct ionic_lif_stats, 179 tx_ucast_drop_packets)}, 180 {"tx_mcast_drop_bytes", offsetof(struct ionic_lif_stats, 181 tx_mcast_drop_bytes)}, 182 {"tx_mcast_drop_packets", offsetof(struct ionic_lif_stats, 183 tx_mcast_drop_packets)}, 184 {"tx_bcast_drop_bytes", offsetof(struct ionic_lif_stats, 185 tx_bcast_drop_bytes)}, 186 {"tx_bcast_drop_packets", offsetof(struct ionic_lif_stats, 187 tx_bcast_drop_packets)}, 188 {"tx_dma_error", offsetof(struct ionic_lif_stats, 189 tx_dma_error)}, 190 /* Rx Queue/Ring drops */ 191 {"rx_queue_disabled", offsetof(struct ionic_lif_stats, 192 rx_queue_disabled)}, 193 {"rx_queue_empty", offsetof(struct ionic_lif_stats, 194 rx_queue_empty)}, 195 {"rx_queue_error", offsetof(struct ionic_lif_stats, 196 rx_queue_error)}, 197 {"rx_desc_fetch_error", offsetof(struct ionic_lif_stats, 198 rx_desc_fetch_error)}, 199 {"rx_desc_data_error", offsetof(struct ionic_lif_stats, 200 rx_desc_data_error)}, 201 /* Tx Queue/Ring drops */ 202 {"tx_queue_disabled", offsetof(struct ionic_lif_stats, 203 tx_queue_disabled)}, 204 {"tx_queue_error", offsetof(struct ionic_lif_stats, 205 tx_queue_error)}, 206 {"tx_desc_fetch_error", offsetof(struct ionic_lif_stats, 207 tx_desc_fetch_error)}, 208 {"tx_desc_data_error", offsetof(struct ionic_lif_stats, 209 tx_desc_data_error)}, 210 }; 211 212 #define IONIC_NB_HW_STATS (sizeof(rte_ionic_xstats_strings) / \ 213 sizeof(rte_ionic_xstats_strings[0])) 214 215 static int 216 ionic_dev_fw_version_get(struct rte_eth_dev *eth_dev, 217 char *fw_version, size_t fw_size) 218 { 219 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 220 struct ionic_adapter *adapter = lif->adapter; 221 222 if (fw_version == NULL || fw_size <= 0) 223 return -EINVAL; 224 225 snprintf(fw_version, fw_size, "%s", 226 adapter->fw_version); 227 fw_version[fw_size - 1] = '\0'; 228 229 return 0; 230 } 231 232 /* 233 * Set device link up, enable tx. 234 */ 235 static int 236 ionic_dev_set_link_up(struct rte_eth_dev *eth_dev) 237 { 238 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 239 struct ionic_adapter *adapter = lif->adapter; 240 struct ionic_dev *idev = &adapter->idev; 241 int err; 242 243 IONIC_PRINT_CALL(); 244 245 ionic_dev_cmd_port_state(idev, IONIC_PORT_ADMIN_STATE_UP); 246 247 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 248 if (err) { 249 IONIC_PRINT(WARNING, "Failed to bring port UP"); 250 return err; 251 } 252 253 return 0; 254 } 255 256 /* 257 * Set device link down, disable tx. 258 */ 259 static int 260 ionic_dev_set_link_down(struct rte_eth_dev *eth_dev) 261 { 262 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 263 struct ionic_adapter *adapter = lif->adapter; 264 struct ionic_dev *idev = &adapter->idev; 265 int err; 266 267 IONIC_PRINT_CALL(); 268 269 ionic_dev_cmd_port_state(idev, IONIC_PORT_ADMIN_STATE_DOWN); 270 271 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 272 if (err) { 273 IONIC_PRINT(WARNING, "Failed to bring port DOWN"); 274 return err; 275 } 276 277 return 0; 278 } 279 280 static int 281 ionic_dev_link_update(struct rte_eth_dev *eth_dev, 282 int wait_to_complete __rte_unused) 283 { 284 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 285 struct ionic_adapter *adapter = lif->adapter; 286 struct rte_eth_link link; 287 288 IONIC_PRINT_CALL(); 289 290 /* Initialize */ 291 memset(&link, 0, sizeof(link)); 292 link.link_autoneg = ETH_LINK_AUTONEG; 293 294 if (!adapter->link_up) { 295 /* Interface is down */ 296 link.link_status = ETH_LINK_DOWN; 297 link.link_duplex = ETH_LINK_HALF_DUPLEX; 298 link.link_speed = ETH_SPEED_NUM_NONE; 299 } else { 300 /* Interface is up */ 301 link.link_status = ETH_LINK_UP; 302 link.link_duplex = ETH_LINK_FULL_DUPLEX; 303 switch (adapter->link_speed) { 304 case 10000: 305 link.link_speed = ETH_SPEED_NUM_10G; 306 break; 307 case 25000: 308 link.link_speed = ETH_SPEED_NUM_25G; 309 break; 310 case 40000: 311 link.link_speed = ETH_SPEED_NUM_40G; 312 break; 313 case 50000: 314 link.link_speed = ETH_SPEED_NUM_50G; 315 break; 316 case 100000: 317 link.link_speed = ETH_SPEED_NUM_100G; 318 break; 319 default: 320 link.link_speed = ETH_SPEED_NUM_NONE; 321 break; 322 } 323 } 324 325 return rte_eth_linkstatus_set(eth_dev, &link); 326 } 327 328 /** 329 * Interrupt handler triggered by NIC for handling 330 * specific interrupt. 331 * 332 * @param param 333 * The address of parameter registered before. 334 * 335 * @return 336 * void 337 */ 338 static void 339 ionic_dev_interrupt_handler(void *param) 340 { 341 struct ionic_adapter *adapter = (struct ionic_adapter *)param; 342 uint32_t i; 343 344 IONIC_PRINT(DEBUG, "->"); 345 346 for (i = 0; i < adapter->nlifs; i++) { 347 if (adapter->lifs[i]) 348 ionic_notifyq_handler(adapter->lifs[i], -1); 349 } 350 } 351 352 static int 353 ionic_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) 354 { 355 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 356 uint32_t max_frame_size; 357 int err; 358 359 IONIC_PRINT_CALL(); 360 361 /* 362 * Note: mtu check against IONIC_MIN_MTU, IONIC_MAX_MTU 363 * is done by the the API. 364 */ 365 366 /* 367 * Max frame size is MTU + Ethernet header + VLAN + QinQ 368 * (plus ETHER_CRC_LEN if the adapter is able to keep CRC) 369 */ 370 max_frame_size = mtu + RTE_ETHER_HDR_LEN + 4 + 4; 371 372 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len < max_frame_size) 373 return -EINVAL; 374 375 err = ionic_lif_change_mtu(lif, mtu); 376 if (err) 377 return err; 378 379 return 0; 380 } 381 382 static int 383 ionic_dev_info_get(struct rte_eth_dev *eth_dev, 384 struct rte_eth_dev_info *dev_info) 385 { 386 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 387 struct ionic_adapter *adapter = lif->adapter; 388 struct ionic_identity *ident = &adapter->ident; 389 390 IONIC_PRINT_CALL(); 391 392 dev_info->max_rx_queues = (uint16_t) 393 ident->lif.eth.config.queue_count[IONIC_QTYPE_RXQ]; 394 dev_info->max_tx_queues = (uint16_t) 395 ident->lif.eth.config.queue_count[IONIC_QTYPE_TXQ]; 396 /* Also add ETHER_CRC_LEN if the adapter is able to keep CRC */ 397 dev_info->min_rx_bufsize = IONIC_MIN_MTU + RTE_ETHER_HDR_LEN; 398 dev_info->max_rx_pktlen = IONIC_MAX_MTU + RTE_ETHER_HDR_LEN; 399 dev_info->max_mac_addrs = adapter->max_mac_addrs; 400 dev_info->min_mtu = IONIC_MIN_MTU; 401 dev_info->max_mtu = IONIC_MAX_MTU; 402 403 dev_info->hash_key_size = IONIC_RSS_HASH_KEY_SIZE; 404 dev_info->reta_size = ident->lif.eth.rss_ind_tbl_sz; 405 dev_info->flow_type_rss_offloads = IONIC_ETH_RSS_OFFLOAD_ALL; 406 407 dev_info->speed_capa = 408 ETH_LINK_SPEED_10G | 409 ETH_LINK_SPEED_25G | 410 ETH_LINK_SPEED_40G | 411 ETH_LINK_SPEED_50G | 412 ETH_LINK_SPEED_100G; 413 414 /* 415 * Per-queue capabilities. Actually most of the offloads are enabled 416 * by default on the port and can be used on selected queues (by adding 417 * packet flags at runtime when required) 418 */ 419 420 dev_info->rx_queue_offload_capa = 421 DEV_RX_OFFLOAD_IPV4_CKSUM | 422 DEV_RX_OFFLOAD_UDP_CKSUM | 423 DEV_RX_OFFLOAD_TCP_CKSUM | 424 0; 425 426 dev_info->tx_queue_offload_capa = 427 DEV_TX_OFFLOAD_IPV4_CKSUM | 428 DEV_TX_OFFLOAD_UDP_CKSUM | 429 DEV_TX_OFFLOAD_TCP_CKSUM | 430 DEV_TX_OFFLOAD_VLAN_INSERT | 431 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 432 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM | 433 0; 434 435 /* 436 * Per-port capabilities 437 * See ionic_set_features to request and check supported features 438 */ 439 440 dev_info->rx_offload_capa = dev_info->rx_queue_offload_capa | 441 DEV_RX_OFFLOAD_JUMBO_FRAME | 442 DEV_RX_OFFLOAD_VLAN_FILTER | 443 DEV_RX_OFFLOAD_VLAN_STRIP | 444 DEV_RX_OFFLOAD_SCATTER | 445 0; 446 447 dev_info->tx_offload_capa = dev_info->tx_queue_offload_capa | 448 DEV_TX_OFFLOAD_MULTI_SEGS | 449 DEV_TX_OFFLOAD_TCP_TSO | 450 0; 451 452 dev_info->rx_desc_lim = rx_desc_lim; 453 dev_info->tx_desc_lim = tx_desc_lim; 454 455 /* Driver-preferred Rx/Tx parameters */ 456 dev_info->default_rxportconf.burst_size = 32; 457 dev_info->default_txportconf.burst_size = 32; 458 dev_info->default_rxportconf.nb_queues = 1; 459 dev_info->default_txportconf.nb_queues = 1; 460 dev_info->default_rxportconf.ring_size = IONIC_DEF_TXRX_DESC; 461 dev_info->default_txportconf.ring_size = IONIC_DEF_TXRX_DESC; 462 463 return 0; 464 } 465 466 static int 467 ionic_flow_ctrl_get(struct rte_eth_dev *eth_dev, 468 struct rte_eth_fc_conf *fc_conf) 469 { 470 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 471 struct ionic_adapter *adapter = lif->adapter; 472 struct ionic_dev *idev = &adapter->idev; 473 474 if (idev->port_info) { 475 fc_conf->autoneg = idev->port_info->config.an_enable; 476 477 if (idev->port_info->config.pause_type) 478 fc_conf->mode = RTE_FC_FULL; 479 else 480 fc_conf->mode = RTE_FC_NONE; 481 } 482 483 return 0; 484 } 485 486 static int 487 ionic_flow_ctrl_set(struct rte_eth_dev *eth_dev, 488 struct rte_eth_fc_conf *fc_conf) 489 { 490 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 491 struct ionic_adapter *adapter = lif->adapter; 492 struct ionic_dev *idev = &adapter->idev; 493 uint8_t pause_type = IONIC_PORT_PAUSE_TYPE_NONE; 494 uint8_t an_enable; 495 496 switch (fc_conf->mode) { 497 case RTE_FC_NONE: 498 pause_type = IONIC_PORT_PAUSE_TYPE_NONE; 499 break; 500 case RTE_FC_FULL: 501 pause_type = IONIC_PORT_PAUSE_TYPE_LINK; 502 break; 503 case RTE_FC_RX_PAUSE: 504 case RTE_FC_TX_PAUSE: 505 return -ENOTSUP; 506 } 507 508 an_enable = fc_conf->autoneg; 509 510 ionic_dev_cmd_port_pause(idev, pause_type); 511 ionic_dev_cmd_port_autoneg(idev, an_enable); 512 513 return 0; 514 } 515 516 static int 517 ionic_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask) 518 { 519 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 520 struct rte_eth_rxmode *rxmode; 521 rxmode = ð_dev->data->dev_conf.rxmode; 522 int i; 523 524 if (mask & ETH_VLAN_STRIP_MASK) { 525 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) { 526 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { 527 struct ionic_qcq *rxq = 528 eth_dev->data->rx_queues[i]; 529 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP; 530 } 531 lif->features |= IONIC_ETH_HW_VLAN_RX_STRIP; 532 } else { 533 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { 534 struct ionic_qcq *rxq = 535 eth_dev->data->rx_queues[i]; 536 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP; 537 } 538 lif->features &= ~IONIC_ETH_HW_VLAN_RX_STRIP; 539 } 540 } 541 542 if (mask & ETH_VLAN_FILTER_MASK) { 543 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 544 lif->features |= IONIC_ETH_HW_VLAN_RX_FILTER; 545 else 546 lif->features &= ~IONIC_ETH_HW_VLAN_RX_FILTER; 547 } 548 549 ionic_lif_set_features(lif); 550 551 return 0; 552 } 553 554 static int 555 ionic_dev_rss_reta_update(struct rte_eth_dev *eth_dev, 556 struct rte_eth_rss_reta_entry64 *reta_conf, 557 uint16_t reta_size) 558 { 559 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 560 struct ionic_adapter *adapter = lif->adapter; 561 struct ionic_identity *ident = &adapter->ident; 562 uint32_t i, j, index, num; 563 564 IONIC_PRINT_CALL(); 565 566 if (!lif->rss_ind_tbl) { 567 IONIC_PRINT(ERR, "RSS RETA not initialized, " 568 "can't update the table"); 569 return -EINVAL; 570 } 571 572 if (reta_size != ident->lif.eth.rss_ind_tbl_sz) { 573 IONIC_PRINT(ERR, "The size of hash lookup table configured " 574 "(%d) doesn't match the number hardware can supported " 575 "(%d)", 576 reta_size, ident->lif.eth.rss_ind_tbl_sz); 577 return -EINVAL; 578 } 579 580 num = lif->adapter->ident.lif.eth.rss_ind_tbl_sz / RTE_RETA_GROUP_SIZE; 581 582 for (i = 0; i < num; i++) { 583 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++) { 584 if (reta_conf[i].mask & ((uint64_t)1 << j)) { 585 index = (i * RTE_RETA_GROUP_SIZE) + j; 586 lif->rss_ind_tbl[index] = reta_conf[i].reta[j]; 587 } 588 } 589 } 590 591 return ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL); 592 } 593 594 static int 595 ionic_dev_rss_reta_query(struct rte_eth_dev *eth_dev, 596 struct rte_eth_rss_reta_entry64 *reta_conf, 597 uint16_t reta_size) 598 { 599 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 600 struct ionic_adapter *adapter = lif->adapter; 601 struct ionic_identity *ident = &adapter->ident; 602 int i, num; 603 604 IONIC_PRINT_CALL(); 605 606 if (reta_size != ident->lif.eth.rss_ind_tbl_sz) { 607 IONIC_PRINT(ERR, "The size of hash lookup table configured " 608 "(%d) doesn't match the number hardware can supported " 609 "(%d)", 610 reta_size, ident->lif.eth.rss_ind_tbl_sz); 611 return -EINVAL; 612 } 613 614 if (!lif->rss_ind_tbl) { 615 IONIC_PRINT(ERR, "RSS RETA has not been built yet"); 616 return -EINVAL; 617 } 618 619 num = reta_size / RTE_RETA_GROUP_SIZE; 620 621 for (i = 0; i < num; i++) { 622 memcpy(reta_conf->reta, 623 &lif->rss_ind_tbl[i * RTE_RETA_GROUP_SIZE], 624 RTE_RETA_GROUP_SIZE); 625 reta_conf++; 626 } 627 628 return 0; 629 } 630 631 static int 632 ionic_dev_rss_hash_conf_get(struct rte_eth_dev *eth_dev, 633 struct rte_eth_rss_conf *rss_conf) 634 { 635 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 636 uint64_t rss_hf = 0; 637 638 IONIC_PRINT_CALL(); 639 640 if (!lif->rss_ind_tbl) { 641 IONIC_PRINT(NOTICE, "RSS not enabled"); 642 return 0; 643 } 644 645 /* Get key value (if not null, rss_key is 40-byte) */ 646 if (rss_conf->rss_key != NULL && 647 rss_conf->rss_key_len >= IONIC_RSS_HASH_KEY_SIZE) 648 memcpy(rss_conf->rss_key, lif->rss_hash_key, 649 IONIC_RSS_HASH_KEY_SIZE); 650 651 if (lif->rss_types & IONIC_RSS_TYPE_IPV4) 652 rss_hf |= ETH_RSS_IPV4; 653 if (lif->rss_types & IONIC_RSS_TYPE_IPV4_TCP) 654 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP; 655 if (lif->rss_types & IONIC_RSS_TYPE_IPV4_UDP) 656 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP; 657 if (lif->rss_types & IONIC_RSS_TYPE_IPV6) 658 rss_hf |= ETH_RSS_IPV6; 659 if (lif->rss_types & IONIC_RSS_TYPE_IPV6_TCP) 660 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP; 661 if (lif->rss_types & IONIC_RSS_TYPE_IPV6_UDP) 662 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP; 663 664 rss_conf->rss_hf = rss_hf; 665 666 return 0; 667 } 668 669 static int 670 ionic_dev_rss_hash_update(struct rte_eth_dev *eth_dev, 671 struct rte_eth_rss_conf *rss_conf) 672 { 673 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 674 uint32_t rss_types = 0; 675 uint8_t *key = NULL; 676 677 IONIC_PRINT_CALL(); 678 679 if (rss_conf->rss_key) 680 key = rss_conf->rss_key; 681 682 if ((rss_conf->rss_hf & IONIC_ETH_RSS_OFFLOAD_ALL) == 0) { 683 /* 684 * Can't disable rss through hash flags, 685 * if it is enabled by default during init 686 */ 687 if (lif->rss_ind_tbl) 688 return -EINVAL; 689 } else { 690 /* Can't enable rss if disabled by default during init */ 691 if (!lif->rss_ind_tbl) 692 return -EINVAL; 693 694 if (rss_conf->rss_hf & ETH_RSS_IPV4) 695 rss_types |= IONIC_RSS_TYPE_IPV4; 696 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) 697 rss_types |= IONIC_RSS_TYPE_IPV4_TCP; 698 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) 699 rss_types |= IONIC_RSS_TYPE_IPV4_UDP; 700 if (rss_conf->rss_hf & ETH_RSS_IPV6) 701 rss_types |= IONIC_RSS_TYPE_IPV6; 702 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) 703 rss_types |= IONIC_RSS_TYPE_IPV6_TCP; 704 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) 705 rss_types |= IONIC_RSS_TYPE_IPV6_UDP; 706 707 ionic_lif_rss_config(lif, rss_types, key, NULL); 708 } 709 710 return 0; 711 } 712 713 static int 714 ionic_dev_stats_get(struct rte_eth_dev *eth_dev, 715 struct rte_eth_stats *stats) 716 { 717 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 718 719 ionic_lif_get_stats(lif, stats); 720 721 return 0; 722 } 723 724 static int 725 ionic_dev_stats_reset(struct rte_eth_dev *eth_dev) 726 { 727 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 728 729 IONIC_PRINT_CALL(); 730 731 ionic_lif_reset_stats(lif); 732 733 return 0; 734 } 735 736 static int 737 ionic_dev_xstats_get_names(__rte_unused struct rte_eth_dev *eth_dev, 738 struct rte_eth_xstat_name *xstats_names, 739 __rte_unused unsigned int size) 740 { 741 unsigned int i; 742 743 if (xstats_names != NULL) { 744 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 745 snprintf(xstats_names[i].name, 746 sizeof(xstats_names[i].name), 747 "%s", rte_ionic_xstats_strings[i].name); 748 } 749 } 750 751 return IONIC_NB_HW_STATS; 752 } 753 754 static int 755 ionic_dev_xstats_get_names_by_id(struct rte_eth_dev *eth_dev, 756 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids, 757 unsigned int limit) 758 { 759 struct rte_eth_xstat_name xstats_names_copy[IONIC_NB_HW_STATS]; 760 uint16_t i; 761 762 if (!ids) { 763 if (xstats_names != NULL) { 764 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 765 snprintf(xstats_names[i].name, 766 sizeof(xstats_names[i].name), 767 "%s", rte_ionic_xstats_strings[i].name); 768 } 769 } 770 771 return IONIC_NB_HW_STATS; 772 } 773 774 ionic_dev_xstats_get_names_by_id(eth_dev, xstats_names_copy, NULL, 775 IONIC_NB_HW_STATS); 776 777 for (i = 0; i < limit; i++) { 778 if (ids[i] >= IONIC_NB_HW_STATS) { 779 IONIC_PRINT(ERR, "id value isn't valid"); 780 return -1; 781 } 782 783 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 784 } 785 786 return limit; 787 } 788 789 static int 790 ionic_dev_xstats_get(struct rte_eth_dev *eth_dev, struct rte_eth_xstat *xstats, 791 unsigned int n) 792 { 793 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 794 struct ionic_lif_stats hw_stats; 795 uint16_t i; 796 797 if (n < IONIC_NB_HW_STATS) 798 return IONIC_NB_HW_STATS; 799 800 ionic_lif_get_hw_stats(lif, &hw_stats); 801 802 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 803 xstats[i].value = *(uint64_t *)(((char *)&hw_stats) + 804 rte_ionic_xstats_strings[i].offset); 805 xstats[i].id = i; 806 } 807 808 return IONIC_NB_HW_STATS; 809 } 810 811 static int 812 ionic_dev_xstats_get_by_id(struct rte_eth_dev *eth_dev, const uint64_t *ids, 813 uint64_t *values, unsigned int n) 814 { 815 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 816 struct ionic_lif_stats hw_stats; 817 uint64_t values_copy[IONIC_NB_HW_STATS]; 818 uint16_t i; 819 820 if (!ids) { 821 if (!ids && n < IONIC_NB_HW_STATS) 822 return IONIC_NB_HW_STATS; 823 824 ionic_lif_get_hw_stats(lif, &hw_stats); 825 826 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 827 values[i] = *(uint64_t *)(((char *)&hw_stats) + 828 rte_ionic_xstats_strings[i].offset); 829 } 830 831 return IONIC_NB_HW_STATS; 832 } 833 834 ionic_dev_xstats_get_by_id(eth_dev, NULL, values_copy, 835 IONIC_NB_HW_STATS); 836 837 for (i = 0; i < n; i++) { 838 if (ids[i] >= IONIC_NB_HW_STATS) { 839 IONIC_PRINT(ERR, "id value isn't valid"); 840 return -1; 841 } 842 843 values[i] = values_copy[ids[i]]; 844 } 845 846 return n; 847 } 848 849 static int 850 ionic_dev_xstats_reset(struct rte_eth_dev *eth_dev) 851 { 852 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 853 854 ionic_lif_reset_hw_stats(lif); 855 856 return 0; 857 } 858 859 static int 860 ionic_dev_configure(struct rte_eth_dev *eth_dev) 861 { 862 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 863 int err; 864 865 IONIC_PRINT_CALL(); 866 867 err = ionic_lif_configure(lif); 868 if (err) { 869 IONIC_PRINT(ERR, "Cannot configure LIF: %d", err); 870 return err; 871 } 872 873 return 0; 874 } 875 876 static inline uint32_t 877 ionic_parse_link_speeds(uint16_t link_speeds) 878 { 879 if (link_speeds & ETH_LINK_SPEED_100G) 880 return 100000; 881 else if (link_speeds & ETH_LINK_SPEED_50G) 882 return 50000; 883 else if (link_speeds & ETH_LINK_SPEED_40G) 884 return 40000; 885 else if (link_speeds & ETH_LINK_SPEED_25G) 886 return 25000; 887 else if (link_speeds & ETH_LINK_SPEED_10G) 888 return 10000; 889 else 890 return 0; 891 } 892 893 /* 894 * Configure device link speed and setup link. 895 * It returns 0 on success. 896 */ 897 static int 898 ionic_dev_start(struct rte_eth_dev *eth_dev) 899 { 900 struct rte_eth_conf *dev_conf = ð_dev->data->dev_conf; 901 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 902 struct ionic_adapter *adapter = lif->adapter; 903 struct ionic_dev *idev = &adapter->idev; 904 uint32_t allowed_speeds; 905 int err; 906 907 IONIC_PRINT_CALL(); 908 909 allowed_speeds = 910 ETH_LINK_SPEED_FIXED | 911 ETH_LINK_SPEED_10G | 912 ETH_LINK_SPEED_25G | 913 ETH_LINK_SPEED_40G | 914 ETH_LINK_SPEED_50G | 915 ETH_LINK_SPEED_100G; 916 917 if (dev_conf->link_speeds & ~allowed_speeds) { 918 IONIC_PRINT(ERR, "Invalid link setting"); 919 return -EINVAL; 920 } 921 922 err = ionic_lif_start(lif); 923 if (err) { 924 IONIC_PRINT(ERR, "Cannot start LIF: %d", err); 925 return err; 926 } 927 928 if (eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) { 929 uint32_t speed = ionic_parse_link_speeds(dev_conf->link_speeds); 930 931 if (speed) 932 ionic_dev_cmd_port_speed(idev, speed); 933 } 934 935 ionic_dev_link_update(eth_dev, 0); 936 937 return 0; 938 } 939 940 /* 941 * Stop device: disable rx and tx functions to allow for reconfiguring. 942 */ 943 static int 944 ionic_dev_stop(struct rte_eth_dev *eth_dev) 945 { 946 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 947 int err; 948 949 IONIC_PRINT_CALL(); 950 951 err = ionic_lif_stop(lif); 952 if (err) 953 IONIC_PRINT(ERR, "Cannot stop LIF: %d", err); 954 955 return err; 956 } 957 958 /* 959 * Reset and stop device. 960 */ 961 static int 962 ionic_dev_close(struct rte_eth_dev *eth_dev) 963 { 964 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 965 int err; 966 967 IONIC_PRINT_CALL(); 968 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 969 return 0; 970 971 err = ionic_lif_stop(lif); 972 if (err) { 973 IONIC_PRINT(ERR, "Cannot stop LIF: %d", err); 974 return -1; 975 } 976 977 err = eth_ionic_dev_uninit(eth_dev); 978 if (err) { 979 IONIC_PRINT(ERR, "Cannot destroy LIF: %d", err); 980 return -1; 981 } 982 983 return 0; 984 } 985 986 static int 987 eth_ionic_dev_init(struct rte_eth_dev *eth_dev, void *init_params) 988 { 989 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 990 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 991 struct ionic_adapter *adapter = (struct ionic_adapter *)init_params; 992 int err; 993 994 IONIC_PRINT_CALL(); 995 996 eth_dev->dev_ops = &ionic_eth_dev_ops; 997 eth_dev->rx_pkt_burst = &ionic_recv_pkts; 998 eth_dev->tx_pkt_burst = &ionic_xmit_pkts; 999 eth_dev->tx_pkt_prepare = &ionic_prep_pkts; 1000 1001 /* Multi-process not supported, primary does initialization anyway */ 1002 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1003 return 0; 1004 1005 rte_eth_copy_pci_info(eth_dev, pci_dev); 1006 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 1007 1008 lif->index = adapter->nlifs; 1009 lif->eth_dev = eth_dev; 1010 lif->adapter = adapter; 1011 adapter->lifs[adapter->nlifs] = lif; 1012 1013 IONIC_PRINT(DEBUG, "Up to %u MAC addresses supported", 1014 adapter->max_mac_addrs); 1015 1016 /* Allocate memory for storing MAC addresses */ 1017 eth_dev->data->mac_addrs = rte_zmalloc("ionic", 1018 RTE_ETHER_ADDR_LEN * adapter->max_mac_addrs, 0); 1019 1020 if (eth_dev->data->mac_addrs == NULL) { 1021 IONIC_PRINT(ERR, "Failed to allocate %u bytes needed to " 1022 "store MAC addresses", 1023 RTE_ETHER_ADDR_LEN * adapter->max_mac_addrs); 1024 err = -ENOMEM; 1025 goto err; 1026 } 1027 1028 err = ionic_lif_alloc(lif); 1029 if (err) { 1030 IONIC_PRINT(ERR, "Cannot allocate LIFs: %d, aborting", 1031 err); 1032 goto err; 1033 } 1034 1035 err = ionic_lif_init(lif); 1036 if (err) { 1037 IONIC_PRINT(ERR, "Cannot init LIFs: %d, aborting", err); 1038 goto err_free_lif; 1039 } 1040 1041 /* Copy the MAC address */ 1042 rte_ether_addr_copy((struct rte_ether_addr *)lif->mac_addr, 1043 ð_dev->data->mac_addrs[0]); 1044 1045 IONIC_PRINT(DEBUG, "Port %u initialized", eth_dev->data->port_id); 1046 1047 return 0; 1048 1049 err_free_lif: 1050 ionic_lif_free(lif); 1051 err: 1052 return err; 1053 } 1054 1055 static int 1056 eth_ionic_dev_uninit(struct rte_eth_dev *eth_dev) 1057 { 1058 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 1059 struct ionic_adapter *adapter = lif->adapter; 1060 1061 IONIC_PRINT_CALL(); 1062 1063 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1064 return 0; 1065 1066 adapter->lifs[lif->index] = NULL; 1067 1068 ionic_lif_deinit(lif); 1069 ionic_lif_free(lif); 1070 1071 return 0; 1072 } 1073 1074 static int 1075 ionic_configure_intr(struct ionic_adapter *adapter) 1076 { 1077 struct rte_pci_device *pci_dev = adapter->pci_dev; 1078 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1079 int err; 1080 1081 IONIC_PRINT(DEBUG, "Configuring %u intrs", adapter->nintrs); 1082 1083 if (rte_intr_efd_enable(intr_handle, adapter->nintrs)) { 1084 IONIC_PRINT(ERR, "Fail to create eventfd"); 1085 return -1; 1086 } 1087 1088 if (rte_intr_dp_is_en(intr_handle)) 1089 IONIC_PRINT(DEBUG, 1090 "Packet I/O interrupt on datapath is enabled"); 1091 1092 if (!intr_handle->intr_vec) { 1093 intr_handle->intr_vec = rte_zmalloc("intr_vec", 1094 adapter->nintrs * sizeof(int), 0); 1095 1096 if (!intr_handle->intr_vec) { 1097 IONIC_PRINT(ERR, "Failed to allocate %u vectors", 1098 adapter->nintrs); 1099 return -ENOMEM; 1100 } 1101 } 1102 1103 err = rte_intr_callback_register(intr_handle, 1104 ionic_dev_interrupt_handler, 1105 adapter); 1106 1107 if (err) { 1108 IONIC_PRINT(ERR, 1109 "Failure registering interrupts handler (%d)", 1110 err); 1111 return err; 1112 } 1113 1114 /* enable intr mapping */ 1115 err = rte_intr_enable(intr_handle); 1116 1117 if (err) { 1118 IONIC_PRINT(ERR, "Failure enabling interrupts (%d)", err); 1119 return err; 1120 } 1121 1122 return 0; 1123 } 1124 1125 static void 1126 ionic_unconfigure_intr(struct ionic_adapter *adapter) 1127 { 1128 struct rte_pci_device *pci_dev = adapter->pci_dev; 1129 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1130 1131 rte_intr_disable(intr_handle); 1132 1133 rte_intr_callback_unregister(intr_handle, 1134 ionic_dev_interrupt_handler, 1135 adapter); 1136 } 1137 1138 static int 1139 eth_ionic_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1140 struct rte_pci_device *pci_dev) 1141 { 1142 char name[RTE_ETH_NAME_MAX_LEN]; 1143 struct rte_mem_resource *resource; 1144 struct ionic_adapter *adapter; 1145 struct ionic_hw *hw; 1146 unsigned long i; 1147 int err; 1148 1149 /* Check structs (trigger error at compilation time) */ 1150 ionic_struct_size_checks(); 1151 1152 /* Multi-process not supported */ 1153 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1154 err = -EPERM; 1155 goto err; 1156 } 1157 1158 IONIC_PRINT(DEBUG, "Initializing device %s", 1159 pci_dev->device.name); 1160 1161 adapter = rte_zmalloc("ionic", sizeof(*adapter), 0); 1162 if (!adapter) { 1163 IONIC_PRINT(ERR, "OOM"); 1164 err = -ENOMEM; 1165 goto err; 1166 } 1167 1168 adapter->pci_dev = pci_dev; 1169 hw = &adapter->hw; 1170 1171 hw->device_id = pci_dev->id.device_id; 1172 hw->vendor_id = pci_dev->id.vendor_id; 1173 1174 err = ionic_init_mac(hw); 1175 if (err != 0) { 1176 IONIC_PRINT(ERR, "Mac init failed: %d", err); 1177 err = -EIO; 1178 goto err_free_adapter; 1179 } 1180 1181 adapter->is_mgmt_nic = (pci_dev->id.device_id == IONIC_DEV_ID_ETH_MGMT); 1182 1183 adapter->num_bars = 0; 1184 for (i = 0; i < PCI_MAX_RESOURCE && i < IONIC_BARS_MAX; i++) { 1185 resource = &pci_dev->mem_resource[i]; 1186 if (resource->phys_addr == 0 || resource->len == 0) 1187 continue; 1188 adapter->bars[adapter->num_bars].vaddr = resource->addr; 1189 adapter->bars[adapter->num_bars].bus_addr = resource->phys_addr; 1190 adapter->bars[adapter->num_bars].len = resource->len; 1191 adapter->num_bars++; 1192 } 1193 1194 /* Discover ionic dev resources */ 1195 1196 err = ionic_setup(adapter); 1197 if (err) { 1198 IONIC_PRINT(ERR, "Cannot setup device: %d, aborting", err); 1199 goto err_free_adapter; 1200 } 1201 1202 err = ionic_identify(adapter); 1203 if (err) { 1204 IONIC_PRINT(ERR, "Cannot identify device: %d, aborting", 1205 err); 1206 goto err_free_adapter; 1207 } 1208 1209 err = ionic_init(adapter); 1210 if (err) { 1211 IONIC_PRINT(ERR, "Cannot init device: %d, aborting", err); 1212 goto err_free_adapter; 1213 } 1214 1215 /* Configure the ports */ 1216 err = ionic_port_identify(adapter); 1217 if (err) { 1218 IONIC_PRINT(ERR, "Cannot identify port: %d, aborting", 1219 err); 1220 goto err_free_adapter; 1221 } 1222 1223 err = ionic_port_init(adapter); 1224 if (err) { 1225 IONIC_PRINT(ERR, "Cannot init port: %d, aborting", err); 1226 goto err_free_adapter; 1227 } 1228 1229 /* Configure LIFs */ 1230 err = ionic_lif_identify(adapter); 1231 if (err) { 1232 IONIC_PRINT(ERR, "Cannot identify lif: %d, aborting", err); 1233 goto err_free_adapter; 1234 } 1235 1236 /* Allocate and init LIFs */ 1237 err = ionic_lifs_size(adapter); 1238 if (err) { 1239 IONIC_PRINT(ERR, "Cannot size LIFs: %d, aborting", err); 1240 goto err_free_adapter; 1241 } 1242 1243 adapter->max_mac_addrs = adapter->ident.lif.eth.max_ucast_filters; 1244 1245 adapter->nlifs = 0; 1246 for (i = 0; i < adapter->ident.dev.nlifs; i++) { 1247 snprintf(name, sizeof(name), "net_%s_lif_%lu", 1248 pci_dev->device.name, i); 1249 1250 err = rte_eth_dev_create(&pci_dev->device, name, 1251 sizeof(struct ionic_lif), 1252 NULL, NULL, 1253 eth_ionic_dev_init, adapter); 1254 if (err) { 1255 IONIC_PRINT(ERR, "Cannot create eth device for " 1256 "ionic lif %s", name); 1257 break; 1258 } 1259 1260 adapter->nlifs++; 1261 } 1262 1263 err = ionic_configure_intr(adapter); 1264 1265 if (err) { 1266 IONIC_PRINT(ERR, "Failed to configure interrupts"); 1267 goto err_free_adapter; 1268 } 1269 1270 return 0; 1271 1272 err_free_adapter: 1273 rte_free(adapter); 1274 err: 1275 return err; 1276 } 1277 1278 static int 1279 eth_ionic_pci_remove(struct rte_pci_device *pci_dev __rte_unused) 1280 { 1281 char name[RTE_ETH_NAME_MAX_LEN]; 1282 struct ionic_adapter *adapter = NULL; 1283 struct rte_eth_dev *eth_dev; 1284 struct ionic_lif *lif; 1285 uint32_t i; 1286 1287 /* Adapter lookup is using (the first) eth_dev name */ 1288 snprintf(name, sizeof(name), "net_%s_lif_0", 1289 pci_dev->device.name); 1290 1291 eth_dev = rte_eth_dev_allocated(name); 1292 if (eth_dev) { 1293 lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 1294 adapter = lif->adapter; 1295 } 1296 1297 if (adapter) { 1298 ionic_unconfigure_intr(adapter); 1299 1300 for (i = 0; i < adapter->nlifs; i++) { 1301 lif = adapter->lifs[i]; 1302 rte_eth_dev_destroy(lif->eth_dev, eth_ionic_dev_uninit); 1303 } 1304 1305 rte_free(adapter); 1306 } 1307 1308 return 0; 1309 } 1310 1311 static struct rte_pci_driver rte_ionic_pmd = { 1312 .id_table = pci_id_ionic_map, 1313 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 1314 .probe = eth_ionic_pci_probe, 1315 .remove = eth_ionic_pci_remove, 1316 }; 1317 1318 RTE_PMD_REGISTER_PCI(net_ionic, rte_ionic_pmd); 1319 RTE_PMD_REGISTER_PCI_TABLE(net_ionic, pci_id_ionic_map); 1320 RTE_PMD_REGISTER_KMOD_DEP(net_ionic, "* igb_uio | uio_pci_generic | vfio-pci"); 1321 RTE_LOG_REGISTER(ionic_logtype, pmd.net.ionic, NOTICE); 1322