1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) 2 * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved. 3 */ 4 5 #include <rte_pci.h> 6 #include <rte_bus_pci.h> 7 #include <rte_ethdev.h> 8 #include <rte_ethdev_driver.h> 9 #include <rte_malloc.h> 10 #include <rte_ethdev_pci.h> 11 12 #include "ionic_logs.h" 13 #include "ionic.h" 14 #include "ionic_dev.h" 15 #include "ionic_mac_api.h" 16 #include "ionic_lif.h" 17 #include "ionic_ethdev.h" 18 #include "ionic_rxtx.h" 19 20 static int eth_ionic_dev_init(struct rte_eth_dev *eth_dev, void *init_params); 21 static int eth_ionic_dev_uninit(struct rte_eth_dev *eth_dev); 22 static int ionic_dev_info_get(struct rte_eth_dev *eth_dev, 23 struct rte_eth_dev_info *dev_info); 24 static int ionic_dev_configure(struct rte_eth_dev *dev); 25 static int ionic_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 26 static int ionic_dev_start(struct rte_eth_dev *dev); 27 static int ionic_dev_stop(struct rte_eth_dev *dev); 28 static int ionic_dev_close(struct rte_eth_dev *dev); 29 static int ionic_dev_set_link_up(struct rte_eth_dev *dev); 30 static int ionic_dev_set_link_down(struct rte_eth_dev *dev); 31 static int ionic_flow_ctrl_get(struct rte_eth_dev *eth_dev, 32 struct rte_eth_fc_conf *fc_conf); 33 static int ionic_flow_ctrl_set(struct rte_eth_dev *eth_dev, 34 struct rte_eth_fc_conf *fc_conf); 35 static int ionic_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask); 36 static int ionic_dev_rss_reta_update(struct rte_eth_dev *eth_dev, 37 struct rte_eth_rss_reta_entry64 *reta_conf, uint16_t reta_size); 38 static int ionic_dev_rss_reta_query(struct rte_eth_dev *eth_dev, 39 struct rte_eth_rss_reta_entry64 *reta_conf, uint16_t reta_size); 40 static int ionic_dev_rss_hash_conf_get(struct rte_eth_dev *eth_dev, 41 struct rte_eth_rss_conf *rss_conf); 42 static int ionic_dev_rss_hash_update(struct rte_eth_dev *eth_dev, 43 struct rte_eth_rss_conf *rss_conf); 44 static int ionic_dev_stats_get(struct rte_eth_dev *eth_dev, 45 struct rte_eth_stats *stats); 46 static int ionic_dev_stats_reset(struct rte_eth_dev *eth_dev); 47 static int ionic_dev_xstats_get(struct rte_eth_dev *dev, 48 struct rte_eth_xstat *xstats, unsigned int n); 49 static int ionic_dev_xstats_get_by_id(struct rte_eth_dev *dev, 50 const uint64_t *ids, uint64_t *values, unsigned int n); 51 static int ionic_dev_xstats_reset(struct rte_eth_dev *dev); 52 static int ionic_dev_xstats_get_names(struct rte_eth_dev *dev, 53 struct rte_eth_xstat_name *xstats_names, unsigned int size); 54 static int ionic_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, 55 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids, 56 unsigned int limit); 57 static int ionic_dev_fw_version_get(struct rte_eth_dev *eth_dev, 58 char *fw_version, size_t fw_size); 59 60 static const struct rte_pci_id pci_id_ionic_map[] = { 61 { RTE_PCI_DEVICE(IONIC_PENSANDO_VENDOR_ID, IONIC_DEV_ID_ETH_PF) }, 62 { RTE_PCI_DEVICE(IONIC_PENSANDO_VENDOR_ID, IONIC_DEV_ID_ETH_VF) }, 63 { RTE_PCI_DEVICE(IONIC_PENSANDO_VENDOR_ID, IONIC_DEV_ID_ETH_MGMT) }, 64 { .vendor_id = 0, /* sentinel */ }, 65 }; 66 67 static const struct rte_eth_desc_lim rx_desc_lim = { 68 .nb_max = IONIC_MAX_RING_DESC, 69 .nb_min = IONIC_MIN_RING_DESC, 70 .nb_align = 1, 71 }; 72 73 static const struct rte_eth_desc_lim tx_desc_lim = { 74 .nb_max = IONIC_MAX_RING_DESC, 75 .nb_min = IONIC_MIN_RING_DESC, 76 .nb_align = 1, 77 .nb_seg_max = IONIC_TX_MAX_SG_ELEMS, 78 .nb_mtu_seg_max = IONIC_TX_MAX_SG_ELEMS, 79 }; 80 81 static const struct eth_dev_ops ionic_eth_dev_ops = { 82 .dev_infos_get = ionic_dev_info_get, 83 .dev_configure = ionic_dev_configure, 84 .mtu_set = ionic_dev_mtu_set, 85 .dev_start = ionic_dev_start, 86 .dev_stop = ionic_dev_stop, 87 .dev_close = ionic_dev_close, 88 .link_update = ionic_dev_link_update, 89 .dev_set_link_up = ionic_dev_set_link_up, 90 .dev_set_link_down = ionic_dev_set_link_down, 91 .mac_addr_add = ionic_dev_add_mac, 92 .mac_addr_remove = ionic_dev_remove_mac, 93 .mac_addr_set = ionic_dev_set_mac, 94 .vlan_filter_set = ionic_dev_vlan_filter_set, 95 .promiscuous_enable = ionic_dev_promiscuous_enable, 96 .promiscuous_disable = ionic_dev_promiscuous_disable, 97 .allmulticast_enable = ionic_dev_allmulticast_enable, 98 .allmulticast_disable = ionic_dev_allmulticast_disable, 99 .flow_ctrl_get = ionic_flow_ctrl_get, 100 .flow_ctrl_set = ionic_flow_ctrl_set, 101 .rxq_info_get = ionic_rxq_info_get, 102 .txq_info_get = ionic_txq_info_get, 103 .rx_queue_setup = ionic_dev_rx_queue_setup, 104 .rx_queue_release = ionic_dev_rx_queue_release, 105 .rx_queue_start = ionic_dev_rx_queue_start, 106 .rx_queue_stop = ionic_dev_rx_queue_stop, 107 .tx_queue_setup = ionic_dev_tx_queue_setup, 108 .tx_queue_release = ionic_dev_tx_queue_release, 109 .tx_queue_start = ionic_dev_tx_queue_start, 110 .tx_queue_stop = ionic_dev_tx_queue_stop, 111 .vlan_offload_set = ionic_vlan_offload_set, 112 .reta_update = ionic_dev_rss_reta_update, 113 .reta_query = ionic_dev_rss_reta_query, 114 .rss_hash_conf_get = ionic_dev_rss_hash_conf_get, 115 .rss_hash_update = ionic_dev_rss_hash_update, 116 .stats_get = ionic_dev_stats_get, 117 .stats_reset = ionic_dev_stats_reset, 118 .xstats_get = ionic_dev_xstats_get, 119 .xstats_get_by_id = ionic_dev_xstats_get_by_id, 120 .xstats_reset = ionic_dev_xstats_reset, 121 .xstats_get_names = ionic_dev_xstats_get_names, 122 .xstats_get_names_by_id = ionic_dev_xstats_get_names_by_id, 123 .fw_version_get = ionic_dev_fw_version_get, 124 }; 125 126 struct rte_ionic_xstats_name_off { 127 char name[RTE_ETH_XSTATS_NAME_SIZE]; 128 unsigned int offset; 129 }; 130 131 static const struct rte_ionic_xstats_name_off rte_ionic_xstats_strings[] = { 132 /* RX */ 133 {"rx_ucast_bytes", offsetof(struct ionic_lif_stats, 134 rx_ucast_bytes)}, 135 {"rx_ucast_packets", offsetof(struct ionic_lif_stats, 136 rx_ucast_packets)}, 137 {"rx_mcast_bytes", offsetof(struct ionic_lif_stats, 138 rx_mcast_bytes)}, 139 {"rx_mcast_packets", offsetof(struct ionic_lif_stats, 140 rx_mcast_packets)}, 141 {"rx_bcast_bytes", offsetof(struct ionic_lif_stats, 142 rx_bcast_bytes)}, 143 {"rx_bcast_packets", offsetof(struct ionic_lif_stats, 144 rx_bcast_packets)}, 145 /* RX drops */ 146 {"rx_ucast_drop_bytes", offsetof(struct ionic_lif_stats, 147 rx_ucast_drop_bytes)}, 148 {"rx_ucast_drop_packets", offsetof(struct ionic_lif_stats, 149 rx_ucast_drop_packets)}, 150 {"rx_mcast_drop_bytes", offsetof(struct ionic_lif_stats, 151 rx_mcast_drop_bytes)}, 152 {"rx_mcast_drop_packets", offsetof(struct ionic_lif_stats, 153 rx_mcast_drop_packets)}, 154 {"rx_bcast_drop_bytes", offsetof(struct ionic_lif_stats, 155 rx_bcast_drop_bytes)}, 156 {"rx_bcast_drop_packets", offsetof(struct ionic_lif_stats, 157 rx_bcast_drop_packets)}, 158 {"rx_dma_error", offsetof(struct ionic_lif_stats, 159 rx_dma_error)}, 160 /* TX */ 161 {"tx_ucast_bytes", offsetof(struct ionic_lif_stats, 162 tx_ucast_bytes)}, 163 {"tx_ucast_packets", offsetof(struct ionic_lif_stats, 164 tx_ucast_packets)}, 165 {"tx_mcast_bytes", offsetof(struct ionic_lif_stats, 166 tx_mcast_bytes)}, 167 {"tx_mcast_packets", offsetof(struct ionic_lif_stats, 168 tx_mcast_packets)}, 169 {"tx_bcast_bytes", offsetof(struct ionic_lif_stats, 170 tx_bcast_bytes)}, 171 {"tx_bcast_packets", offsetof(struct ionic_lif_stats, 172 tx_bcast_packets)}, 173 /* TX drops */ 174 {"tx_ucast_drop_bytes", offsetof(struct ionic_lif_stats, 175 tx_ucast_drop_bytes)}, 176 {"tx_ucast_drop_packets", offsetof(struct ionic_lif_stats, 177 tx_ucast_drop_packets)}, 178 {"tx_mcast_drop_bytes", offsetof(struct ionic_lif_stats, 179 tx_mcast_drop_bytes)}, 180 {"tx_mcast_drop_packets", offsetof(struct ionic_lif_stats, 181 tx_mcast_drop_packets)}, 182 {"tx_bcast_drop_bytes", offsetof(struct ionic_lif_stats, 183 tx_bcast_drop_bytes)}, 184 {"tx_bcast_drop_packets", offsetof(struct ionic_lif_stats, 185 tx_bcast_drop_packets)}, 186 {"tx_dma_error", offsetof(struct ionic_lif_stats, 187 tx_dma_error)}, 188 /* Rx Queue/Ring drops */ 189 {"rx_queue_disabled", offsetof(struct ionic_lif_stats, 190 rx_queue_disabled)}, 191 {"rx_queue_empty", offsetof(struct ionic_lif_stats, 192 rx_queue_empty)}, 193 {"rx_queue_error", offsetof(struct ionic_lif_stats, 194 rx_queue_error)}, 195 {"rx_desc_fetch_error", offsetof(struct ionic_lif_stats, 196 rx_desc_fetch_error)}, 197 {"rx_desc_data_error", offsetof(struct ionic_lif_stats, 198 rx_desc_data_error)}, 199 /* Tx Queue/Ring drops */ 200 {"tx_queue_disabled", offsetof(struct ionic_lif_stats, 201 tx_queue_disabled)}, 202 {"tx_queue_error", offsetof(struct ionic_lif_stats, 203 tx_queue_error)}, 204 {"tx_desc_fetch_error", offsetof(struct ionic_lif_stats, 205 tx_desc_fetch_error)}, 206 {"tx_desc_data_error", offsetof(struct ionic_lif_stats, 207 tx_desc_data_error)}, 208 }; 209 210 #define IONIC_NB_HW_STATS (sizeof(rte_ionic_xstats_strings) / \ 211 sizeof(rte_ionic_xstats_strings[0])) 212 213 static int 214 ionic_dev_fw_version_get(struct rte_eth_dev *eth_dev, 215 char *fw_version, size_t fw_size) 216 { 217 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 218 struct ionic_adapter *adapter = lif->adapter; 219 220 if (fw_version == NULL || fw_size <= 0) 221 return -EINVAL; 222 223 snprintf(fw_version, fw_size, "%s", 224 adapter->fw_version); 225 fw_version[fw_size - 1] = '\0'; 226 227 return 0; 228 } 229 230 /* 231 * Set device link up, enable tx. 232 */ 233 static int 234 ionic_dev_set_link_up(struct rte_eth_dev *eth_dev) 235 { 236 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 237 int err; 238 239 IONIC_PRINT_CALL(); 240 241 err = ionic_lif_start(lif); 242 if (err) 243 IONIC_PRINT(ERR, "Could not start lif to set link up"); 244 245 ionic_dev_link_update(lif->eth_dev, 0); 246 247 return err; 248 } 249 250 /* 251 * Set device link down, disable tx. 252 */ 253 static int 254 ionic_dev_set_link_down(struct rte_eth_dev *eth_dev) 255 { 256 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 257 258 IONIC_PRINT_CALL(); 259 260 ionic_lif_stop(lif); 261 262 ionic_dev_link_update(lif->eth_dev, 0); 263 264 return 0; 265 } 266 267 int 268 ionic_dev_link_update(struct rte_eth_dev *eth_dev, 269 int wait_to_complete __rte_unused) 270 { 271 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 272 struct ionic_adapter *adapter = lif->adapter; 273 struct rte_eth_link link; 274 275 IONIC_PRINT_CALL(); 276 277 /* Initialize */ 278 memset(&link, 0, sizeof(link)); 279 link.link_autoneg = ETH_LINK_AUTONEG; 280 281 if (!adapter->link_up || 282 !(lif->state & IONIC_LIF_F_UP)) { 283 /* Interface is down */ 284 link.link_status = ETH_LINK_DOWN; 285 link.link_duplex = ETH_LINK_HALF_DUPLEX; 286 link.link_speed = ETH_SPEED_NUM_NONE; 287 } else { 288 /* Interface is up */ 289 link.link_status = ETH_LINK_UP; 290 link.link_duplex = ETH_LINK_FULL_DUPLEX; 291 switch (adapter->link_speed) { 292 case 10000: 293 link.link_speed = ETH_SPEED_NUM_10G; 294 break; 295 case 25000: 296 link.link_speed = ETH_SPEED_NUM_25G; 297 break; 298 case 40000: 299 link.link_speed = ETH_SPEED_NUM_40G; 300 break; 301 case 50000: 302 link.link_speed = ETH_SPEED_NUM_50G; 303 break; 304 case 100000: 305 link.link_speed = ETH_SPEED_NUM_100G; 306 break; 307 default: 308 link.link_speed = ETH_SPEED_NUM_NONE; 309 break; 310 } 311 } 312 313 return rte_eth_linkstatus_set(eth_dev, &link); 314 } 315 316 /** 317 * Interrupt handler triggered by NIC for handling 318 * specific interrupt. 319 * 320 * @param param 321 * The address of parameter registered before. 322 * 323 * @return 324 * void 325 */ 326 static void 327 ionic_dev_interrupt_handler(void *param) 328 { 329 struct ionic_adapter *adapter = (struct ionic_adapter *)param; 330 331 IONIC_PRINT(DEBUG, "->"); 332 333 if (adapter->lif) 334 ionic_notifyq_handler(adapter->lif, -1); 335 } 336 337 static int 338 ionic_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) 339 { 340 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 341 uint32_t max_frame_size; 342 int err; 343 344 IONIC_PRINT_CALL(); 345 346 /* 347 * Note: mtu check against IONIC_MIN_MTU, IONIC_MAX_MTU 348 * is done by the the API. 349 */ 350 351 /* 352 * Max frame size is MTU + Ethernet header + VLAN + QinQ 353 * (plus ETHER_CRC_LEN if the adapter is able to keep CRC) 354 */ 355 max_frame_size = mtu + RTE_ETHER_HDR_LEN + 4 + 4; 356 357 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len < max_frame_size) 358 return -EINVAL; 359 360 err = ionic_lif_change_mtu(lif, mtu); 361 if (err) 362 return err; 363 364 return 0; 365 } 366 367 static int 368 ionic_dev_info_get(struct rte_eth_dev *eth_dev, 369 struct rte_eth_dev_info *dev_info) 370 { 371 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 372 struct ionic_adapter *adapter = lif->adapter; 373 struct ionic_identity *ident = &adapter->ident; 374 375 IONIC_PRINT_CALL(); 376 377 dev_info->max_rx_queues = (uint16_t) 378 ident->lif.eth.config.queue_count[IONIC_QTYPE_RXQ]; 379 dev_info->max_tx_queues = (uint16_t) 380 ident->lif.eth.config.queue_count[IONIC_QTYPE_TXQ]; 381 /* Also add ETHER_CRC_LEN if the adapter is able to keep CRC */ 382 dev_info->min_rx_bufsize = IONIC_MIN_MTU + RTE_ETHER_HDR_LEN; 383 dev_info->max_rx_pktlen = IONIC_MAX_MTU + RTE_ETHER_HDR_LEN; 384 dev_info->max_mac_addrs = adapter->max_mac_addrs; 385 dev_info->min_mtu = IONIC_MIN_MTU; 386 dev_info->max_mtu = IONIC_MAX_MTU; 387 388 dev_info->hash_key_size = IONIC_RSS_HASH_KEY_SIZE; 389 dev_info->reta_size = ident->lif.eth.rss_ind_tbl_sz; 390 dev_info->flow_type_rss_offloads = IONIC_ETH_RSS_OFFLOAD_ALL; 391 392 dev_info->speed_capa = 393 ETH_LINK_SPEED_10G | 394 ETH_LINK_SPEED_25G | 395 ETH_LINK_SPEED_40G | 396 ETH_LINK_SPEED_50G | 397 ETH_LINK_SPEED_100G; 398 399 /* 400 * Per-queue capabilities. Actually most of the offloads are enabled 401 * by default on the port and can be used on selected queues (by adding 402 * packet flags at runtime when required) 403 */ 404 405 dev_info->rx_queue_offload_capa = 406 DEV_RX_OFFLOAD_IPV4_CKSUM | 407 DEV_RX_OFFLOAD_UDP_CKSUM | 408 DEV_RX_OFFLOAD_TCP_CKSUM | 409 0; 410 411 dev_info->tx_queue_offload_capa = 412 DEV_TX_OFFLOAD_IPV4_CKSUM | 413 DEV_TX_OFFLOAD_UDP_CKSUM | 414 DEV_TX_OFFLOAD_TCP_CKSUM | 415 DEV_TX_OFFLOAD_VLAN_INSERT | 416 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 417 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM | 418 0; 419 420 /* 421 * Per-port capabilities 422 * See ionic_set_features to request and check supported features 423 */ 424 425 dev_info->rx_offload_capa = dev_info->rx_queue_offload_capa | 426 DEV_RX_OFFLOAD_JUMBO_FRAME | 427 DEV_RX_OFFLOAD_VLAN_FILTER | 428 DEV_RX_OFFLOAD_VLAN_STRIP | 429 DEV_RX_OFFLOAD_SCATTER | 430 0; 431 432 dev_info->tx_offload_capa = dev_info->tx_queue_offload_capa | 433 DEV_TX_OFFLOAD_MULTI_SEGS | 434 DEV_TX_OFFLOAD_TCP_TSO | 435 0; 436 437 dev_info->rx_desc_lim = rx_desc_lim; 438 dev_info->tx_desc_lim = tx_desc_lim; 439 440 /* Driver-preferred Rx/Tx parameters */ 441 dev_info->default_rxportconf.burst_size = 32; 442 dev_info->default_txportconf.burst_size = 32; 443 dev_info->default_rxportconf.nb_queues = 1; 444 dev_info->default_txportconf.nb_queues = 1; 445 dev_info->default_rxportconf.ring_size = IONIC_DEF_TXRX_DESC; 446 dev_info->default_txportconf.ring_size = IONIC_DEF_TXRX_DESC; 447 448 return 0; 449 } 450 451 static int 452 ionic_flow_ctrl_get(struct rte_eth_dev *eth_dev, 453 struct rte_eth_fc_conf *fc_conf) 454 { 455 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 456 struct ionic_adapter *adapter = lif->adapter; 457 struct ionic_dev *idev = &adapter->idev; 458 459 if (idev->port_info) { 460 fc_conf->autoneg = idev->port_info->config.an_enable; 461 462 if (idev->port_info->config.pause_type) 463 fc_conf->mode = RTE_FC_FULL; 464 else 465 fc_conf->mode = RTE_FC_NONE; 466 } 467 468 return 0; 469 } 470 471 static int 472 ionic_flow_ctrl_set(struct rte_eth_dev *eth_dev, 473 struct rte_eth_fc_conf *fc_conf) 474 { 475 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 476 struct ionic_adapter *adapter = lif->adapter; 477 struct ionic_dev *idev = &adapter->idev; 478 uint8_t pause_type = IONIC_PORT_PAUSE_TYPE_NONE; 479 uint8_t an_enable; 480 481 switch (fc_conf->mode) { 482 case RTE_FC_NONE: 483 pause_type = IONIC_PORT_PAUSE_TYPE_NONE; 484 break; 485 case RTE_FC_FULL: 486 pause_type = IONIC_PORT_PAUSE_TYPE_LINK; 487 break; 488 case RTE_FC_RX_PAUSE: 489 case RTE_FC_TX_PAUSE: 490 return -ENOTSUP; 491 } 492 493 an_enable = fc_conf->autoneg; 494 495 ionic_dev_cmd_port_pause(idev, pause_type); 496 ionic_dev_cmd_port_autoneg(idev, an_enable); 497 498 return 0; 499 } 500 501 static int 502 ionic_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask) 503 { 504 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 505 struct rte_eth_rxmode *rxmode; 506 rxmode = ð_dev->data->dev_conf.rxmode; 507 int i; 508 509 if (mask & ETH_VLAN_STRIP_MASK) { 510 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) { 511 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { 512 struct ionic_qcq *rxq = 513 eth_dev->data->rx_queues[i]; 514 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP; 515 } 516 lif->features |= IONIC_ETH_HW_VLAN_RX_STRIP; 517 } else { 518 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { 519 struct ionic_qcq *rxq = 520 eth_dev->data->rx_queues[i]; 521 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP; 522 } 523 lif->features &= ~IONIC_ETH_HW_VLAN_RX_STRIP; 524 } 525 } 526 527 if (mask & ETH_VLAN_FILTER_MASK) { 528 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 529 lif->features |= IONIC_ETH_HW_VLAN_RX_FILTER; 530 else 531 lif->features &= ~IONIC_ETH_HW_VLAN_RX_FILTER; 532 } 533 534 ionic_lif_set_features(lif); 535 536 return 0; 537 } 538 539 static int 540 ionic_dev_rss_reta_update(struct rte_eth_dev *eth_dev, 541 struct rte_eth_rss_reta_entry64 *reta_conf, 542 uint16_t reta_size) 543 { 544 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 545 struct ionic_adapter *adapter = lif->adapter; 546 struct ionic_identity *ident = &adapter->ident; 547 uint32_t i, j, index, num; 548 549 IONIC_PRINT_CALL(); 550 551 if (!lif->rss_ind_tbl) { 552 IONIC_PRINT(ERR, "RSS RETA not initialized, " 553 "can't update the table"); 554 return -EINVAL; 555 } 556 557 if (reta_size != ident->lif.eth.rss_ind_tbl_sz) { 558 IONIC_PRINT(ERR, "The size of hash lookup table configured " 559 "(%d) does not match the number hardware can support " 560 "(%d)", 561 reta_size, ident->lif.eth.rss_ind_tbl_sz); 562 return -EINVAL; 563 } 564 565 num = lif->adapter->ident.lif.eth.rss_ind_tbl_sz / RTE_RETA_GROUP_SIZE; 566 567 for (i = 0; i < num; i++) { 568 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++) { 569 if (reta_conf[i].mask & ((uint64_t)1 << j)) { 570 index = (i * RTE_RETA_GROUP_SIZE) + j; 571 lif->rss_ind_tbl[index] = reta_conf[i].reta[j]; 572 } 573 } 574 } 575 576 return ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL); 577 } 578 579 static int 580 ionic_dev_rss_reta_query(struct rte_eth_dev *eth_dev, 581 struct rte_eth_rss_reta_entry64 *reta_conf, 582 uint16_t reta_size) 583 { 584 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 585 struct ionic_adapter *adapter = lif->adapter; 586 struct ionic_identity *ident = &adapter->ident; 587 int i, num; 588 589 IONIC_PRINT_CALL(); 590 591 if (reta_size != ident->lif.eth.rss_ind_tbl_sz) { 592 IONIC_PRINT(ERR, "The size of hash lookup table configured " 593 "(%d) does not match the number hardware can support " 594 "(%d)", 595 reta_size, ident->lif.eth.rss_ind_tbl_sz); 596 return -EINVAL; 597 } 598 599 if (!lif->rss_ind_tbl) { 600 IONIC_PRINT(ERR, "RSS RETA has not been built yet"); 601 return -EINVAL; 602 } 603 604 num = reta_size / RTE_RETA_GROUP_SIZE; 605 606 for (i = 0; i < num; i++) { 607 memcpy(reta_conf->reta, 608 &lif->rss_ind_tbl[i * RTE_RETA_GROUP_SIZE], 609 RTE_RETA_GROUP_SIZE); 610 reta_conf++; 611 } 612 613 return 0; 614 } 615 616 static int 617 ionic_dev_rss_hash_conf_get(struct rte_eth_dev *eth_dev, 618 struct rte_eth_rss_conf *rss_conf) 619 { 620 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 621 uint64_t rss_hf = 0; 622 623 IONIC_PRINT_CALL(); 624 625 if (!lif->rss_ind_tbl) { 626 IONIC_PRINT(NOTICE, "RSS not enabled"); 627 return 0; 628 } 629 630 /* Get key value (if not null, rss_key is 40-byte) */ 631 if (rss_conf->rss_key != NULL && 632 rss_conf->rss_key_len >= IONIC_RSS_HASH_KEY_SIZE) 633 memcpy(rss_conf->rss_key, lif->rss_hash_key, 634 IONIC_RSS_HASH_KEY_SIZE); 635 636 if (lif->rss_types & IONIC_RSS_TYPE_IPV4) 637 rss_hf |= ETH_RSS_IPV4; 638 if (lif->rss_types & IONIC_RSS_TYPE_IPV4_TCP) 639 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP; 640 if (lif->rss_types & IONIC_RSS_TYPE_IPV4_UDP) 641 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP; 642 if (lif->rss_types & IONIC_RSS_TYPE_IPV6) 643 rss_hf |= ETH_RSS_IPV6; 644 if (lif->rss_types & IONIC_RSS_TYPE_IPV6_TCP) 645 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP; 646 if (lif->rss_types & IONIC_RSS_TYPE_IPV6_UDP) 647 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP; 648 649 rss_conf->rss_hf = rss_hf; 650 651 return 0; 652 } 653 654 static int 655 ionic_dev_rss_hash_update(struct rte_eth_dev *eth_dev, 656 struct rte_eth_rss_conf *rss_conf) 657 { 658 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 659 uint32_t rss_types = 0; 660 uint8_t *key = NULL; 661 662 IONIC_PRINT_CALL(); 663 664 if (rss_conf->rss_key) 665 key = rss_conf->rss_key; 666 667 if ((rss_conf->rss_hf & IONIC_ETH_RSS_OFFLOAD_ALL) == 0) { 668 /* 669 * Can't disable rss through hash flags, 670 * if it is enabled by default during init 671 */ 672 if (lif->rss_ind_tbl) 673 return -EINVAL; 674 } else { 675 /* Can't enable rss if disabled by default during init */ 676 if (!lif->rss_ind_tbl) 677 return -EINVAL; 678 679 if (rss_conf->rss_hf & ETH_RSS_IPV4) 680 rss_types |= IONIC_RSS_TYPE_IPV4; 681 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) 682 rss_types |= IONIC_RSS_TYPE_IPV4_TCP; 683 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) 684 rss_types |= IONIC_RSS_TYPE_IPV4_UDP; 685 if (rss_conf->rss_hf & ETH_RSS_IPV6) 686 rss_types |= IONIC_RSS_TYPE_IPV6; 687 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) 688 rss_types |= IONIC_RSS_TYPE_IPV6_TCP; 689 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) 690 rss_types |= IONIC_RSS_TYPE_IPV6_UDP; 691 692 ionic_lif_rss_config(lif, rss_types, key, NULL); 693 } 694 695 return 0; 696 } 697 698 static int 699 ionic_dev_stats_get(struct rte_eth_dev *eth_dev, 700 struct rte_eth_stats *stats) 701 { 702 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 703 704 ionic_lif_get_stats(lif, stats); 705 706 return 0; 707 } 708 709 static int 710 ionic_dev_stats_reset(struct rte_eth_dev *eth_dev) 711 { 712 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 713 714 IONIC_PRINT_CALL(); 715 716 ionic_lif_reset_stats(lif); 717 718 return 0; 719 } 720 721 static int 722 ionic_dev_xstats_get_names(__rte_unused struct rte_eth_dev *eth_dev, 723 struct rte_eth_xstat_name *xstats_names, 724 __rte_unused unsigned int size) 725 { 726 unsigned int i; 727 728 if (xstats_names != NULL) { 729 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 730 snprintf(xstats_names[i].name, 731 sizeof(xstats_names[i].name), 732 "%s", rte_ionic_xstats_strings[i].name); 733 } 734 } 735 736 return IONIC_NB_HW_STATS; 737 } 738 739 static int 740 ionic_dev_xstats_get_names_by_id(struct rte_eth_dev *eth_dev, 741 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids, 742 unsigned int limit) 743 { 744 struct rte_eth_xstat_name xstats_names_copy[IONIC_NB_HW_STATS]; 745 uint16_t i; 746 747 if (!ids) { 748 if (xstats_names != NULL) { 749 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 750 snprintf(xstats_names[i].name, 751 sizeof(xstats_names[i].name), 752 "%s", rte_ionic_xstats_strings[i].name); 753 } 754 } 755 756 return IONIC_NB_HW_STATS; 757 } 758 759 ionic_dev_xstats_get_names_by_id(eth_dev, xstats_names_copy, NULL, 760 IONIC_NB_HW_STATS); 761 762 for (i = 0; i < limit; i++) { 763 if (ids[i] >= IONIC_NB_HW_STATS) { 764 IONIC_PRINT(ERR, "id value isn't valid"); 765 return -1; 766 } 767 768 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 769 } 770 771 return limit; 772 } 773 774 static int 775 ionic_dev_xstats_get(struct rte_eth_dev *eth_dev, struct rte_eth_xstat *xstats, 776 unsigned int n) 777 { 778 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 779 struct ionic_lif_stats hw_stats; 780 uint16_t i; 781 782 if (n < IONIC_NB_HW_STATS) 783 return IONIC_NB_HW_STATS; 784 785 ionic_lif_get_hw_stats(lif, &hw_stats); 786 787 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 788 xstats[i].value = *(uint64_t *)(((char *)&hw_stats) + 789 rte_ionic_xstats_strings[i].offset); 790 xstats[i].id = i; 791 } 792 793 return IONIC_NB_HW_STATS; 794 } 795 796 static int 797 ionic_dev_xstats_get_by_id(struct rte_eth_dev *eth_dev, const uint64_t *ids, 798 uint64_t *values, unsigned int n) 799 { 800 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 801 struct ionic_lif_stats hw_stats; 802 uint64_t values_copy[IONIC_NB_HW_STATS]; 803 uint16_t i; 804 805 if (!ids) { 806 if (!ids && n < IONIC_NB_HW_STATS) 807 return IONIC_NB_HW_STATS; 808 809 ionic_lif_get_hw_stats(lif, &hw_stats); 810 811 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 812 values[i] = *(uint64_t *)(((char *)&hw_stats) + 813 rte_ionic_xstats_strings[i].offset); 814 } 815 816 return IONIC_NB_HW_STATS; 817 } 818 819 ionic_dev_xstats_get_by_id(eth_dev, NULL, values_copy, 820 IONIC_NB_HW_STATS); 821 822 for (i = 0; i < n; i++) { 823 if (ids[i] >= IONIC_NB_HW_STATS) { 824 IONIC_PRINT(ERR, "id value isn't valid"); 825 return -1; 826 } 827 828 values[i] = values_copy[ids[i]]; 829 } 830 831 return n; 832 } 833 834 static int 835 ionic_dev_xstats_reset(struct rte_eth_dev *eth_dev) 836 { 837 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 838 839 ionic_lif_reset_hw_stats(lif); 840 841 return 0; 842 } 843 844 static int 845 ionic_dev_configure(struct rte_eth_dev *eth_dev) 846 { 847 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 848 int err; 849 850 IONIC_PRINT_CALL(); 851 852 err = ionic_lif_configure(lif); 853 if (err) { 854 IONIC_PRINT(ERR, "Cannot configure LIF: %d", err); 855 return err; 856 } 857 858 return 0; 859 } 860 861 static inline uint32_t 862 ionic_parse_link_speeds(uint16_t link_speeds) 863 { 864 if (link_speeds & ETH_LINK_SPEED_100G) 865 return 100000; 866 else if (link_speeds & ETH_LINK_SPEED_50G) 867 return 50000; 868 else if (link_speeds & ETH_LINK_SPEED_40G) 869 return 40000; 870 else if (link_speeds & ETH_LINK_SPEED_25G) 871 return 25000; 872 else if (link_speeds & ETH_LINK_SPEED_10G) 873 return 10000; 874 else 875 return 0; 876 } 877 878 /* 879 * Configure device link speed and setup link. 880 * It returns 0 on success. 881 */ 882 static int 883 ionic_dev_start(struct rte_eth_dev *eth_dev) 884 { 885 struct rte_eth_conf *dev_conf = ð_dev->data->dev_conf; 886 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 887 struct ionic_adapter *adapter = lif->adapter; 888 struct ionic_dev *idev = &adapter->idev; 889 uint32_t allowed_speeds; 890 int err; 891 892 IONIC_PRINT_CALL(); 893 894 allowed_speeds = 895 ETH_LINK_SPEED_FIXED | 896 ETH_LINK_SPEED_10G | 897 ETH_LINK_SPEED_25G | 898 ETH_LINK_SPEED_40G | 899 ETH_LINK_SPEED_50G | 900 ETH_LINK_SPEED_100G; 901 902 if (dev_conf->link_speeds & ~allowed_speeds) { 903 IONIC_PRINT(ERR, "Invalid link setting"); 904 return -EINVAL; 905 } 906 907 if (dev_conf->lpbk_mode) 908 IONIC_PRINT(WARNING, "Loopback mode not supported"); 909 910 err = ionic_lif_start(lif); 911 if (err) { 912 IONIC_PRINT(ERR, "Cannot start LIF: %d", err); 913 return err; 914 } 915 916 if (eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) { 917 uint32_t speed = ionic_parse_link_speeds(dev_conf->link_speeds); 918 919 if (speed) 920 ionic_dev_cmd_port_speed(idev, speed); 921 } 922 923 ionic_dev_link_update(eth_dev, 0); 924 925 return 0; 926 } 927 928 /* 929 * Stop device: disable rx and tx functions to allow for reconfiguring. 930 */ 931 static int 932 ionic_dev_stop(struct rte_eth_dev *eth_dev) 933 { 934 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 935 936 IONIC_PRINT_CALL(); 937 938 ionic_lif_stop(lif); 939 940 return 0; 941 } 942 943 static void ionic_unconfigure_intr(struct ionic_adapter *adapter); 944 945 /* 946 * Reset and stop device. 947 */ 948 static int 949 ionic_dev_close(struct rte_eth_dev *eth_dev) 950 { 951 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 952 struct ionic_adapter *adapter = lif->adapter; 953 954 IONIC_PRINT_CALL(); 955 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 956 return 0; 957 958 ionic_lif_stop(lif); 959 960 ionic_lif_free_queues(lif); 961 962 IONIC_PRINT(NOTICE, "Removing device %s", eth_dev->device->name); 963 ionic_unconfigure_intr(adapter); 964 965 rte_eth_dev_destroy(eth_dev, eth_ionic_dev_uninit); 966 967 ionic_port_reset(adapter); 968 ionic_reset(adapter); 969 970 rte_free(adapter); 971 972 return 0; 973 } 974 975 static int 976 eth_ionic_dev_init(struct rte_eth_dev *eth_dev, void *init_params) 977 { 978 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 979 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 980 struct ionic_adapter *adapter = (struct ionic_adapter *)init_params; 981 int err; 982 983 IONIC_PRINT_CALL(); 984 985 eth_dev->dev_ops = &ionic_eth_dev_ops; 986 eth_dev->rx_pkt_burst = &ionic_recv_pkts; 987 eth_dev->tx_pkt_burst = &ionic_xmit_pkts; 988 eth_dev->tx_pkt_prepare = &ionic_prep_pkts; 989 990 /* Multi-process not supported, primary does initialization anyway */ 991 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 992 return 0; 993 994 rte_eth_copy_pci_info(eth_dev, pci_dev); 995 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 996 997 lif->eth_dev = eth_dev; 998 lif->adapter = adapter; 999 adapter->lif = lif; 1000 1001 IONIC_PRINT(DEBUG, "Up to %u MAC addresses supported", 1002 adapter->max_mac_addrs); 1003 1004 /* Allocate memory for storing MAC addresses */ 1005 eth_dev->data->mac_addrs = rte_zmalloc("ionic", 1006 RTE_ETHER_ADDR_LEN * adapter->max_mac_addrs, 0); 1007 1008 if (eth_dev->data->mac_addrs == NULL) { 1009 IONIC_PRINT(ERR, "Failed to allocate %u bytes needed to " 1010 "store MAC addresses", 1011 RTE_ETHER_ADDR_LEN * adapter->max_mac_addrs); 1012 err = -ENOMEM; 1013 goto err; 1014 } 1015 1016 err = ionic_lif_alloc(lif); 1017 if (err) { 1018 IONIC_PRINT(ERR, "Cannot allocate LIFs: %d, aborting", 1019 err); 1020 goto err; 1021 } 1022 1023 err = ionic_lif_init(lif); 1024 if (err) { 1025 IONIC_PRINT(ERR, "Cannot init LIFs: %d, aborting", err); 1026 goto err_free_lif; 1027 } 1028 1029 /* Copy the MAC address */ 1030 rte_ether_addr_copy((struct rte_ether_addr *)lif->mac_addr, 1031 ð_dev->data->mac_addrs[0]); 1032 1033 IONIC_PRINT(DEBUG, "Port %u initialized", eth_dev->data->port_id); 1034 1035 return 0; 1036 1037 err_free_lif: 1038 ionic_lif_free(lif); 1039 err: 1040 return err; 1041 } 1042 1043 static int 1044 eth_ionic_dev_uninit(struct rte_eth_dev *eth_dev) 1045 { 1046 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 1047 struct ionic_adapter *adapter = lif->adapter; 1048 1049 IONIC_PRINT_CALL(); 1050 1051 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1052 return 0; 1053 1054 adapter->lif = NULL; 1055 1056 ionic_lif_deinit(lif); 1057 ionic_lif_free(lif); 1058 1059 if (!(lif->state & IONIC_LIF_F_FW_RESET)) 1060 ionic_lif_reset(lif); 1061 1062 return 0; 1063 } 1064 1065 static int 1066 ionic_configure_intr(struct ionic_adapter *adapter) 1067 { 1068 struct rte_pci_device *pci_dev = adapter->pci_dev; 1069 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1070 int err; 1071 1072 IONIC_PRINT(DEBUG, "Configuring %u intrs", adapter->nintrs); 1073 1074 if (rte_intr_efd_enable(intr_handle, adapter->nintrs)) { 1075 IONIC_PRINT(ERR, "Fail to create eventfd"); 1076 return -1; 1077 } 1078 1079 if (rte_intr_dp_is_en(intr_handle)) 1080 IONIC_PRINT(DEBUG, 1081 "Packet I/O interrupt on datapath is enabled"); 1082 1083 if (!intr_handle->intr_vec) { 1084 intr_handle->intr_vec = rte_zmalloc("intr_vec", 1085 adapter->nintrs * sizeof(int), 0); 1086 1087 if (!intr_handle->intr_vec) { 1088 IONIC_PRINT(ERR, "Failed to allocate %u vectors", 1089 adapter->nintrs); 1090 return -ENOMEM; 1091 } 1092 } 1093 1094 err = rte_intr_callback_register(intr_handle, 1095 ionic_dev_interrupt_handler, 1096 adapter); 1097 1098 if (err) { 1099 IONIC_PRINT(ERR, 1100 "Failure registering interrupts handler (%d)", 1101 err); 1102 return err; 1103 } 1104 1105 /* enable intr mapping */ 1106 err = rte_intr_enable(intr_handle); 1107 1108 if (err) { 1109 IONIC_PRINT(ERR, "Failure enabling interrupts (%d)", err); 1110 return err; 1111 } 1112 1113 return 0; 1114 } 1115 1116 static void 1117 ionic_unconfigure_intr(struct ionic_adapter *adapter) 1118 { 1119 struct rte_pci_device *pci_dev = adapter->pci_dev; 1120 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1121 1122 rte_intr_disable(intr_handle); 1123 1124 rte_intr_callback_unregister(intr_handle, 1125 ionic_dev_interrupt_handler, 1126 adapter); 1127 } 1128 1129 static int 1130 eth_ionic_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1131 struct rte_pci_device *pci_dev) 1132 { 1133 char name[RTE_ETH_NAME_MAX_LEN]; 1134 struct rte_mem_resource *resource; 1135 struct ionic_adapter *adapter; 1136 struct ionic_hw *hw; 1137 unsigned long i; 1138 int err; 1139 1140 /* Check structs (trigger error at compilation time) */ 1141 ionic_struct_size_checks(); 1142 1143 /* Multi-process not supported */ 1144 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1145 err = -EPERM; 1146 goto err; 1147 } 1148 1149 IONIC_PRINT(DEBUG, "Initializing device %s", 1150 pci_dev->device.name); 1151 1152 adapter = rte_zmalloc("ionic", sizeof(*adapter), 0); 1153 if (!adapter) { 1154 IONIC_PRINT(ERR, "OOM"); 1155 err = -ENOMEM; 1156 goto err; 1157 } 1158 1159 adapter->pci_dev = pci_dev; 1160 hw = &adapter->hw; 1161 1162 hw->device_id = pci_dev->id.device_id; 1163 hw->vendor_id = pci_dev->id.vendor_id; 1164 1165 err = ionic_init_mac(hw); 1166 if (err != 0) { 1167 IONIC_PRINT(ERR, "Mac init failed: %d", err); 1168 err = -EIO; 1169 goto err_free_adapter; 1170 } 1171 1172 adapter->num_bars = 0; 1173 for (i = 0; i < PCI_MAX_RESOURCE && i < IONIC_BARS_MAX; i++) { 1174 resource = &pci_dev->mem_resource[i]; 1175 if (resource->phys_addr == 0 || resource->len == 0) 1176 continue; 1177 adapter->bars[adapter->num_bars].vaddr = resource->addr; 1178 adapter->bars[adapter->num_bars].bus_addr = resource->phys_addr; 1179 adapter->bars[adapter->num_bars].len = resource->len; 1180 adapter->num_bars++; 1181 } 1182 1183 /* Discover ionic dev resources */ 1184 1185 err = ionic_setup(adapter); 1186 if (err) { 1187 IONIC_PRINT(ERR, "Cannot setup device: %d, aborting", err); 1188 goto err_free_adapter; 1189 } 1190 1191 err = ionic_identify(adapter); 1192 if (err) { 1193 IONIC_PRINT(ERR, "Cannot identify device: %d, aborting", 1194 err); 1195 goto err_free_adapter; 1196 } 1197 1198 err = ionic_init(adapter); 1199 if (err) { 1200 IONIC_PRINT(ERR, "Cannot init device: %d, aborting", err); 1201 goto err_free_adapter; 1202 } 1203 1204 /* Configure the ports */ 1205 err = ionic_port_identify(adapter); 1206 if (err) { 1207 IONIC_PRINT(ERR, "Cannot identify port: %d, aborting", 1208 err); 1209 goto err_free_adapter; 1210 } 1211 1212 err = ionic_port_init(adapter); 1213 if (err) { 1214 IONIC_PRINT(ERR, "Cannot init port: %d, aborting", err); 1215 goto err_free_adapter; 1216 } 1217 1218 /* Configure LIFs */ 1219 err = ionic_lif_identify(adapter); 1220 if (err) { 1221 IONIC_PRINT(ERR, "Cannot identify lif: %d, aborting", err); 1222 goto err_free_adapter; 1223 } 1224 1225 /* Allocate and init LIFs */ 1226 err = ionic_lifs_size(adapter); 1227 if (err) { 1228 IONIC_PRINT(ERR, "Cannot size LIFs: %d, aborting", err); 1229 goto err_free_adapter; 1230 } 1231 1232 adapter->max_mac_addrs = adapter->ident.lif.eth.max_ucast_filters; 1233 1234 if (adapter->ident.dev.nlifs != 1) { 1235 IONIC_PRINT(ERR, "Unexpected request for %d LIFs", 1236 adapter->ident.dev.nlifs); 1237 goto err_free_adapter; 1238 } 1239 1240 snprintf(name, sizeof(name), "%s_lif", pci_dev->device.name); 1241 err = rte_eth_dev_create(&pci_dev->device, 1242 name, sizeof(struct ionic_lif), 1243 NULL, NULL, eth_ionic_dev_init, adapter); 1244 if (err) { 1245 IONIC_PRINT(ERR, "Cannot create eth device for %s", name); 1246 goto err_free_adapter; 1247 } 1248 1249 err = ionic_configure_intr(adapter); 1250 1251 if (err) { 1252 IONIC_PRINT(ERR, "Failed to configure interrupts"); 1253 goto err_free_adapter; 1254 } 1255 1256 return 0; 1257 1258 err_free_adapter: 1259 rte_free(adapter); 1260 err: 1261 return err; 1262 } 1263 1264 static int 1265 eth_ionic_pci_remove(struct rte_pci_device *pci_dev) 1266 { 1267 char name[RTE_ETH_NAME_MAX_LEN]; 1268 struct rte_eth_dev *eth_dev; 1269 1270 /* Adapter lookup is using the eth_dev name */ 1271 snprintf(name, sizeof(name), "%s_lif", pci_dev->device.name); 1272 1273 eth_dev = rte_eth_dev_allocated(name); 1274 if (eth_dev) 1275 ionic_dev_close(eth_dev); 1276 else 1277 IONIC_PRINT(DEBUG, "Cannot find device %s", 1278 pci_dev->device.name); 1279 1280 return 0; 1281 } 1282 1283 static struct rte_pci_driver rte_ionic_pmd = { 1284 .id_table = pci_id_ionic_map, 1285 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 1286 .probe = eth_ionic_pci_probe, 1287 .remove = eth_ionic_pci_remove, 1288 }; 1289 1290 RTE_PMD_REGISTER_PCI(net_ionic, rte_ionic_pmd); 1291 RTE_PMD_REGISTER_PCI_TABLE(net_ionic, pci_id_ionic_map); 1292 RTE_PMD_REGISTER_KMOD_DEP(net_ionic, "* igb_uio | uio_pci_generic | vfio-pci"); 1293 RTE_LOG_REGISTER(ionic_logtype, pmd.net.ionic, NOTICE); 1294