1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) 2 * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved. 3 */ 4 5 #include <rte_pci.h> 6 #include <rte_bus_pci.h> 7 #include <rte_ethdev.h> 8 #include <rte_ethdev_driver.h> 9 #include <rte_malloc.h> 10 #include <rte_ethdev_pci.h> 11 12 #include "ionic_logs.h" 13 #include "ionic.h" 14 #include "ionic_dev.h" 15 #include "ionic_mac_api.h" 16 #include "ionic_lif.h" 17 #include "ionic_ethdev.h" 18 #include "ionic_rxtx.h" 19 20 static int eth_ionic_dev_init(struct rte_eth_dev *eth_dev, void *init_params); 21 static int eth_ionic_dev_uninit(struct rte_eth_dev *eth_dev); 22 static int ionic_dev_info_get(struct rte_eth_dev *eth_dev, 23 struct rte_eth_dev_info *dev_info); 24 static int ionic_dev_configure(struct rte_eth_dev *dev); 25 static int ionic_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 26 static int ionic_dev_start(struct rte_eth_dev *dev); 27 static void ionic_dev_stop(struct rte_eth_dev *dev); 28 static void ionic_dev_close(struct rte_eth_dev *dev); 29 static int ionic_dev_set_link_up(struct rte_eth_dev *dev); 30 static int ionic_dev_set_link_down(struct rte_eth_dev *dev); 31 static int ionic_dev_link_update(struct rte_eth_dev *eth_dev, 32 int wait_to_complete); 33 static int ionic_flow_ctrl_get(struct rte_eth_dev *eth_dev, 34 struct rte_eth_fc_conf *fc_conf); 35 static int ionic_flow_ctrl_set(struct rte_eth_dev *eth_dev, 36 struct rte_eth_fc_conf *fc_conf); 37 static int ionic_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask); 38 static int ionic_dev_rss_reta_update(struct rte_eth_dev *eth_dev, 39 struct rte_eth_rss_reta_entry64 *reta_conf, uint16_t reta_size); 40 static int ionic_dev_rss_reta_query(struct rte_eth_dev *eth_dev, 41 struct rte_eth_rss_reta_entry64 *reta_conf, uint16_t reta_size); 42 static int ionic_dev_rss_hash_conf_get(struct rte_eth_dev *eth_dev, 43 struct rte_eth_rss_conf *rss_conf); 44 static int ionic_dev_rss_hash_update(struct rte_eth_dev *eth_dev, 45 struct rte_eth_rss_conf *rss_conf); 46 static int ionic_dev_stats_get(struct rte_eth_dev *eth_dev, 47 struct rte_eth_stats *stats); 48 static int ionic_dev_stats_reset(struct rte_eth_dev *eth_dev); 49 static int ionic_dev_xstats_get(struct rte_eth_dev *dev, 50 struct rte_eth_xstat *xstats, unsigned int n); 51 static int ionic_dev_xstats_get_by_id(struct rte_eth_dev *dev, 52 const uint64_t *ids, uint64_t *values, unsigned int n); 53 static int ionic_dev_xstats_reset(struct rte_eth_dev *dev); 54 static int ionic_dev_xstats_get_names(struct rte_eth_dev *dev, 55 struct rte_eth_xstat_name *xstats_names, unsigned int size); 56 static int ionic_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, 57 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids, 58 unsigned int limit); 59 static int ionic_dev_fw_version_get(struct rte_eth_dev *eth_dev, 60 char *fw_version, size_t fw_size); 61 62 int ionic_logtype; 63 64 static const struct rte_pci_id pci_id_ionic_map[] = { 65 { RTE_PCI_DEVICE(IONIC_PENSANDO_VENDOR_ID, IONIC_DEV_ID_ETH_PF) }, 66 { RTE_PCI_DEVICE(IONIC_PENSANDO_VENDOR_ID, IONIC_DEV_ID_ETH_VF) }, 67 { RTE_PCI_DEVICE(IONIC_PENSANDO_VENDOR_ID, IONIC_DEV_ID_ETH_MGMT) }, 68 { .vendor_id = 0, /* sentinel */ }, 69 }; 70 71 static const struct rte_eth_desc_lim rx_desc_lim = { 72 .nb_max = IONIC_MAX_RING_DESC, 73 .nb_min = IONIC_MIN_RING_DESC, 74 .nb_align = 1, 75 }; 76 77 static const struct rte_eth_desc_lim tx_desc_lim = { 78 .nb_max = IONIC_MAX_RING_DESC, 79 .nb_min = IONIC_MIN_RING_DESC, 80 .nb_align = 1, 81 .nb_seg_max = IONIC_TX_MAX_SG_ELEMS, 82 .nb_mtu_seg_max = IONIC_TX_MAX_SG_ELEMS, 83 }; 84 85 static const struct eth_dev_ops ionic_eth_dev_ops = { 86 .dev_infos_get = ionic_dev_info_get, 87 .dev_configure = ionic_dev_configure, 88 .mtu_set = ionic_dev_mtu_set, 89 .dev_start = ionic_dev_start, 90 .dev_stop = ionic_dev_stop, 91 .dev_close = ionic_dev_close, 92 .link_update = ionic_dev_link_update, 93 .dev_set_link_up = ionic_dev_set_link_up, 94 .dev_set_link_down = ionic_dev_set_link_down, 95 .mac_addr_add = ionic_dev_add_mac, 96 .mac_addr_remove = ionic_dev_remove_mac, 97 .mac_addr_set = ionic_dev_set_mac, 98 .vlan_filter_set = ionic_dev_vlan_filter_set, 99 .promiscuous_enable = ionic_dev_promiscuous_enable, 100 .promiscuous_disable = ionic_dev_promiscuous_disable, 101 .allmulticast_enable = ionic_dev_allmulticast_enable, 102 .allmulticast_disable = ionic_dev_allmulticast_disable, 103 .flow_ctrl_get = ionic_flow_ctrl_get, 104 .flow_ctrl_set = ionic_flow_ctrl_set, 105 .rxq_info_get = ionic_rxq_info_get, 106 .txq_info_get = ionic_txq_info_get, 107 .rx_queue_setup = ionic_dev_rx_queue_setup, 108 .rx_queue_release = ionic_dev_rx_queue_release, 109 .rx_queue_start = ionic_dev_rx_queue_start, 110 .rx_queue_stop = ionic_dev_rx_queue_stop, 111 .tx_queue_setup = ionic_dev_tx_queue_setup, 112 .tx_queue_release = ionic_dev_tx_queue_release, 113 .tx_queue_start = ionic_dev_tx_queue_start, 114 .tx_queue_stop = ionic_dev_tx_queue_stop, 115 .vlan_offload_set = ionic_vlan_offload_set, 116 .reta_update = ionic_dev_rss_reta_update, 117 .reta_query = ionic_dev_rss_reta_query, 118 .rss_hash_conf_get = ionic_dev_rss_hash_conf_get, 119 .rss_hash_update = ionic_dev_rss_hash_update, 120 .stats_get = ionic_dev_stats_get, 121 .stats_reset = ionic_dev_stats_reset, 122 .xstats_get = ionic_dev_xstats_get, 123 .xstats_get_by_id = ionic_dev_xstats_get_by_id, 124 .xstats_reset = ionic_dev_xstats_reset, 125 .xstats_get_names = ionic_dev_xstats_get_names, 126 .xstats_get_names_by_id = ionic_dev_xstats_get_names_by_id, 127 .fw_version_get = ionic_dev_fw_version_get, 128 }; 129 130 struct rte_ionic_xstats_name_off { 131 char name[RTE_ETH_XSTATS_NAME_SIZE]; 132 unsigned int offset; 133 }; 134 135 static const struct rte_ionic_xstats_name_off rte_ionic_xstats_strings[] = { 136 /* RX */ 137 {"rx_ucast_bytes", offsetof(struct ionic_lif_stats, 138 rx_ucast_bytes)}, 139 {"rx_ucast_packets", offsetof(struct ionic_lif_stats, 140 rx_ucast_packets)}, 141 {"rx_mcast_bytes", offsetof(struct ionic_lif_stats, 142 rx_mcast_bytes)}, 143 {"rx_mcast_packets", offsetof(struct ionic_lif_stats, 144 rx_mcast_packets)}, 145 {"rx_bcast_bytes", offsetof(struct ionic_lif_stats, 146 rx_bcast_bytes)}, 147 {"rx_bcast_packets", offsetof(struct ionic_lif_stats, 148 rx_bcast_packets)}, 149 /* RX drops */ 150 {"rx_ucast_drop_bytes", offsetof(struct ionic_lif_stats, 151 rx_ucast_drop_bytes)}, 152 {"rx_ucast_drop_packets", offsetof(struct ionic_lif_stats, 153 rx_ucast_drop_packets)}, 154 {"rx_mcast_drop_bytes", offsetof(struct ionic_lif_stats, 155 rx_mcast_drop_bytes)}, 156 {"rx_mcast_drop_packets", offsetof(struct ionic_lif_stats, 157 rx_mcast_drop_packets)}, 158 {"rx_bcast_drop_bytes", offsetof(struct ionic_lif_stats, 159 rx_bcast_drop_bytes)}, 160 {"rx_bcast_drop_packets", offsetof(struct ionic_lif_stats, 161 rx_bcast_drop_packets)}, 162 {"rx_dma_error", offsetof(struct ionic_lif_stats, 163 rx_dma_error)}, 164 /* TX */ 165 {"tx_ucast_bytes", offsetof(struct ionic_lif_stats, 166 tx_ucast_bytes)}, 167 {"tx_ucast_packets", offsetof(struct ionic_lif_stats, 168 tx_ucast_packets)}, 169 {"tx_mcast_bytes", offsetof(struct ionic_lif_stats, 170 tx_mcast_bytes)}, 171 {"tx_mcast_packets", offsetof(struct ionic_lif_stats, 172 tx_mcast_packets)}, 173 {"tx_bcast_bytes", offsetof(struct ionic_lif_stats, 174 tx_bcast_bytes)}, 175 {"tx_bcast_packets", offsetof(struct ionic_lif_stats, 176 tx_bcast_packets)}, 177 /* TX drops */ 178 {"tx_ucast_drop_bytes", offsetof(struct ionic_lif_stats, 179 tx_ucast_drop_bytes)}, 180 {"tx_ucast_drop_packets", offsetof(struct ionic_lif_stats, 181 tx_ucast_drop_packets)}, 182 {"tx_mcast_drop_bytes", offsetof(struct ionic_lif_stats, 183 tx_mcast_drop_bytes)}, 184 {"tx_mcast_drop_packets", offsetof(struct ionic_lif_stats, 185 tx_mcast_drop_packets)}, 186 {"tx_bcast_drop_bytes", offsetof(struct ionic_lif_stats, 187 tx_bcast_drop_bytes)}, 188 {"tx_bcast_drop_packets", offsetof(struct ionic_lif_stats, 189 tx_bcast_drop_packets)}, 190 {"tx_dma_error", offsetof(struct ionic_lif_stats, 191 tx_dma_error)}, 192 /* Rx Queue/Ring drops */ 193 {"rx_queue_disabled", offsetof(struct ionic_lif_stats, 194 rx_queue_disabled)}, 195 {"rx_queue_empty", offsetof(struct ionic_lif_stats, 196 rx_queue_empty)}, 197 {"rx_queue_error", offsetof(struct ionic_lif_stats, 198 rx_queue_error)}, 199 {"rx_desc_fetch_error", offsetof(struct ionic_lif_stats, 200 rx_desc_fetch_error)}, 201 {"rx_desc_data_error", offsetof(struct ionic_lif_stats, 202 rx_desc_data_error)}, 203 /* Tx Queue/Ring drops */ 204 {"tx_queue_disabled", offsetof(struct ionic_lif_stats, 205 tx_queue_disabled)}, 206 {"tx_queue_error", offsetof(struct ionic_lif_stats, 207 tx_queue_error)}, 208 {"tx_desc_fetch_error", offsetof(struct ionic_lif_stats, 209 tx_desc_fetch_error)}, 210 {"tx_desc_data_error", offsetof(struct ionic_lif_stats, 211 tx_desc_data_error)}, 212 }; 213 214 #define IONIC_NB_HW_STATS (sizeof(rte_ionic_xstats_strings) / \ 215 sizeof(rte_ionic_xstats_strings[0])) 216 217 static int 218 ionic_dev_fw_version_get(struct rte_eth_dev *eth_dev, 219 char *fw_version, size_t fw_size) 220 { 221 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 222 struct ionic_adapter *adapter = lif->adapter; 223 224 if (fw_version == NULL || fw_size <= 0) 225 return -EINVAL; 226 227 snprintf(fw_version, fw_size, "%s", 228 adapter->fw_version); 229 fw_version[fw_size - 1] = '\0'; 230 231 return 0; 232 } 233 234 /* 235 * Set device link up, enable tx. 236 */ 237 static int 238 ionic_dev_set_link_up(struct rte_eth_dev *eth_dev) 239 { 240 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 241 struct ionic_adapter *adapter = lif->adapter; 242 struct ionic_dev *idev = &adapter->idev; 243 int err; 244 245 IONIC_PRINT_CALL(); 246 247 ionic_dev_cmd_port_state(idev, IONIC_PORT_ADMIN_STATE_UP); 248 249 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 250 if (err) { 251 IONIC_PRINT(WARNING, "Failed to bring port UP"); 252 return err; 253 } 254 255 return 0; 256 } 257 258 /* 259 * Set device link down, disable tx. 260 */ 261 static int 262 ionic_dev_set_link_down(struct rte_eth_dev *eth_dev) 263 { 264 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 265 struct ionic_adapter *adapter = lif->adapter; 266 struct ionic_dev *idev = &adapter->idev; 267 int err; 268 269 IONIC_PRINT_CALL(); 270 271 ionic_dev_cmd_port_state(idev, IONIC_PORT_ADMIN_STATE_DOWN); 272 273 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 274 if (err) { 275 IONIC_PRINT(WARNING, "Failed to bring port DOWN"); 276 return err; 277 } 278 279 return 0; 280 } 281 282 static int 283 ionic_dev_link_update(struct rte_eth_dev *eth_dev, 284 int wait_to_complete __rte_unused) 285 { 286 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 287 struct ionic_adapter *adapter = lif->adapter; 288 struct rte_eth_link link; 289 290 IONIC_PRINT_CALL(); 291 292 /* Initialize */ 293 memset(&link, 0, sizeof(link)); 294 link.link_autoneg = ETH_LINK_AUTONEG; 295 296 if (!adapter->link_up) { 297 /* Interface is down */ 298 link.link_status = ETH_LINK_DOWN; 299 link.link_duplex = ETH_LINK_HALF_DUPLEX; 300 link.link_speed = ETH_SPEED_NUM_NONE; 301 } else { 302 /* Interface is up */ 303 link.link_status = ETH_LINK_UP; 304 link.link_duplex = ETH_LINK_FULL_DUPLEX; 305 switch (adapter->link_speed) { 306 case 10000: 307 link.link_speed = ETH_SPEED_NUM_10G; 308 break; 309 case 25000: 310 link.link_speed = ETH_SPEED_NUM_25G; 311 break; 312 case 40000: 313 link.link_speed = ETH_SPEED_NUM_40G; 314 break; 315 case 50000: 316 link.link_speed = ETH_SPEED_NUM_50G; 317 break; 318 case 100000: 319 link.link_speed = ETH_SPEED_NUM_100G; 320 break; 321 default: 322 link.link_speed = ETH_SPEED_NUM_NONE; 323 break; 324 } 325 } 326 327 return rte_eth_linkstatus_set(eth_dev, &link); 328 } 329 330 /** 331 * Interrupt handler triggered by NIC for handling 332 * specific interrupt. 333 * 334 * @param param 335 * The address of parameter registered before. 336 * 337 * @return 338 * void 339 */ 340 static void 341 ionic_dev_interrupt_handler(void *param) 342 { 343 struct ionic_adapter *adapter = (struct ionic_adapter *)param; 344 uint32_t i; 345 346 IONIC_PRINT(DEBUG, "->"); 347 348 for (i = 0; i < adapter->nlifs; i++) { 349 if (adapter->lifs[i]) 350 ionic_notifyq_handler(adapter->lifs[i], -1); 351 } 352 } 353 354 static int 355 ionic_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) 356 { 357 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 358 uint32_t max_frame_size; 359 int err; 360 361 IONIC_PRINT_CALL(); 362 363 /* 364 * Note: mtu check against IONIC_MIN_MTU, IONIC_MAX_MTU 365 * is done by the the API. 366 */ 367 368 /* 369 * Max frame size is MTU + Ethernet header + VLAN + QinQ 370 * (plus ETHER_CRC_LEN if the adapter is able to keep CRC) 371 */ 372 max_frame_size = mtu + RTE_ETHER_HDR_LEN + 4 + 4; 373 374 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len < max_frame_size) 375 return -EINVAL; 376 377 err = ionic_lif_change_mtu(lif, mtu); 378 if (err) 379 return err; 380 381 return 0; 382 } 383 384 static int 385 ionic_dev_info_get(struct rte_eth_dev *eth_dev, 386 struct rte_eth_dev_info *dev_info) 387 { 388 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 389 struct ionic_adapter *adapter = lif->adapter; 390 struct ionic_identity *ident = &adapter->ident; 391 392 IONIC_PRINT_CALL(); 393 394 dev_info->max_rx_queues = (uint16_t) 395 ident->lif.eth.config.queue_count[IONIC_QTYPE_RXQ]; 396 dev_info->max_tx_queues = (uint16_t) 397 ident->lif.eth.config.queue_count[IONIC_QTYPE_TXQ]; 398 /* Also add ETHER_CRC_LEN if the adapter is able to keep CRC */ 399 dev_info->min_rx_bufsize = IONIC_MIN_MTU + RTE_ETHER_HDR_LEN; 400 dev_info->max_rx_pktlen = IONIC_MAX_MTU + RTE_ETHER_HDR_LEN; 401 dev_info->max_mac_addrs = adapter->max_mac_addrs; 402 dev_info->min_mtu = IONIC_MIN_MTU; 403 dev_info->max_mtu = IONIC_MAX_MTU; 404 405 dev_info->hash_key_size = IONIC_RSS_HASH_KEY_SIZE; 406 dev_info->reta_size = ident->lif.eth.rss_ind_tbl_sz; 407 dev_info->flow_type_rss_offloads = IONIC_ETH_RSS_OFFLOAD_ALL; 408 409 dev_info->speed_capa = 410 ETH_LINK_SPEED_10G | 411 ETH_LINK_SPEED_25G | 412 ETH_LINK_SPEED_40G | 413 ETH_LINK_SPEED_50G | 414 ETH_LINK_SPEED_100G; 415 416 /* 417 * Per-queue capabilities. Actually most of the offloads are enabled 418 * by default on the port and can be used on selected queues (by adding 419 * packet flags at runtime when required) 420 */ 421 422 dev_info->rx_queue_offload_capa = 423 DEV_RX_OFFLOAD_IPV4_CKSUM | 424 DEV_RX_OFFLOAD_UDP_CKSUM | 425 DEV_RX_OFFLOAD_TCP_CKSUM | 426 0; 427 428 dev_info->tx_queue_offload_capa = 429 DEV_TX_OFFLOAD_IPV4_CKSUM | 430 DEV_TX_OFFLOAD_UDP_CKSUM | 431 DEV_TX_OFFLOAD_TCP_CKSUM | 432 DEV_TX_OFFLOAD_VLAN_INSERT | 433 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 434 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM | 435 0; 436 437 /* 438 * Per-port capabilities 439 * See ionic_set_features to request and check supported features 440 */ 441 442 dev_info->rx_offload_capa = dev_info->rx_queue_offload_capa | 443 DEV_RX_OFFLOAD_JUMBO_FRAME | 444 DEV_RX_OFFLOAD_VLAN_FILTER | 445 DEV_RX_OFFLOAD_VLAN_STRIP | 446 DEV_RX_OFFLOAD_SCATTER | 447 0; 448 449 dev_info->tx_offload_capa = dev_info->tx_queue_offload_capa | 450 DEV_TX_OFFLOAD_MULTI_SEGS | 451 DEV_TX_OFFLOAD_TCP_TSO | 452 0; 453 454 dev_info->rx_desc_lim = rx_desc_lim; 455 dev_info->tx_desc_lim = tx_desc_lim; 456 457 /* Driver-preferred Rx/Tx parameters */ 458 dev_info->default_rxportconf.burst_size = 32; 459 dev_info->default_txportconf.burst_size = 32; 460 dev_info->default_rxportconf.nb_queues = 1; 461 dev_info->default_txportconf.nb_queues = 1; 462 dev_info->default_rxportconf.ring_size = IONIC_DEF_TXRX_DESC; 463 dev_info->default_txportconf.ring_size = IONIC_DEF_TXRX_DESC; 464 465 return 0; 466 } 467 468 static int 469 ionic_flow_ctrl_get(struct rte_eth_dev *eth_dev, 470 struct rte_eth_fc_conf *fc_conf) 471 { 472 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 473 struct ionic_adapter *adapter = lif->adapter; 474 struct ionic_dev *idev = &adapter->idev; 475 476 if (idev->port_info) { 477 fc_conf->autoneg = idev->port_info->config.an_enable; 478 479 if (idev->port_info->config.pause_type) 480 fc_conf->mode = RTE_FC_FULL; 481 else 482 fc_conf->mode = RTE_FC_NONE; 483 } 484 485 return 0; 486 } 487 488 static int 489 ionic_flow_ctrl_set(struct rte_eth_dev *eth_dev, 490 struct rte_eth_fc_conf *fc_conf) 491 { 492 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 493 struct ionic_adapter *adapter = lif->adapter; 494 struct ionic_dev *idev = &adapter->idev; 495 uint8_t pause_type = IONIC_PORT_PAUSE_TYPE_NONE; 496 uint8_t an_enable; 497 498 switch (fc_conf->mode) { 499 case RTE_FC_NONE: 500 pause_type = IONIC_PORT_PAUSE_TYPE_NONE; 501 break; 502 case RTE_FC_FULL: 503 pause_type = IONIC_PORT_PAUSE_TYPE_LINK; 504 break; 505 case RTE_FC_RX_PAUSE: 506 case RTE_FC_TX_PAUSE: 507 return -ENOTSUP; 508 } 509 510 an_enable = fc_conf->autoneg; 511 512 ionic_dev_cmd_port_pause(idev, pause_type); 513 ionic_dev_cmd_port_autoneg(idev, an_enable); 514 515 return 0; 516 } 517 518 static int 519 ionic_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask) 520 { 521 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 522 struct rte_eth_rxmode *rxmode; 523 rxmode = ð_dev->data->dev_conf.rxmode; 524 int i; 525 526 if (mask & ETH_VLAN_STRIP_MASK) { 527 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) { 528 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { 529 struct ionic_qcq *rxq = 530 eth_dev->data->rx_queues[i]; 531 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP; 532 } 533 lif->features |= IONIC_ETH_HW_VLAN_RX_STRIP; 534 } else { 535 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { 536 struct ionic_qcq *rxq = 537 eth_dev->data->rx_queues[i]; 538 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP; 539 } 540 lif->features &= ~IONIC_ETH_HW_VLAN_RX_STRIP; 541 } 542 } 543 544 if (mask & ETH_VLAN_FILTER_MASK) { 545 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 546 lif->features |= IONIC_ETH_HW_VLAN_RX_FILTER; 547 else 548 lif->features &= ~IONIC_ETH_HW_VLAN_RX_FILTER; 549 } 550 551 ionic_lif_set_features(lif); 552 553 return 0; 554 } 555 556 static int 557 ionic_dev_rss_reta_update(struct rte_eth_dev *eth_dev, 558 struct rte_eth_rss_reta_entry64 *reta_conf, 559 uint16_t reta_size) 560 { 561 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 562 struct ionic_adapter *adapter = lif->adapter; 563 struct ionic_identity *ident = &adapter->ident; 564 uint32_t i, j, index, num; 565 566 IONIC_PRINT_CALL(); 567 568 if (!lif->rss_ind_tbl) { 569 IONIC_PRINT(ERR, "RSS RETA not initialized, " 570 "can't update the table"); 571 return -EINVAL; 572 } 573 574 if (reta_size != ident->lif.eth.rss_ind_tbl_sz) { 575 IONIC_PRINT(ERR, "The size of hash lookup table configured " 576 "(%d) doesn't match the number hardware can supported " 577 "(%d)", 578 reta_size, ident->lif.eth.rss_ind_tbl_sz); 579 return -EINVAL; 580 } 581 582 num = lif->adapter->ident.lif.eth.rss_ind_tbl_sz / RTE_RETA_GROUP_SIZE; 583 584 for (i = 0; i < num; i++) { 585 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++) { 586 if (reta_conf[i].mask & ((uint64_t)1 << j)) { 587 index = (i * RTE_RETA_GROUP_SIZE) + j; 588 lif->rss_ind_tbl[index] = reta_conf[i].reta[j]; 589 } 590 } 591 } 592 593 return ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL); 594 } 595 596 static int 597 ionic_dev_rss_reta_query(struct rte_eth_dev *eth_dev, 598 struct rte_eth_rss_reta_entry64 *reta_conf, 599 uint16_t reta_size) 600 { 601 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 602 struct ionic_adapter *adapter = lif->adapter; 603 struct ionic_identity *ident = &adapter->ident; 604 int i, num; 605 606 IONIC_PRINT_CALL(); 607 608 if (reta_size != ident->lif.eth.rss_ind_tbl_sz) { 609 IONIC_PRINT(ERR, "The size of hash lookup table configured " 610 "(%d) doesn't match the number hardware can supported " 611 "(%d)", 612 reta_size, ident->lif.eth.rss_ind_tbl_sz); 613 return -EINVAL; 614 } 615 616 if (!lif->rss_ind_tbl) { 617 IONIC_PRINT(ERR, "RSS RETA has not been built yet"); 618 return -EINVAL; 619 } 620 621 num = reta_size / RTE_RETA_GROUP_SIZE; 622 623 for (i = 0; i < num; i++) { 624 memcpy(reta_conf->reta, 625 &lif->rss_ind_tbl[i * RTE_RETA_GROUP_SIZE], 626 RTE_RETA_GROUP_SIZE); 627 reta_conf++; 628 } 629 630 return 0; 631 } 632 633 static int 634 ionic_dev_rss_hash_conf_get(struct rte_eth_dev *eth_dev, 635 struct rte_eth_rss_conf *rss_conf) 636 { 637 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 638 uint64_t rss_hf = 0; 639 640 IONIC_PRINT_CALL(); 641 642 if (!lif->rss_ind_tbl) { 643 IONIC_PRINT(NOTICE, "RSS not enabled"); 644 return 0; 645 } 646 647 /* Get key value (if not null, rss_key is 40-byte) */ 648 if (rss_conf->rss_key != NULL && 649 rss_conf->rss_key_len >= IONIC_RSS_HASH_KEY_SIZE) 650 memcpy(rss_conf->rss_key, lif->rss_hash_key, 651 IONIC_RSS_HASH_KEY_SIZE); 652 653 if (lif->rss_types & IONIC_RSS_TYPE_IPV4) 654 rss_hf |= ETH_RSS_IPV4; 655 if (lif->rss_types & IONIC_RSS_TYPE_IPV4_TCP) 656 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP; 657 if (lif->rss_types & IONIC_RSS_TYPE_IPV4_UDP) 658 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP; 659 if (lif->rss_types & IONIC_RSS_TYPE_IPV6) 660 rss_hf |= ETH_RSS_IPV6; 661 if (lif->rss_types & IONIC_RSS_TYPE_IPV6_TCP) 662 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP; 663 if (lif->rss_types & IONIC_RSS_TYPE_IPV6_UDP) 664 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP; 665 666 rss_conf->rss_hf = rss_hf; 667 668 return 0; 669 } 670 671 static int 672 ionic_dev_rss_hash_update(struct rte_eth_dev *eth_dev, 673 struct rte_eth_rss_conf *rss_conf) 674 { 675 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 676 uint32_t rss_types = 0; 677 uint8_t *key = NULL; 678 679 IONIC_PRINT_CALL(); 680 681 if (rss_conf->rss_key) 682 key = rss_conf->rss_key; 683 684 if ((rss_conf->rss_hf & IONIC_ETH_RSS_OFFLOAD_ALL) == 0) { 685 /* 686 * Can't disable rss through hash flags, 687 * if it is enabled by default during init 688 */ 689 if (lif->rss_ind_tbl) 690 return -EINVAL; 691 } else { 692 /* Can't enable rss if disabled by default during init */ 693 if (!lif->rss_ind_tbl) 694 return -EINVAL; 695 696 if (rss_conf->rss_hf & ETH_RSS_IPV4) 697 rss_types |= IONIC_RSS_TYPE_IPV4; 698 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) 699 rss_types |= IONIC_RSS_TYPE_IPV4_TCP; 700 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) 701 rss_types |= IONIC_RSS_TYPE_IPV4_UDP; 702 if (rss_conf->rss_hf & ETH_RSS_IPV6) 703 rss_types |= IONIC_RSS_TYPE_IPV6; 704 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) 705 rss_types |= IONIC_RSS_TYPE_IPV6_TCP; 706 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) 707 rss_types |= IONIC_RSS_TYPE_IPV6_UDP; 708 709 ionic_lif_rss_config(lif, rss_types, key, NULL); 710 } 711 712 return 0; 713 } 714 715 static int 716 ionic_dev_stats_get(struct rte_eth_dev *eth_dev, 717 struct rte_eth_stats *stats) 718 { 719 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 720 721 ionic_lif_get_stats(lif, stats); 722 723 return 0; 724 } 725 726 static int 727 ionic_dev_stats_reset(struct rte_eth_dev *eth_dev) 728 { 729 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 730 731 IONIC_PRINT_CALL(); 732 733 ionic_lif_reset_stats(lif); 734 735 return 0; 736 } 737 738 static int 739 ionic_dev_xstats_get_names(__rte_unused struct rte_eth_dev *eth_dev, 740 struct rte_eth_xstat_name *xstats_names, 741 __rte_unused unsigned int size) 742 { 743 unsigned int i; 744 745 if (xstats_names != NULL) { 746 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 747 snprintf(xstats_names[i].name, 748 sizeof(xstats_names[i].name), 749 "%s", rte_ionic_xstats_strings[i].name); 750 } 751 } 752 753 return IONIC_NB_HW_STATS; 754 } 755 756 static int 757 ionic_dev_xstats_get_names_by_id(struct rte_eth_dev *eth_dev, 758 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids, 759 unsigned int limit) 760 { 761 struct rte_eth_xstat_name xstats_names_copy[IONIC_NB_HW_STATS]; 762 uint16_t i; 763 764 if (!ids) { 765 if (xstats_names != NULL) { 766 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 767 snprintf(xstats_names[i].name, 768 sizeof(xstats_names[i].name), 769 "%s", rte_ionic_xstats_strings[i].name); 770 } 771 } 772 773 return IONIC_NB_HW_STATS; 774 } 775 776 ionic_dev_xstats_get_names_by_id(eth_dev, xstats_names_copy, NULL, 777 IONIC_NB_HW_STATS); 778 779 for (i = 0; i < limit; i++) { 780 if (ids[i] >= IONIC_NB_HW_STATS) { 781 IONIC_PRINT(ERR, "id value isn't valid"); 782 return -1; 783 } 784 785 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 786 } 787 788 return limit; 789 } 790 791 static int 792 ionic_dev_xstats_get(struct rte_eth_dev *eth_dev, struct rte_eth_xstat *xstats, 793 unsigned int n) 794 { 795 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 796 struct ionic_lif_stats hw_stats; 797 uint16_t i; 798 799 if (n < IONIC_NB_HW_STATS) 800 return IONIC_NB_HW_STATS; 801 802 ionic_lif_get_hw_stats(lif, &hw_stats); 803 804 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 805 xstats[i].value = *(uint64_t *)(((char *)&hw_stats) + 806 rte_ionic_xstats_strings[i].offset); 807 xstats[i].id = i; 808 } 809 810 return IONIC_NB_HW_STATS; 811 } 812 813 static int 814 ionic_dev_xstats_get_by_id(struct rte_eth_dev *eth_dev, const uint64_t *ids, 815 uint64_t *values, unsigned int n) 816 { 817 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 818 struct ionic_lif_stats hw_stats; 819 uint64_t values_copy[IONIC_NB_HW_STATS]; 820 uint16_t i; 821 822 if (!ids) { 823 if (!ids && n < IONIC_NB_HW_STATS) 824 return IONIC_NB_HW_STATS; 825 826 ionic_lif_get_hw_stats(lif, &hw_stats); 827 828 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 829 values[i] = *(uint64_t *)(((char *)&hw_stats) + 830 rte_ionic_xstats_strings[i].offset); 831 } 832 833 return IONIC_NB_HW_STATS; 834 } 835 836 ionic_dev_xstats_get_by_id(eth_dev, NULL, values_copy, 837 IONIC_NB_HW_STATS); 838 839 for (i = 0; i < n; i++) { 840 if (ids[i] >= IONIC_NB_HW_STATS) { 841 IONIC_PRINT(ERR, "id value isn't valid"); 842 return -1; 843 } 844 845 values[i] = values_copy[ids[i]]; 846 } 847 848 return n; 849 } 850 851 static int 852 ionic_dev_xstats_reset(struct rte_eth_dev *eth_dev) 853 { 854 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 855 856 ionic_lif_reset_hw_stats(lif); 857 858 return 0; 859 } 860 861 static int 862 ionic_dev_configure(struct rte_eth_dev *eth_dev) 863 { 864 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 865 int err; 866 867 IONIC_PRINT_CALL(); 868 869 err = ionic_lif_configure(lif); 870 if (err) { 871 IONIC_PRINT(ERR, "Cannot configure LIF: %d", err); 872 return err; 873 } 874 875 return 0; 876 } 877 878 static inline uint32_t 879 ionic_parse_link_speeds(uint16_t link_speeds) 880 { 881 if (link_speeds & ETH_LINK_SPEED_100G) 882 return 100000; 883 else if (link_speeds & ETH_LINK_SPEED_50G) 884 return 50000; 885 else if (link_speeds & ETH_LINK_SPEED_40G) 886 return 40000; 887 else if (link_speeds & ETH_LINK_SPEED_25G) 888 return 25000; 889 else if (link_speeds & ETH_LINK_SPEED_10G) 890 return 10000; 891 else 892 return 0; 893 } 894 895 /* 896 * Configure device link speed and setup link. 897 * It returns 0 on success. 898 */ 899 static int 900 ionic_dev_start(struct rte_eth_dev *eth_dev) 901 { 902 struct rte_eth_conf *dev_conf = ð_dev->data->dev_conf; 903 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 904 struct ionic_adapter *adapter = lif->adapter; 905 struct ionic_dev *idev = &adapter->idev; 906 uint32_t allowed_speeds; 907 int err; 908 909 IONIC_PRINT_CALL(); 910 911 allowed_speeds = 912 ETH_LINK_SPEED_FIXED | 913 ETH_LINK_SPEED_10G | 914 ETH_LINK_SPEED_25G | 915 ETH_LINK_SPEED_40G | 916 ETH_LINK_SPEED_50G | 917 ETH_LINK_SPEED_100G; 918 919 if (dev_conf->link_speeds & ~allowed_speeds) { 920 IONIC_PRINT(ERR, "Invalid link setting"); 921 return -EINVAL; 922 } 923 924 err = ionic_lif_start(lif); 925 if (err) { 926 IONIC_PRINT(ERR, "Cannot start LIF: %d", err); 927 return err; 928 } 929 930 if (eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) { 931 uint32_t speed = ionic_parse_link_speeds(dev_conf->link_speeds); 932 933 if (speed) 934 ionic_dev_cmd_port_speed(idev, speed); 935 } 936 937 ionic_dev_link_update(eth_dev, 0); 938 939 return 0; 940 } 941 942 /* 943 * Stop device: disable rx and tx functions to allow for reconfiguring. 944 */ 945 static void 946 ionic_dev_stop(struct rte_eth_dev *eth_dev) 947 { 948 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 949 int err; 950 951 IONIC_PRINT_CALL(); 952 953 err = ionic_lif_stop(lif); 954 if (err) 955 IONIC_PRINT(ERR, "Cannot stop LIF: %d", err); 956 } 957 958 /* 959 * Reset and stop device. 960 */ 961 static void 962 ionic_dev_close(struct rte_eth_dev *eth_dev) 963 { 964 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 965 int err; 966 967 IONIC_PRINT_CALL(); 968 969 err = ionic_lif_stop(lif); 970 if (err) { 971 IONIC_PRINT(ERR, "Cannot stop LIF: %d", err); 972 return; 973 } 974 975 err = eth_ionic_dev_uninit(eth_dev); 976 if (err) { 977 IONIC_PRINT(ERR, "Cannot destroy LIF: %d", err); 978 return; 979 } 980 } 981 982 static int 983 eth_ionic_dev_init(struct rte_eth_dev *eth_dev, void *init_params) 984 { 985 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 986 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 987 struct ionic_adapter *adapter = (struct ionic_adapter *)init_params; 988 int err; 989 990 IONIC_PRINT_CALL(); 991 992 eth_dev->dev_ops = &ionic_eth_dev_ops; 993 eth_dev->rx_pkt_burst = &ionic_recv_pkts; 994 eth_dev->tx_pkt_burst = &ionic_xmit_pkts; 995 eth_dev->tx_pkt_prepare = &ionic_prep_pkts; 996 997 /* Multi-process not supported, primary does initialization anyway */ 998 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 999 return 0; 1000 1001 rte_eth_copy_pci_info(eth_dev, pci_dev); 1002 1003 lif->index = adapter->nlifs; 1004 lif->eth_dev = eth_dev; 1005 lif->adapter = adapter; 1006 adapter->lifs[adapter->nlifs] = lif; 1007 1008 IONIC_PRINT(DEBUG, "Up to %u MAC addresses supported", 1009 adapter->max_mac_addrs); 1010 1011 /* Allocate memory for storing MAC addresses */ 1012 eth_dev->data->mac_addrs = rte_zmalloc("ionic", 1013 RTE_ETHER_ADDR_LEN * adapter->max_mac_addrs, 0); 1014 1015 if (eth_dev->data->mac_addrs == NULL) { 1016 IONIC_PRINT(ERR, "Failed to allocate %u bytes needed to " 1017 "store MAC addresses", 1018 RTE_ETHER_ADDR_LEN * adapter->max_mac_addrs); 1019 err = -ENOMEM; 1020 goto err; 1021 } 1022 1023 err = ionic_lif_alloc(lif); 1024 if (err) { 1025 IONIC_PRINT(ERR, "Cannot allocate LIFs: %d, aborting", 1026 err); 1027 goto err; 1028 } 1029 1030 err = ionic_lif_init(lif); 1031 if (err) { 1032 IONIC_PRINT(ERR, "Cannot init LIFs: %d, aborting", err); 1033 goto err_free_lif; 1034 } 1035 1036 /* Copy the MAC address */ 1037 rte_ether_addr_copy((struct rte_ether_addr *)lif->mac_addr, 1038 ð_dev->data->mac_addrs[0]); 1039 1040 IONIC_PRINT(DEBUG, "Port %u initialized", eth_dev->data->port_id); 1041 1042 return 0; 1043 1044 err_free_lif: 1045 ionic_lif_free(lif); 1046 err: 1047 return err; 1048 } 1049 1050 static int 1051 eth_ionic_dev_uninit(struct rte_eth_dev *eth_dev) 1052 { 1053 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 1054 struct ionic_adapter *adapter = lif->adapter; 1055 1056 IONIC_PRINT_CALL(); 1057 1058 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1059 return 0; 1060 1061 adapter->lifs[lif->index] = NULL; 1062 1063 ionic_lif_deinit(lif); 1064 ionic_lif_free(lif); 1065 1066 eth_dev->dev_ops = NULL; 1067 eth_dev->rx_pkt_burst = NULL; 1068 eth_dev->tx_pkt_burst = NULL; 1069 eth_dev->tx_pkt_prepare = NULL; 1070 1071 return 0; 1072 } 1073 1074 static int 1075 ionic_configure_intr(struct ionic_adapter *adapter) 1076 { 1077 struct rte_pci_device *pci_dev = adapter->pci_dev; 1078 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1079 int err; 1080 1081 IONIC_PRINT(DEBUG, "Configuring %u intrs", adapter->nintrs); 1082 1083 if (rte_intr_efd_enable(intr_handle, adapter->nintrs)) { 1084 IONIC_PRINT(ERR, "Fail to create eventfd"); 1085 return -1; 1086 } 1087 1088 if (rte_intr_dp_is_en(intr_handle)) 1089 IONIC_PRINT(DEBUG, 1090 "Packet I/O interrupt on datapath is enabled"); 1091 1092 if (!intr_handle->intr_vec) { 1093 intr_handle->intr_vec = rte_zmalloc("intr_vec", 1094 adapter->nintrs * sizeof(int), 0); 1095 1096 if (!intr_handle->intr_vec) { 1097 IONIC_PRINT(ERR, "Failed to allocate %u vectors", 1098 adapter->nintrs); 1099 return -ENOMEM; 1100 } 1101 } 1102 1103 err = rte_intr_callback_register(intr_handle, 1104 ionic_dev_interrupt_handler, 1105 adapter); 1106 1107 if (err) { 1108 IONIC_PRINT(ERR, 1109 "Failure registering interrupts handler (%d)", 1110 err); 1111 return err; 1112 } 1113 1114 /* enable intr mapping */ 1115 err = rte_intr_enable(intr_handle); 1116 1117 if (err) { 1118 IONIC_PRINT(ERR, "Failure enabling interrupts (%d)", err); 1119 return err; 1120 } 1121 1122 return 0; 1123 } 1124 1125 static void 1126 ionic_unconfigure_intr(struct ionic_adapter *adapter) 1127 { 1128 struct rte_pci_device *pci_dev = adapter->pci_dev; 1129 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1130 1131 rte_intr_disable(intr_handle); 1132 1133 rte_intr_callback_unregister(intr_handle, 1134 ionic_dev_interrupt_handler, 1135 adapter); 1136 } 1137 1138 static int 1139 eth_ionic_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1140 struct rte_pci_device *pci_dev) 1141 { 1142 char name[RTE_ETH_NAME_MAX_LEN]; 1143 struct rte_mem_resource *resource; 1144 struct ionic_adapter *adapter; 1145 struct ionic_hw *hw; 1146 unsigned long i; 1147 int err; 1148 1149 /* Check structs (trigger error at compilation time) */ 1150 ionic_struct_size_checks(); 1151 1152 /* Multi-process not supported */ 1153 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1154 err = -EPERM; 1155 goto err; 1156 } 1157 1158 IONIC_PRINT(DEBUG, "Initializing device %s", 1159 pci_dev->device.name); 1160 1161 adapter = rte_zmalloc("ionic", sizeof(*adapter), 0); 1162 if (!adapter) { 1163 IONIC_PRINT(ERR, "OOM"); 1164 err = -ENOMEM; 1165 goto err; 1166 } 1167 1168 adapter->pci_dev = pci_dev; 1169 hw = &adapter->hw; 1170 1171 hw->device_id = pci_dev->id.device_id; 1172 hw->vendor_id = pci_dev->id.vendor_id; 1173 1174 err = ionic_init_mac(hw); 1175 if (err != 0) { 1176 IONIC_PRINT(ERR, "Mac init failed: %d", err); 1177 err = -EIO; 1178 goto err_free_adapter; 1179 } 1180 1181 adapter->is_mgmt_nic = (pci_dev->id.device_id == IONIC_DEV_ID_ETH_MGMT); 1182 1183 adapter->num_bars = 0; 1184 for (i = 0; i < PCI_MAX_RESOURCE && i < IONIC_BARS_MAX; i++) { 1185 resource = &pci_dev->mem_resource[i]; 1186 if (resource->phys_addr == 0 || resource->len == 0) 1187 continue; 1188 adapter->bars[adapter->num_bars].vaddr = resource->addr; 1189 adapter->bars[adapter->num_bars].bus_addr = resource->phys_addr; 1190 adapter->bars[adapter->num_bars].len = resource->len; 1191 adapter->num_bars++; 1192 } 1193 1194 /* Discover ionic dev resources */ 1195 1196 err = ionic_setup(adapter); 1197 if (err) { 1198 IONIC_PRINT(ERR, "Cannot setup device: %d, aborting", err); 1199 goto err_free_adapter; 1200 } 1201 1202 err = ionic_identify(adapter); 1203 if (err) { 1204 IONIC_PRINT(ERR, "Cannot identify device: %d, aborting", 1205 err); 1206 goto err_free_adapter; 1207 } 1208 1209 err = ionic_init(adapter); 1210 if (err) { 1211 IONIC_PRINT(ERR, "Cannot init device: %d, aborting", err); 1212 goto err_free_adapter; 1213 } 1214 1215 /* Configure the ports */ 1216 err = ionic_port_identify(adapter); 1217 if (err) { 1218 IONIC_PRINT(ERR, "Cannot identify port: %d, aborting", 1219 err); 1220 goto err_free_adapter; 1221 } 1222 1223 err = ionic_port_init(adapter); 1224 if (err) { 1225 IONIC_PRINT(ERR, "Cannot init port: %d, aborting", err); 1226 goto err_free_adapter; 1227 } 1228 1229 /* Configure LIFs */ 1230 err = ionic_lif_identify(adapter); 1231 if (err) { 1232 IONIC_PRINT(ERR, "Cannot identify lif: %d, aborting", err); 1233 goto err_free_adapter; 1234 } 1235 1236 /* Allocate and init LIFs */ 1237 err = ionic_lifs_size(adapter); 1238 if (err) { 1239 IONIC_PRINT(ERR, "Cannot size LIFs: %d, aborting", err); 1240 goto err_free_adapter; 1241 } 1242 1243 adapter->max_mac_addrs = adapter->ident.lif.eth.max_ucast_filters; 1244 1245 adapter->nlifs = 0; 1246 for (i = 0; i < adapter->ident.dev.nlifs; i++) { 1247 snprintf(name, sizeof(name), "net_%s_lif_%lu", 1248 pci_dev->device.name, i); 1249 1250 err = rte_eth_dev_create(&pci_dev->device, name, 1251 sizeof(struct ionic_lif), 1252 NULL, NULL, 1253 eth_ionic_dev_init, adapter); 1254 if (err) { 1255 IONIC_PRINT(ERR, "Cannot create eth device for " 1256 "ionic lif %s", name); 1257 break; 1258 } 1259 1260 adapter->nlifs++; 1261 } 1262 1263 err = ionic_configure_intr(adapter); 1264 1265 if (err) { 1266 IONIC_PRINT(ERR, "Failed to configure interrupts"); 1267 goto err_free_adapter; 1268 } 1269 1270 return 0; 1271 1272 err_free_adapter: 1273 rte_free(adapter); 1274 err: 1275 return err; 1276 } 1277 1278 static int 1279 eth_ionic_pci_remove(struct rte_pci_device *pci_dev __rte_unused) 1280 { 1281 char name[RTE_ETH_NAME_MAX_LEN]; 1282 struct ionic_adapter *adapter = NULL; 1283 struct rte_eth_dev *eth_dev; 1284 struct ionic_lif *lif; 1285 uint32_t i; 1286 1287 /* Adapter lookup is using (the first) eth_dev name */ 1288 snprintf(name, sizeof(name), "net_%s_lif_0", 1289 pci_dev->device.name); 1290 1291 eth_dev = rte_eth_dev_allocated(name); 1292 if (eth_dev) { 1293 lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 1294 adapter = lif->adapter; 1295 } 1296 1297 if (adapter) { 1298 ionic_unconfigure_intr(adapter); 1299 1300 for (i = 0; i < adapter->nlifs; i++) { 1301 lif = adapter->lifs[i]; 1302 rte_eth_dev_destroy(lif->eth_dev, eth_ionic_dev_uninit); 1303 } 1304 1305 rte_free(adapter); 1306 } 1307 1308 return 0; 1309 } 1310 1311 static struct rte_pci_driver rte_ionic_pmd = { 1312 .id_table = pci_id_ionic_map, 1313 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 1314 .probe = eth_ionic_pci_probe, 1315 .remove = eth_ionic_pci_remove, 1316 }; 1317 1318 RTE_PMD_REGISTER_PCI(net_ionic, rte_ionic_pmd); 1319 RTE_PMD_REGISTER_PCI_TABLE(net_ionic, pci_id_ionic_map); 1320 RTE_PMD_REGISTER_KMOD_DEP(net_ionic, "* igb_uio | uio_pci_generic | vfio-pci"); 1321 1322 RTE_INIT(ionic_init_log) 1323 { 1324 ionic_logtype = rte_log_register("pmd.net.ionic"); 1325 if (ionic_logtype >= 0) 1326 rte_log_set_level(ionic_logtype, RTE_LOG_NOTICE); 1327 } 1328