1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) 2 * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved. 3 */ 4 5 #include <rte_pci.h> 6 #include <rte_bus_pci.h> 7 #include <rte_ethdev.h> 8 #include <ethdev_driver.h> 9 #include <rte_malloc.h> 10 #include <ethdev_pci.h> 11 12 #include "ionic_logs.h" 13 #include "ionic.h" 14 #include "ionic_dev.h" 15 #include "ionic_mac_api.h" 16 #include "ionic_lif.h" 17 #include "ionic_ethdev.h" 18 #include "ionic_rxtx.h" 19 20 static int eth_ionic_dev_init(struct rte_eth_dev *eth_dev, void *init_params); 21 static int eth_ionic_dev_uninit(struct rte_eth_dev *eth_dev); 22 static int ionic_dev_info_get(struct rte_eth_dev *eth_dev, 23 struct rte_eth_dev_info *dev_info); 24 static int ionic_dev_configure(struct rte_eth_dev *dev); 25 static int ionic_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 26 static int ionic_dev_start(struct rte_eth_dev *dev); 27 static int ionic_dev_stop(struct rte_eth_dev *dev); 28 static int ionic_dev_close(struct rte_eth_dev *dev); 29 static int ionic_dev_set_link_up(struct rte_eth_dev *dev); 30 static int ionic_dev_set_link_down(struct rte_eth_dev *dev); 31 static int ionic_flow_ctrl_get(struct rte_eth_dev *eth_dev, 32 struct rte_eth_fc_conf *fc_conf); 33 static int ionic_flow_ctrl_set(struct rte_eth_dev *eth_dev, 34 struct rte_eth_fc_conf *fc_conf); 35 static int ionic_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask); 36 static int ionic_dev_rss_reta_update(struct rte_eth_dev *eth_dev, 37 struct rte_eth_rss_reta_entry64 *reta_conf, uint16_t reta_size); 38 static int ionic_dev_rss_reta_query(struct rte_eth_dev *eth_dev, 39 struct rte_eth_rss_reta_entry64 *reta_conf, uint16_t reta_size); 40 static int ionic_dev_rss_hash_conf_get(struct rte_eth_dev *eth_dev, 41 struct rte_eth_rss_conf *rss_conf); 42 static int ionic_dev_rss_hash_update(struct rte_eth_dev *eth_dev, 43 struct rte_eth_rss_conf *rss_conf); 44 static int ionic_dev_stats_get(struct rte_eth_dev *eth_dev, 45 struct rte_eth_stats *stats); 46 static int ionic_dev_stats_reset(struct rte_eth_dev *eth_dev); 47 static int ionic_dev_xstats_get(struct rte_eth_dev *dev, 48 struct rte_eth_xstat *xstats, unsigned int n); 49 static int ionic_dev_xstats_get_by_id(struct rte_eth_dev *dev, 50 const uint64_t *ids, uint64_t *values, unsigned int n); 51 static int ionic_dev_xstats_reset(struct rte_eth_dev *dev); 52 static int ionic_dev_xstats_get_names(struct rte_eth_dev *dev, 53 struct rte_eth_xstat_name *xstats_names, unsigned int size); 54 static int ionic_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, 55 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids, 56 unsigned int limit); 57 static int ionic_dev_fw_version_get(struct rte_eth_dev *eth_dev, 58 char *fw_version, size_t fw_size); 59 60 static const struct rte_pci_id pci_id_ionic_map[] = { 61 { RTE_PCI_DEVICE(IONIC_PENSANDO_VENDOR_ID, IONIC_DEV_ID_ETH_PF) }, 62 { RTE_PCI_DEVICE(IONIC_PENSANDO_VENDOR_ID, IONIC_DEV_ID_ETH_VF) }, 63 { RTE_PCI_DEVICE(IONIC_PENSANDO_VENDOR_ID, IONIC_DEV_ID_ETH_MGMT) }, 64 { .vendor_id = 0, /* sentinel */ }, 65 }; 66 67 static const struct rte_eth_desc_lim rx_desc_lim = { 68 .nb_max = IONIC_MAX_RING_DESC, 69 .nb_min = IONIC_MIN_RING_DESC, 70 .nb_align = 1, 71 }; 72 73 static const struct rte_eth_desc_lim tx_desc_lim = { 74 .nb_max = IONIC_MAX_RING_DESC, 75 .nb_min = IONIC_MIN_RING_DESC, 76 .nb_align = 1, 77 .nb_seg_max = IONIC_TX_MAX_SG_ELEMS, 78 .nb_mtu_seg_max = IONIC_TX_MAX_SG_ELEMS, 79 }; 80 81 static const struct eth_dev_ops ionic_eth_dev_ops = { 82 .dev_infos_get = ionic_dev_info_get, 83 .dev_configure = ionic_dev_configure, 84 .mtu_set = ionic_dev_mtu_set, 85 .dev_start = ionic_dev_start, 86 .dev_stop = ionic_dev_stop, 87 .dev_close = ionic_dev_close, 88 .link_update = ionic_dev_link_update, 89 .dev_set_link_up = ionic_dev_set_link_up, 90 .dev_set_link_down = ionic_dev_set_link_down, 91 .mac_addr_add = ionic_dev_add_mac, 92 .mac_addr_remove = ionic_dev_remove_mac, 93 .mac_addr_set = ionic_dev_set_mac, 94 .vlan_filter_set = ionic_dev_vlan_filter_set, 95 .promiscuous_enable = ionic_dev_promiscuous_enable, 96 .promiscuous_disable = ionic_dev_promiscuous_disable, 97 .allmulticast_enable = ionic_dev_allmulticast_enable, 98 .allmulticast_disable = ionic_dev_allmulticast_disable, 99 .flow_ctrl_get = ionic_flow_ctrl_get, 100 .flow_ctrl_set = ionic_flow_ctrl_set, 101 .rxq_info_get = ionic_rxq_info_get, 102 .txq_info_get = ionic_txq_info_get, 103 .rx_queue_setup = ionic_dev_rx_queue_setup, 104 .rx_queue_release = ionic_dev_rx_queue_release, 105 .rx_queue_start = ionic_dev_rx_queue_start, 106 .rx_queue_stop = ionic_dev_rx_queue_stop, 107 .tx_queue_setup = ionic_dev_tx_queue_setup, 108 .tx_queue_release = ionic_dev_tx_queue_release, 109 .tx_queue_start = ionic_dev_tx_queue_start, 110 .tx_queue_stop = ionic_dev_tx_queue_stop, 111 .vlan_offload_set = ionic_vlan_offload_set, 112 .reta_update = ionic_dev_rss_reta_update, 113 .reta_query = ionic_dev_rss_reta_query, 114 .rss_hash_conf_get = ionic_dev_rss_hash_conf_get, 115 .rss_hash_update = ionic_dev_rss_hash_update, 116 .stats_get = ionic_dev_stats_get, 117 .stats_reset = ionic_dev_stats_reset, 118 .xstats_get = ionic_dev_xstats_get, 119 .xstats_get_by_id = ionic_dev_xstats_get_by_id, 120 .xstats_reset = ionic_dev_xstats_reset, 121 .xstats_get_names = ionic_dev_xstats_get_names, 122 .xstats_get_names_by_id = ionic_dev_xstats_get_names_by_id, 123 .fw_version_get = ionic_dev_fw_version_get, 124 }; 125 126 struct rte_ionic_xstats_name_off { 127 char name[RTE_ETH_XSTATS_NAME_SIZE]; 128 unsigned int offset; 129 }; 130 131 static const struct rte_ionic_xstats_name_off rte_ionic_xstats_strings[] = { 132 /* RX */ 133 {"rx_ucast_bytes", offsetof(struct ionic_lif_stats, 134 rx_ucast_bytes)}, 135 {"rx_ucast_packets", offsetof(struct ionic_lif_stats, 136 rx_ucast_packets)}, 137 {"rx_mcast_bytes", offsetof(struct ionic_lif_stats, 138 rx_mcast_bytes)}, 139 {"rx_mcast_packets", offsetof(struct ionic_lif_stats, 140 rx_mcast_packets)}, 141 {"rx_bcast_bytes", offsetof(struct ionic_lif_stats, 142 rx_bcast_bytes)}, 143 {"rx_bcast_packets", offsetof(struct ionic_lif_stats, 144 rx_bcast_packets)}, 145 /* RX drops */ 146 {"rx_ucast_drop_bytes", offsetof(struct ionic_lif_stats, 147 rx_ucast_drop_bytes)}, 148 {"rx_ucast_drop_packets", offsetof(struct ionic_lif_stats, 149 rx_ucast_drop_packets)}, 150 {"rx_mcast_drop_bytes", offsetof(struct ionic_lif_stats, 151 rx_mcast_drop_bytes)}, 152 {"rx_mcast_drop_packets", offsetof(struct ionic_lif_stats, 153 rx_mcast_drop_packets)}, 154 {"rx_bcast_drop_bytes", offsetof(struct ionic_lif_stats, 155 rx_bcast_drop_bytes)}, 156 {"rx_bcast_drop_packets", offsetof(struct ionic_lif_stats, 157 rx_bcast_drop_packets)}, 158 {"rx_dma_error", offsetof(struct ionic_lif_stats, 159 rx_dma_error)}, 160 /* TX */ 161 {"tx_ucast_bytes", offsetof(struct ionic_lif_stats, 162 tx_ucast_bytes)}, 163 {"tx_ucast_packets", offsetof(struct ionic_lif_stats, 164 tx_ucast_packets)}, 165 {"tx_mcast_bytes", offsetof(struct ionic_lif_stats, 166 tx_mcast_bytes)}, 167 {"tx_mcast_packets", offsetof(struct ionic_lif_stats, 168 tx_mcast_packets)}, 169 {"tx_bcast_bytes", offsetof(struct ionic_lif_stats, 170 tx_bcast_bytes)}, 171 {"tx_bcast_packets", offsetof(struct ionic_lif_stats, 172 tx_bcast_packets)}, 173 /* TX drops */ 174 {"tx_ucast_drop_bytes", offsetof(struct ionic_lif_stats, 175 tx_ucast_drop_bytes)}, 176 {"tx_ucast_drop_packets", offsetof(struct ionic_lif_stats, 177 tx_ucast_drop_packets)}, 178 {"tx_mcast_drop_bytes", offsetof(struct ionic_lif_stats, 179 tx_mcast_drop_bytes)}, 180 {"tx_mcast_drop_packets", offsetof(struct ionic_lif_stats, 181 tx_mcast_drop_packets)}, 182 {"tx_bcast_drop_bytes", offsetof(struct ionic_lif_stats, 183 tx_bcast_drop_bytes)}, 184 {"tx_bcast_drop_packets", offsetof(struct ionic_lif_stats, 185 tx_bcast_drop_packets)}, 186 {"tx_dma_error", offsetof(struct ionic_lif_stats, 187 tx_dma_error)}, 188 /* Rx Queue/Ring drops */ 189 {"rx_queue_disabled", offsetof(struct ionic_lif_stats, 190 rx_queue_disabled)}, 191 {"rx_queue_empty", offsetof(struct ionic_lif_stats, 192 rx_queue_empty)}, 193 {"rx_queue_error", offsetof(struct ionic_lif_stats, 194 rx_queue_error)}, 195 {"rx_desc_fetch_error", offsetof(struct ionic_lif_stats, 196 rx_desc_fetch_error)}, 197 {"rx_desc_data_error", offsetof(struct ionic_lif_stats, 198 rx_desc_data_error)}, 199 /* Tx Queue/Ring drops */ 200 {"tx_queue_disabled", offsetof(struct ionic_lif_stats, 201 tx_queue_disabled)}, 202 {"tx_queue_error", offsetof(struct ionic_lif_stats, 203 tx_queue_error)}, 204 {"tx_desc_fetch_error", offsetof(struct ionic_lif_stats, 205 tx_desc_fetch_error)}, 206 {"tx_desc_data_error", offsetof(struct ionic_lif_stats, 207 tx_desc_data_error)}, 208 }; 209 210 #define IONIC_NB_HW_STATS (sizeof(rte_ionic_xstats_strings) / \ 211 sizeof(rte_ionic_xstats_strings[0])) 212 213 static int 214 ionic_dev_fw_version_get(struct rte_eth_dev *eth_dev, 215 char *fw_version, size_t fw_size) 216 { 217 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 218 struct ionic_adapter *adapter = lif->adapter; 219 220 if (fw_version == NULL || fw_size <= 0) 221 return -EINVAL; 222 223 snprintf(fw_version, fw_size, "%s", 224 adapter->fw_version); 225 fw_version[fw_size - 1] = '\0'; 226 227 return 0; 228 } 229 230 /* 231 * Set device link up, enable tx. 232 */ 233 static int 234 ionic_dev_set_link_up(struct rte_eth_dev *eth_dev) 235 { 236 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 237 int err; 238 239 IONIC_PRINT_CALL(); 240 241 err = ionic_lif_start(lif); 242 if (err) 243 IONIC_PRINT(ERR, "Could not start lif to set link up"); 244 245 ionic_dev_link_update(lif->eth_dev, 0); 246 247 return err; 248 } 249 250 /* 251 * Set device link down, disable tx. 252 */ 253 static int 254 ionic_dev_set_link_down(struct rte_eth_dev *eth_dev) 255 { 256 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 257 258 IONIC_PRINT_CALL(); 259 260 ionic_lif_stop(lif); 261 262 ionic_dev_link_update(lif->eth_dev, 0); 263 264 return 0; 265 } 266 267 int 268 ionic_dev_link_update(struct rte_eth_dev *eth_dev, 269 int wait_to_complete __rte_unused) 270 { 271 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 272 struct ionic_adapter *adapter = lif->adapter; 273 struct rte_eth_link link; 274 275 IONIC_PRINT_CALL(); 276 277 /* Initialize */ 278 memset(&link, 0, sizeof(link)); 279 280 if (adapter->idev.port_info->config.an_enable) { 281 link.link_autoneg = ETH_LINK_AUTONEG; 282 } 283 284 if (!adapter->link_up || 285 !(lif->state & IONIC_LIF_F_UP)) { 286 /* Interface is down */ 287 link.link_status = ETH_LINK_DOWN; 288 link.link_duplex = ETH_LINK_HALF_DUPLEX; 289 link.link_speed = ETH_SPEED_NUM_NONE; 290 } else { 291 /* Interface is up */ 292 link.link_status = ETH_LINK_UP; 293 link.link_duplex = ETH_LINK_FULL_DUPLEX; 294 switch (adapter->link_speed) { 295 case 10000: 296 link.link_speed = ETH_SPEED_NUM_10G; 297 break; 298 case 25000: 299 link.link_speed = ETH_SPEED_NUM_25G; 300 break; 301 case 40000: 302 link.link_speed = ETH_SPEED_NUM_40G; 303 break; 304 case 50000: 305 link.link_speed = ETH_SPEED_NUM_50G; 306 break; 307 case 100000: 308 link.link_speed = ETH_SPEED_NUM_100G; 309 break; 310 default: 311 link.link_speed = ETH_SPEED_NUM_NONE; 312 break; 313 } 314 } 315 316 return rte_eth_linkstatus_set(eth_dev, &link); 317 } 318 319 /** 320 * Interrupt handler triggered by NIC for handling 321 * specific interrupt. 322 * 323 * @param param 324 * The address of parameter registered before. 325 * 326 * @return 327 * void 328 */ 329 static void 330 ionic_dev_interrupt_handler(void *param) 331 { 332 struct ionic_adapter *adapter = (struct ionic_adapter *)param; 333 334 IONIC_PRINT(DEBUG, "->"); 335 336 if (adapter->lif) 337 ionic_notifyq_handler(adapter->lif, -1); 338 } 339 340 static int 341 ionic_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) 342 { 343 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 344 uint32_t max_frame_size; 345 int err; 346 347 IONIC_PRINT_CALL(); 348 349 /* 350 * Note: mtu check against IONIC_MIN_MTU, IONIC_MAX_MTU 351 * is done by the the API. 352 */ 353 354 /* 355 * Max frame size is MTU + Ethernet header + VLAN + QinQ 356 * (plus ETHER_CRC_LEN if the adapter is able to keep CRC) 357 */ 358 max_frame_size = mtu + RTE_ETHER_HDR_LEN + 4 + 4; 359 360 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len < max_frame_size) 361 return -EINVAL; 362 363 err = ionic_lif_change_mtu(lif, mtu); 364 if (err) 365 return err; 366 367 return 0; 368 } 369 370 static int 371 ionic_dev_info_get(struct rte_eth_dev *eth_dev, 372 struct rte_eth_dev_info *dev_info) 373 { 374 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 375 struct ionic_adapter *adapter = lif->adapter; 376 struct ionic_identity *ident = &adapter->ident; 377 union ionic_lif_config *cfg = &ident->lif.eth.config; 378 379 IONIC_PRINT_CALL(); 380 381 dev_info->max_rx_queues = (uint16_t) 382 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_RXQ]); 383 dev_info->max_tx_queues = (uint16_t) 384 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ]); 385 386 /* Also add ETHER_CRC_LEN if the adapter is able to keep CRC */ 387 dev_info->min_rx_bufsize = IONIC_MIN_MTU + RTE_ETHER_HDR_LEN; 388 dev_info->max_rx_pktlen = IONIC_MAX_MTU + RTE_ETHER_HDR_LEN; 389 dev_info->max_mac_addrs = adapter->max_mac_addrs; 390 dev_info->min_mtu = IONIC_MIN_MTU; 391 dev_info->max_mtu = IONIC_MAX_MTU; 392 393 dev_info->hash_key_size = IONIC_RSS_HASH_KEY_SIZE; 394 dev_info->reta_size = rte_le_to_cpu_16(ident->lif.eth.rss_ind_tbl_sz); 395 dev_info->flow_type_rss_offloads = IONIC_ETH_RSS_OFFLOAD_ALL; 396 397 dev_info->speed_capa = 398 ETH_LINK_SPEED_10G | 399 ETH_LINK_SPEED_25G | 400 ETH_LINK_SPEED_40G | 401 ETH_LINK_SPEED_50G | 402 ETH_LINK_SPEED_100G; 403 404 /* 405 * Per-queue capabilities 406 * RTE does not support disabling a feature on a queue if it is 407 * enabled globally on the device. Thus the driver does not advertise 408 * capabilities like DEV_TX_OFFLOAD_IPV4_CKSUM as per-queue even 409 * though the driver would be otherwise capable of disabling it on 410 * a per-queue basis. 411 */ 412 413 dev_info->rx_queue_offload_capa = 0; 414 dev_info->tx_queue_offload_capa = 0; 415 416 /* 417 * Per-port capabilities 418 * See ionic_set_features to request and check supported features 419 */ 420 421 dev_info->rx_offload_capa = dev_info->rx_queue_offload_capa | 422 DEV_RX_OFFLOAD_IPV4_CKSUM | 423 DEV_RX_OFFLOAD_UDP_CKSUM | 424 DEV_RX_OFFLOAD_TCP_CKSUM | 425 DEV_RX_OFFLOAD_JUMBO_FRAME | 426 DEV_RX_OFFLOAD_VLAN_FILTER | 427 DEV_RX_OFFLOAD_VLAN_STRIP | 428 DEV_RX_OFFLOAD_SCATTER | 429 DEV_RX_OFFLOAD_RSS_HASH | 430 0; 431 432 dev_info->tx_offload_capa = dev_info->tx_queue_offload_capa | 433 DEV_TX_OFFLOAD_IPV4_CKSUM | 434 DEV_TX_OFFLOAD_UDP_CKSUM | 435 DEV_TX_OFFLOAD_TCP_CKSUM | 436 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 437 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM | 438 DEV_TX_OFFLOAD_MULTI_SEGS | 439 DEV_TX_OFFLOAD_TCP_TSO | 440 DEV_TX_OFFLOAD_VLAN_INSERT | 441 0; 442 443 dev_info->rx_desc_lim = rx_desc_lim; 444 dev_info->tx_desc_lim = tx_desc_lim; 445 446 /* Driver-preferred Rx/Tx parameters */ 447 dev_info->default_rxportconf.burst_size = 32; 448 dev_info->default_txportconf.burst_size = 32; 449 dev_info->default_rxportconf.nb_queues = 1; 450 dev_info->default_txportconf.nb_queues = 1; 451 dev_info->default_rxportconf.ring_size = IONIC_DEF_TXRX_DESC; 452 dev_info->default_txportconf.ring_size = IONIC_DEF_TXRX_DESC; 453 454 dev_info->default_rxconf = (struct rte_eth_rxconf) { 455 /* Packets are always dropped if no desc are available */ 456 .rx_drop_en = 1, 457 }; 458 459 return 0; 460 } 461 462 static int 463 ionic_flow_ctrl_get(struct rte_eth_dev *eth_dev, 464 struct rte_eth_fc_conf *fc_conf) 465 { 466 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 467 struct ionic_adapter *adapter = lif->adapter; 468 struct ionic_dev *idev = &adapter->idev; 469 470 if (idev->port_info) { 471 /* Flow control autoneg not supported */ 472 fc_conf->autoneg = 0; 473 474 if (idev->port_info->config.pause_type) 475 fc_conf->mode = RTE_FC_FULL; 476 else 477 fc_conf->mode = RTE_FC_NONE; 478 } 479 480 return 0; 481 } 482 483 static int 484 ionic_flow_ctrl_set(struct rte_eth_dev *eth_dev, 485 struct rte_eth_fc_conf *fc_conf) 486 { 487 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 488 struct ionic_adapter *adapter = lif->adapter; 489 struct ionic_dev *idev = &adapter->idev; 490 uint8_t pause_type = IONIC_PORT_PAUSE_TYPE_NONE; 491 int err; 492 493 if (fc_conf->autoneg) { 494 IONIC_PRINT(WARNING, "Flow control autoneg not supported"); 495 return -ENOTSUP; 496 } 497 498 switch (fc_conf->mode) { 499 case RTE_FC_NONE: 500 pause_type = IONIC_PORT_PAUSE_TYPE_NONE; 501 break; 502 case RTE_FC_FULL: 503 pause_type = IONIC_PORT_PAUSE_TYPE_LINK; 504 break; 505 case RTE_FC_RX_PAUSE: 506 case RTE_FC_TX_PAUSE: 507 return -ENOTSUP; 508 } 509 510 ionic_dev_cmd_port_pause(idev, pause_type); 511 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 512 if (err) 513 IONIC_PRINT(WARNING, "Failed to configure flow control"); 514 515 return err; 516 } 517 518 static int 519 ionic_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask) 520 { 521 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 522 523 ionic_lif_configure_vlan_offload(lif, mask); 524 525 ionic_lif_set_features(lif); 526 527 return 0; 528 } 529 530 static int 531 ionic_dev_rss_reta_update(struct rte_eth_dev *eth_dev, 532 struct rte_eth_rss_reta_entry64 *reta_conf, 533 uint16_t reta_size) 534 { 535 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 536 struct ionic_adapter *adapter = lif->adapter; 537 struct ionic_identity *ident = &adapter->ident; 538 uint32_t i, j, index, num; 539 uint16_t tbl_sz = rte_le_to_cpu_16(ident->lif.eth.rss_ind_tbl_sz); 540 541 IONIC_PRINT_CALL(); 542 543 if (!lif->rss_ind_tbl) { 544 IONIC_PRINT(ERR, "RSS RETA not initialized, " 545 "can't update the table"); 546 return -EINVAL; 547 } 548 549 if (reta_size != tbl_sz) { 550 IONIC_PRINT(ERR, "The size of hash lookup table configured " 551 "(%d) does not match the number hardware can support " 552 "(%d)", 553 reta_size, tbl_sz); 554 return -EINVAL; 555 } 556 557 num = tbl_sz / RTE_RETA_GROUP_SIZE; 558 559 for (i = 0; i < num; i++) { 560 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++) { 561 if (reta_conf[i].mask & ((uint64_t)1 << j)) { 562 index = (i * RTE_RETA_GROUP_SIZE) + j; 563 lif->rss_ind_tbl[index] = reta_conf[i].reta[j]; 564 } 565 } 566 } 567 568 return ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL); 569 } 570 571 static int 572 ionic_dev_rss_reta_query(struct rte_eth_dev *eth_dev, 573 struct rte_eth_rss_reta_entry64 *reta_conf, 574 uint16_t reta_size) 575 { 576 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 577 struct ionic_adapter *adapter = lif->adapter; 578 struct ionic_identity *ident = &adapter->ident; 579 int i, num; 580 uint16_t tbl_sz = rte_le_to_cpu_16(ident->lif.eth.rss_ind_tbl_sz); 581 582 IONIC_PRINT_CALL(); 583 584 if (reta_size != tbl_sz) { 585 IONIC_PRINT(ERR, "The size of hash lookup table configured " 586 "(%d) does not match the number hardware can support " 587 "(%d)", 588 reta_size, tbl_sz); 589 return -EINVAL; 590 } 591 592 if (!lif->rss_ind_tbl) { 593 IONIC_PRINT(ERR, "RSS RETA has not been built yet"); 594 return -EINVAL; 595 } 596 597 num = reta_size / RTE_RETA_GROUP_SIZE; 598 599 for (i = 0; i < num; i++) { 600 memcpy(reta_conf->reta, 601 &lif->rss_ind_tbl[i * RTE_RETA_GROUP_SIZE], 602 RTE_RETA_GROUP_SIZE); 603 reta_conf++; 604 } 605 606 return 0; 607 } 608 609 static int 610 ionic_dev_rss_hash_conf_get(struct rte_eth_dev *eth_dev, 611 struct rte_eth_rss_conf *rss_conf) 612 { 613 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 614 uint64_t rss_hf = 0; 615 616 IONIC_PRINT_CALL(); 617 618 if (!lif->rss_ind_tbl) { 619 IONIC_PRINT(NOTICE, "RSS not enabled"); 620 return 0; 621 } 622 623 /* Get key value (if not null, rss_key is 40-byte) */ 624 if (rss_conf->rss_key != NULL && 625 rss_conf->rss_key_len >= IONIC_RSS_HASH_KEY_SIZE) 626 memcpy(rss_conf->rss_key, lif->rss_hash_key, 627 IONIC_RSS_HASH_KEY_SIZE); 628 629 if (lif->rss_types & IONIC_RSS_TYPE_IPV4) 630 rss_hf |= ETH_RSS_IPV4; 631 if (lif->rss_types & IONIC_RSS_TYPE_IPV4_TCP) 632 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP; 633 if (lif->rss_types & IONIC_RSS_TYPE_IPV4_UDP) 634 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP; 635 if (lif->rss_types & IONIC_RSS_TYPE_IPV6) 636 rss_hf |= ETH_RSS_IPV6; 637 if (lif->rss_types & IONIC_RSS_TYPE_IPV6_TCP) 638 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP; 639 if (lif->rss_types & IONIC_RSS_TYPE_IPV6_UDP) 640 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP; 641 642 rss_conf->rss_hf = rss_hf; 643 644 return 0; 645 } 646 647 static int 648 ionic_dev_rss_hash_update(struct rte_eth_dev *eth_dev, 649 struct rte_eth_rss_conf *rss_conf) 650 { 651 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 652 uint32_t rss_types = 0; 653 uint8_t *key = NULL; 654 655 IONIC_PRINT_CALL(); 656 657 if (rss_conf->rss_key) 658 key = rss_conf->rss_key; 659 660 if ((rss_conf->rss_hf & IONIC_ETH_RSS_OFFLOAD_ALL) == 0) { 661 /* 662 * Can't disable rss through hash flags, 663 * if it is enabled by default during init 664 */ 665 if (lif->rss_ind_tbl) 666 return -EINVAL; 667 } else { 668 /* Can't enable rss if disabled by default during init */ 669 if (!lif->rss_ind_tbl) 670 return -EINVAL; 671 672 if (rss_conf->rss_hf & ETH_RSS_IPV4) 673 rss_types |= IONIC_RSS_TYPE_IPV4; 674 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) 675 rss_types |= IONIC_RSS_TYPE_IPV4_TCP; 676 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) 677 rss_types |= IONIC_RSS_TYPE_IPV4_UDP; 678 if (rss_conf->rss_hf & ETH_RSS_IPV6) 679 rss_types |= IONIC_RSS_TYPE_IPV6; 680 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) 681 rss_types |= IONIC_RSS_TYPE_IPV6_TCP; 682 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) 683 rss_types |= IONIC_RSS_TYPE_IPV6_UDP; 684 685 ionic_lif_rss_config(lif, rss_types, key, NULL); 686 } 687 688 return 0; 689 } 690 691 static int 692 ionic_dev_stats_get(struct rte_eth_dev *eth_dev, 693 struct rte_eth_stats *stats) 694 { 695 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 696 697 ionic_lif_get_stats(lif, stats); 698 699 return 0; 700 } 701 702 static int 703 ionic_dev_stats_reset(struct rte_eth_dev *eth_dev) 704 { 705 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 706 707 IONIC_PRINT_CALL(); 708 709 ionic_lif_reset_stats(lif); 710 711 return 0; 712 } 713 714 static int 715 ionic_dev_xstats_get_names(__rte_unused struct rte_eth_dev *eth_dev, 716 struct rte_eth_xstat_name *xstats_names, 717 __rte_unused unsigned int size) 718 { 719 unsigned int i; 720 721 if (xstats_names != NULL) { 722 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 723 snprintf(xstats_names[i].name, 724 sizeof(xstats_names[i].name), 725 "%s", rte_ionic_xstats_strings[i].name); 726 } 727 } 728 729 return IONIC_NB_HW_STATS; 730 } 731 732 static int 733 ionic_dev_xstats_get_names_by_id(struct rte_eth_dev *eth_dev, 734 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids, 735 unsigned int limit) 736 { 737 struct rte_eth_xstat_name xstats_names_copy[IONIC_NB_HW_STATS]; 738 uint16_t i; 739 740 if (!ids) { 741 if (xstats_names != NULL) { 742 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 743 snprintf(xstats_names[i].name, 744 sizeof(xstats_names[i].name), 745 "%s", rte_ionic_xstats_strings[i].name); 746 } 747 } 748 749 return IONIC_NB_HW_STATS; 750 } 751 752 ionic_dev_xstats_get_names_by_id(eth_dev, xstats_names_copy, NULL, 753 IONIC_NB_HW_STATS); 754 755 for (i = 0; i < limit; i++) { 756 if (ids[i] >= IONIC_NB_HW_STATS) { 757 IONIC_PRINT(ERR, "id value isn't valid"); 758 return -1; 759 } 760 761 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 762 } 763 764 return limit; 765 } 766 767 static int 768 ionic_dev_xstats_get(struct rte_eth_dev *eth_dev, struct rte_eth_xstat *xstats, 769 unsigned int n) 770 { 771 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 772 struct ionic_lif_stats hw_stats; 773 uint16_t i; 774 775 if (n < IONIC_NB_HW_STATS) 776 return IONIC_NB_HW_STATS; 777 778 ionic_lif_get_hw_stats(lif, &hw_stats); 779 780 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 781 xstats[i].value = *(uint64_t *)(((char *)&hw_stats) + 782 rte_ionic_xstats_strings[i].offset); 783 xstats[i].id = i; 784 } 785 786 return IONIC_NB_HW_STATS; 787 } 788 789 static int 790 ionic_dev_xstats_get_by_id(struct rte_eth_dev *eth_dev, const uint64_t *ids, 791 uint64_t *values, unsigned int n) 792 { 793 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 794 struct ionic_lif_stats hw_stats; 795 uint64_t values_copy[IONIC_NB_HW_STATS]; 796 uint16_t i; 797 798 if (!ids) { 799 if (!ids && n < IONIC_NB_HW_STATS) 800 return IONIC_NB_HW_STATS; 801 802 ionic_lif_get_hw_stats(lif, &hw_stats); 803 804 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 805 values[i] = *(uint64_t *)(((char *)&hw_stats) + 806 rte_ionic_xstats_strings[i].offset); 807 } 808 809 return IONIC_NB_HW_STATS; 810 } 811 812 ionic_dev_xstats_get_by_id(eth_dev, NULL, values_copy, 813 IONIC_NB_HW_STATS); 814 815 for (i = 0; i < n; i++) { 816 if (ids[i] >= IONIC_NB_HW_STATS) { 817 IONIC_PRINT(ERR, "id value isn't valid"); 818 return -1; 819 } 820 821 values[i] = values_copy[ids[i]]; 822 } 823 824 return n; 825 } 826 827 static int 828 ionic_dev_xstats_reset(struct rte_eth_dev *eth_dev) 829 { 830 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 831 832 ionic_lif_reset_hw_stats(lif); 833 834 return 0; 835 } 836 837 static int 838 ionic_dev_configure(struct rte_eth_dev *eth_dev) 839 { 840 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 841 842 IONIC_PRINT_CALL(); 843 844 ionic_lif_configure(lif); 845 846 ionic_lif_set_features(lif); 847 848 return 0; 849 } 850 851 static inline uint32_t 852 ionic_parse_link_speeds(uint16_t link_speeds) 853 { 854 if (link_speeds & ETH_LINK_SPEED_100G) 855 return 100000; 856 else if (link_speeds & ETH_LINK_SPEED_50G) 857 return 50000; 858 else if (link_speeds & ETH_LINK_SPEED_40G) 859 return 40000; 860 else if (link_speeds & ETH_LINK_SPEED_25G) 861 return 25000; 862 else if (link_speeds & ETH_LINK_SPEED_10G) 863 return 10000; 864 else 865 return 0; 866 } 867 868 /* 869 * Configure device link speed and setup link. 870 * It returns 0 on success. 871 */ 872 static int 873 ionic_dev_start(struct rte_eth_dev *eth_dev) 874 { 875 struct rte_eth_conf *dev_conf = ð_dev->data->dev_conf; 876 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 877 struct ionic_adapter *adapter = lif->adapter; 878 struct ionic_dev *idev = &adapter->idev; 879 uint32_t speed = 0, allowed_speeds; 880 uint8_t an_enable; 881 int err; 882 883 IONIC_PRINT_CALL(); 884 885 allowed_speeds = 886 ETH_LINK_SPEED_FIXED | 887 ETH_LINK_SPEED_10G | 888 ETH_LINK_SPEED_25G | 889 ETH_LINK_SPEED_40G | 890 ETH_LINK_SPEED_50G | 891 ETH_LINK_SPEED_100G; 892 893 if (dev_conf->link_speeds & ~allowed_speeds) { 894 IONIC_PRINT(ERR, "Invalid link setting"); 895 return -EINVAL; 896 } 897 898 if (dev_conf->lpbk_mode) 899 IONIC_PRINT(WARNING, "Loopback mode not supported"); 900 901 err = ionic_lif_start(lif); 902 if (err) { 903 IONIC_PRINT(ERR, "Cannot start LIF: %d", err); 904 return err; 905 } 906 907 /* Configure link */ 908 an_enable = (dev_conf->link_speeds & ETH_LINK_SPEED_FIXED) == 0; 909 910 ionic_dev_cmd_port_autoneg(idev, an_enable); 911 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 912 if (err) 913 IONIC_PRINT(WARNING, "Failed to %s autonegotiation", 914 an_enable ? "enable" : "disable"); 915 916 if (!an_enable) 917 speed = ionic_parse_link_speeds(dev_conf->link_speeds); 918 if (speed) { 919 ionic_dev_cmd_port_speed(idev, speed); 920 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 921 if (err) 922 IONIC_PRINT(WARNING, "Failed to set link speed %u", 923 speed); 924 } 925 926 ionic_dev_link_update(eth_dev, 0); 927 928 return 0; 929 } 930 931 /* 932 * Stop device: disable rx and tx functions to allow for reconfiguring. 933 */ 934 static int 935 ionic_dev_stop(struct rte_eth_dev *eth_dev) 936 { 937 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 938 939 IONIC_PRINT_CALL(); 940 941 ionic_lif_stop(lif); 942 943 return 0; 944 } 945 946 static void ionic_unconfigure_intr(struct ionic_adapter *adapter); 947 948 /* 949 * Reset and stop device. 950 */ 951 static int 952 ionic_dev_close(struct rte_eth_dev *eth_dev) 953 { 954 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 955 struct ionic_adapter *adapter = lif->adapter; 956 957 IONIC_PRINT_CALL(); 958 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 959 return 0; 960 961 ionic_lif_stop(lif); 962 963 ionic_lif_free_queues(lif); 964 965 IONIC_PRINT(NOTICE, "Removing device %s", eth_dev->device->name); 966 ionic_unconfigure_intr(adapter); 967 968 rte_eth_dev_destroy(eth_dev, eth_ionic_dev_uninit); 969 970 ionic_port_reset(adapter); 971 ionic_reset(adapter); 972 973 rte_free(adapter); 974 975 return 0; 976 } 977 978 static int 979 eth_ionic_dev_init(struct rte_eth_dev *eth_dev, void *init_params) 980 { 981 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 982 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 983 struct ionic_adapter *adapter = (struct ionic_adapter *)init_params; 984 int err; 985 986 IONIC_PRINT_CALL(); 987 988 eth_dev->dev_ops = &ionic_eth_dev_ops; 989 eth_dev->rx_pkt_burst = &ionic_recv_pkts; 990 eth_dev->tx_pkt_burst = &ionic_xmit_pkts; 991 eth_dev->tx_pkt_prepare = &ionic_prep_pkts; 992 993 /* Multi-process not supported, primary does initialization anyway */ 994 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 995 return 0; 996 997 rte_eth_copy_pci_info(eth_dev, pci_dev); 998 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 999 1000 lif->eth_dev = eth_dev; 1001 lif->adapter = adapter; 1002 adapter->lif = lif; 1003 1004 IONIC_PRINT(DEBUG, "Up to %u MAC addresses supported", 1005 adapter->max_mac_addrs); 1006 1007 /* Allocate memory for storing MAC addresses */ 1008 eth_dev->data->mac_addrs = rte_zmalloc("ionic", 1009 RTE_ETHER_ADDR_LEN * adapter->max_mac_addrs, 0); 1010 1011 if (eth_dev->data->mac_addrs == NULL) { 1012 IONIC_PRINT(ERR, "Failed to allocate %u bytes needed to " 1013 "store MAC addresses", 1014 RTE_ETHER_ADDR_LEN * adapter->max_mac_addrs); 1015 err = -ENOMEM; 1016 goto err; 1017 } 1018 1019 err = ionic_lif_alloc(lif); 1020 if (err) { 1021 IONIC_PRINT(ERR, "Cannot allocate LIFs: %d, aborting", 1022 err); 1023 goto err; 1024 } 1025 1026 err = ionic_lif_init(lif); 1027 if (err) { 1028 IONIC_PRINT(ERR, "Cannot init LIFs: %d, aborting", err); 1029 goto err_free_lif; 1030 } 1031 1032 /* Copy the MAC address */ 1033 rte_ether_addr_copy((struct rte_ether_addr *)lif->mac_addr, 1034 ð_dev->data->mac_addrs[0]); 1035 1036 IONIC_PRINT(DEBUG, "Port %u initialized", eth_dev->data->port_id); 1037 1038 return 0; 1039 1040 err_free_lif: 1041 ionic_lif_free(lif); 1042 err: 1043 return err; 1044 } 1045 1046 static int 1047 eth_ionic_dev_uninit(struct rte_eth_dev *eth_dev) 1048 { 1049 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 1050 struct ionic_adapter *adapter = lif->adapter; 1051 1052 IONIC_PRINT_CALL(); 1053 1054 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1055 return 0; 1056 1057 adapter->lif = NULL; 1058 1059 ionic_lif_deinit(lif); 1060 ionic_lif_free(lif); 1061 1062 if (!(lif->state & IONIC_LIF_F_FW_RESET)) 1063 ionic_lif_reset(lif); 1064 1065 return 0; 1066 } 1067 1068 static int 1069 ionic_configure_intr(struct ionic_adapter *adapter) 1070 { 1071 struct rte_pci_device *pci_dev = adapter->pci_dev; 1072 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1073 int err; 1074 1075 IONIC_PRINT(DEBUG, "Configuring %u intrs", adapter->nintrs); 1076 1077 if (rte_intr_efd_enable(intr_handle, adapter->nintrs)) { 1078 IONIC_PRINT(ERR, "Fail to create eventfd"); 1079 return -1; 1080 } 1081 1082 if (rte_intr_dp_is_en(intr_handle)) 1083 IONIC_PRINT(DEBUG, 1084 "Packet I/O interrupt on datapath is enabled"); 1085 1086 if (!intr_handle->intr_vec) { 1087 intr_handle->intr_vec = rte_zmalloc("intr_vec", 1088 adapter->nintrs * sizeof(int), 0); 1089 1090 if (!intr_handle->intr_vec) { 1091 IONIC_PRINT(ERR, "Failed to allocate %u vectors", 1092 adapter->nintrs); 1093 return -ENOMEM; 1094 } 1095 } 1096 1097 err = rte_intr_callback_register(intr_handle, 1098 ionic_dev_interrupt_handler, 1099 adapter); 1100 1101 if (err) { 1102 IONIC_PRINT(ERR, 1103 "Failure registering interrupts handler (%d)", 1104 err); 1105 return err; 1106 } 1107 1108 /* enable intr mapping */ 1109 err = rte_intr_enable(intr_handle); 1110 1111 if (err) { 1112 IONIC_PRINT(ERR, "Failure enabling interrupts (%d)", err); 1113 return err; 1114 } 1115 1116 return 0; 1117 } 1118 1119 static void 1120 ionic_unconfigure_intr(struct ionic_adapter *adapter) 1121 { 1122 struct rte_pci_device *pci_dev = adapter->pci_dev; 1123 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1124 1125 rte_intr_disable(intr_handle); 1126 1127 rte_intr_callback_unregister(intr_handle, 1128 ionic_dev_interrupt_handler, 1129 adapter); 1130 } 1131 1132 static int 1133 eth_ionic_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1134 struct rte_pci_device *pci_dev) 1135 { 1136 char name[RTE_ETH_NAME_MAX_LEN]; 1137 struct rte_mem_resource *resource; 1138 struct ionic_adapter *adapter; 1139 struct ionic_hw *hw; 1140 unsigned long i; 1141 int err; 1142 1143 /* Check structs (trigger error at compilation time) */ 1144 ionic_struct_size_checks(); 1145 1146 /* Multi-process not supported */ 1147 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1148 err = -EPERM; 1149 goto err; 1150 } 1151 1152 IONIC_PRINT(DEBUG, "Initializing device %s", 1153 pci_dev->device.name); 1154 1155 adapter = rte_zmalloc("ionic", sizeof(*adapter), 0); 1156 if (!adapter) { 1157 IONIC_PRINT(ERR, "OOM"); 1158 err = -ENOMEM; 1159 goto err; 1160 } 1161 1162 adapter->pci_dev = pci_dev; 1163 hw = &adapter->hw; 1164 1165 hw->device_id = pci_dev->id.device_id; 1166 hw->vendor_id = pci_dev->id.vendor_id; 1167 1168 err = ionic_init_mac(hw); 1169 if (err != 0) { 1170 IONIC_PRINT(ERR, "Mac init failed: %d", err); 1171 err = -EIO; 1172 goto err_free_adapter; 1173 } 1174 1175 adapter->num_bars = 0; 1176 for (i = 0; i < PCI_MAX_RESOURCE && i < IONIC_BARS_MAX; i++) { 1177 resource = &pci_dev->mem_resource[i]; 1178 if (resource->phys_addr == 0 || resource->len == 0) 1179 continue; 1180 adapter->bars[adapter->num_bars].vaddr = resource->addr; 1181 adapter->bars[adapter->num_bars].bus_addr = resource->phys_addr; 1182 adapter->bars[adapter->num_bars].len = resource->len; 1183 adapter->num_bars++; 1184 } 1185 1186 /* Discover ionic dev resources */ 1187 1188 err = ionic_setup(adapter); 1189 if (err) { 1190 IONIC_PRINT(ERR, "Cannot setup device: %d, aborting", err); 1191 goto err_free_adapter; 1192 } 1193 1194 err = ionic_identify(adapter); 1195 if (err) { 1196 IONIC_PRINT(ERR, "Cannot identify device: %d, aborting", 1197 err); 1198 goto err_free_adapter; 1199 } 1200 1201 err = ionic_init(adapter); 1202 if (err) { 1203 IONIC_PRINT(ERR, "Cannot init device: %d, aborting", err); 1204 goto err_free_adapter; 1205 } 1206 1207 /* Configure the ports */ 1208 err = ionic_port_identify(adapter); 1209 if (err) { 1210 IONIC_PRINT(ERR, "Cannot identify port: %d, aborting", 1211 err); 1212 goto err_free_adapter; 1213 } 1214 1215 err = ionic_port_init(adapter); 1216 if (err) { 1217 IONIC_PRINT(ERR, "Cannot init port: %d, aborting", err); 1218 goto err_free_adapter; 1219 } 1220 1221 /* Configure LIFs */ 1222 err = ionic_lif_identify(adapter); 1223 if (err) { 1224 IONIC_PRINT(ERR, "Cannot identify lif: %d, aborting", err); 1225 goto err_free_adapter; 1226 } 1227 1228 /* Allocate and init LIFs */ 1229 err = ionic_lifs_size(adapter); 1230 if (err) { 1231 IONIC_PRINT(ERR, "Cannot size LIFs: %d, aborting", err); 1232 goto err_free_adapter; 1233 } 1234 1235 adapter->max_mac_addrs = 1236 rte_le_to_cpu_32(adapter->ident.lif.eth.max_ucast_filters); 1237 1238 if (rte_le_to_cpu_32(adapter->ident.dev.nlifs) != 1) { 1239 IONIC_PRINT(ERR, "Unexpected request for %d LIFs", 1240 rte_le_to_cpu_32(adapter->ident.dev.nlifs)); 1241 goto err_free_adapter; 1242 } 1243 1244 snprintf(name, sizeof(name), "%s_lif", pci_dev->device.name); 1245 err = rte_eth_dev_create(&pci_dev->device, 1246 name, sizeof(struct ionic_lif), 1247 NULL, NULL, eth_ionic_dev_init, adapter); 1248 if (err) { 1249 IONIC_PRINT(ERR, "Cannot create eth device for %s", name); 1250 goto err_free_adapter; 1251 } 1252 1253 err = ionic_configure_intr(adapter); 1254 1255 if (err) { 1256 IONIC_PRINT(ERR, "Failed to configure interrupts"); 1257 goto err_free_adapter; 1258 } 1259 1260 return 0; 1261 1262 err_free_adapter: 1263 rte_free(adapter); 1264 err: 1265 return err; 1266 } 1267 1268 static int 1269 eth_ionic_pci_remove(struct rte_pci_device *pci_dev) 1270 { 1271 char name[RTE_ETH_NAME_MAX_LEN]; 1272 struct rte_eth_dev *eth_dev; 1273 1274 /* Adapter lookup is using the eth_dev name */ 1275 snprintf(name, sizeof(name), "%s_lif", pci_dev->device.name); 1276 1277 eth_dev = rte_eth_dev_allocated(name); 1278 if (eth_dev) 1279 ionic_dev_close(eth_dev); 1280 else 1281 IONIC_PRINT(DEBUG, "Cannot find device %s", 1282 pci_dev->device.name); 1283 1284 return 0; 1285 } 1286 1287 static struct rte_pci_driver rte_ionic_pmd = { 1288 .id_table = pci_id_ionic_map, 1289 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 1290 .probe = eth_ionic_pci_probe, 1291 .remove = eth_ionic_pci_remove, 1292 }; 1293 1294 RTE_PMD_REGISTER_PCI(net_ionic, rte_ionic_pmd); 1295 RTE_PMD_REGISTER_PCI_TABLE(net_ionic, pci_id_ionic_map); 1296 RTE_PMD_REGISTER_KMOD_DEP(net_ionic, "* igb_uio | uio_pci_generic | vfio-pci"); 1297 RTE_LOG_REGISTER(ionic_logtype, pmd.net.ionic, NOTICE); 1298