1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) 2 * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved. 3 */ 4 5 #include <rte_pci.h> 6 #include <rte_bus_pci.h> 7 #include <rte_ethdev.h> 8 #include <ethdev_driver.h> 9 #include <rte_malloc.h> 10 #include <ethdev_pci.h> 11 12 #include "ionic_logs.h" 13 #include "ionic.h" 14 #include "ionic_dev.h" 15 #include "ionic_mac_api.h" 16 #include "ionic_lif.h" 17 #include "ionic_ethdev.h" 18 #include "ionic_rxtx.h" 19 20 static int eth_ionic_dev_init(struct rte_eth_dev *eth_dev, void *init_params); 21 static int eth_ionic_dev_uninit(struct rte_eth_dev *eth_dev); 22 static int ionic_dev_info_get(struct rte_eth_dev *eth_dev, 23 struct rte_eth_dev_info *dev_info); 24 static int ionic_dev_configure(struct rte_eth_dev *dev); 25 static int ionic_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 26 static int ionic_dev_start(struct rte_eth_dev *dev); 27 static int ionic_dev_stop(struct rte_eth_dev *dev); 28 static int ionic_dev_close(struct rte_eth_dev *dev); 29 static int ionic_dev_set_link_up(struct rte_eth_dev *dev); 30 static int ionic_dev_set_link_down(struct rte_eth_dev *dev); 31 static int ionic_flow_ctrl_get(struct rte_eth_dev *eth_dev, 32 struct rte_eth_fc_conf *fc_conf); 33 static int ionic_flow_ctrl_set(struct rte_eth_dev *eth_dev, 34 struct rte_eth_fc_conf *fc_conf); 35 static int ionic_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask); 36 static int ionic_dev_rss_reta_update(struct rte_eth_dev *eth_dev, 37 struct rte_eth_rss_reta_entry64 *reta_conf, uint16_t reta_size); 38 static int ionic_dev_rss_reta_query(struct rte_eth_dev *eth_dev, 39 struct rte_eth_rss_reta_entry64 *reta_conf, uint16_t reta_size); 40 static int ionic_dev_rss_hash_conf_get(struct rte_eth_dev *eth_dev, 41 struct rte_eth_rss_conf *rss_conf); 42 static int ionic_dev_rss_hash_update(struct rte_eth_dev *eth_dev, 43 struct rte_eth_rss_conf *rss_conf); 44 static int ionic_dev_stats_get(struct rte_eth_dev *eth_dev, 45 struct rte_eth_stats *stats); 46 static int ionic_dev_stats_reset(struct rte_eth_dev *eth_dev); 47 static int ionic_dev_xstats_get(struct rte_eth_dev *dev, 48 struct rte_eth_xstat *xstats, unsigned int n); 49 static int ionic_dev_xstats_get_by_id(struct rte_eth_dev *dev, 50 const uint64_t *ids, uint64_t *values, unsigned int n); 51 static int ionic_dev_xstats_reset(struct rte_eth_dev *dev); 52 static int ionic_dev_xstats_get_names(struct rte_eth_dev *dev, 53 struct rte_eth_xstat_name *xstats_names, unsigned int size); 54 static int ionic_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, 55 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids, 56 unsigned int limit); 57 static int ionic_dev_fw_version_get(struct rte_eth_dev *eth_dev, 58 char *fw_version, size_t fw_size); 59 60 static const struct rte_pci_id pci_id_ionic_map[] = { 61 { RTE_PCI_DEVICE(IONIC_PENSANDO_VENDOR_ID, IONIC_DEV_ID_ETH_PF) }, 62 { RTE_PCI_DEVICE(IONIC_PENSANDO_VENDOR_ID, IONIC_DEV_ID_ETH_VF) }, 63 { RTE_PCI_DEVICE(IONIC_PENSANDO_VENDOR_ID, IONIC_DEV_ID_ETH_MGMT) }, 64 { .vendor_id = 0, /* sentinel */ }, 65 }; 66 67 static const struct rte_eth_desc_lim rx_desc_lim = { 68 .nb_max = IONIC_MAX_RING_DESC, 69 .nb_min = IONIC_MIN_RING_DESC, 70 .nb_align = 1, 71 }; 72 73 static const struct rte_eth_desc_lim tx_desc_lim_v1 = { 74 .nb_max = IONIC_MAX_RING_DESC, 75 .nb_min = IONIC_MIN_RING_DESC, 76 .nb_align = 1, 77 .nb_seg_max = IONIC_TX_MAX_SG_ELEMS_V1 + 1, 78 .nb_mtu_seg_max = IONIC_TX_MAX_SG_ELEMS_V1 + 1, 79 }; 80 81 static const struct eth_dev_ops ionic_eth_dev_ops = { 82 .dev_infos_get = ionic_dev_info_get, 83 .dev_configure = ionic_dev_configure, 84 .mtu_set = ionic_dev_mtu_set, 85 .dev_start = ionic_dev_start, 86 .dev_stop = ionic_dev_stop, 87 .dev_close = ionic_dev_close, 88 .link_update = ionic_dev_link_update, 89 .dev_set_link_up = ionic_dev_set_link_up, 90 .dev_set_link_down = ionic_dev_set_link_down, 91 .mac_addr_add = ionic_dev_add_mac, 92 .mac_addr_remove = ionic_dev_remove_mac, 93 .mac_addr_set = ionic_dev_set_mac, 94 .vlan_filter_set = ionic_dev_vlan_filter_set, 95 .promiscuous_enable = ionic_dev_promiscuous_enable, 96 .promiscuous_disable = ionic_dev_promiscuous_disable, 97 .allmulticast_enable = ionic_dev_allmulticast_enable, 98 .allmulticast_disable = ionic_dev_allmulticast_disable, 99 .flow_ctrl_get = ionic_flow_ctrl_get, 100 .flow_ctrl_set = ionic_flow_ctrl_set, 101 .rxq_info_get = ionic_rxq_info_get, 102 .txq_info_get = ionic_txq_info_get, 103 .rx_queue_setup = ionic_dev_rx_queue_setup, 104 .rx_queue_release = ionic_dev_rx_queue_release, 105 .rx_queue_start = ionic_dev_rx_queue_start, 106 .rx_queue_stop = ionic_dev_rx_queue_stop, 107 .tx_queue_setup = ionic_dev_tx_queue_setup, 108 .tx_queue_release = ionic_dev_tx_queue_release, 109 .tx_queue_start = ionic_dev_tx_queue_start, 110 .tx_queue_stop = ionic_dev_tx_queue_stop, 111 .vlan_offload_set = ionic_vlan_offload_set, 112 .reta_update = ionic_dev_rss_reta_update, 113 .reta_query = ionic_dev_rss_reta_query, 114 .rss_hash_conf_get = ionic_dev_rss_hash_conf_get, 115 .rss_hash_update = ionic_dev_rss_hash_update, 116 .stats_get = ionic_dev_stats_get, 117 .stats_reset = ionic_dev_stats_reset, 118 .xstats_get = ionic_dev_xstats_get, 119 .xstats_get_by_id = ionic_dev_xstats_get_by_id, 120 .xstats_reset = ionic_dev_xstats_reset, 121 .xstats_get_names = ionic_dev_xstats_get_names, 122 .xstats_get_names_by_id = ionic_dev_xstats_get_names_by_id, 123 .fw_version_get = ionic_dev_fw_version_get, 124 }; 125 126 struct rte_ionic_xstats_name_off { 127 char name[RTE_ETH_XSTATS_NAME_SIZE]; 128 unsigned int offset; 129 }; 130 131 static const struct rte_ionic_xstats_name_off rte_ionic_xstats_strings[] = { 132 /* RX */ 133 {"rx_ucast_bytes", offsetof(struct ionic_lif_stats, 134 rx_ucast_bytes)}, 135 {"rx_ucast_packets", offsetof(struct ionic_lif_stats, 136 rx_ucast_packets)}, 137 {"rx_mcast_bytes", offsetof(struct ionic_lif_stats, 138 rx_mcast_bytes)}, 139 {"rx_mcast_packets", offsetof(struct ionic_lif_stats, 140 rx_mcast_packets)}, 141 {"rx_bcast_bytes", offsetof(struct ionic_lif_stats, 142 rx_bcast_bytes)}, 143 {"rx_bcast_packets", offsetof(struct ionic_lif_stats, 144 rx_bcast_packets)}, 145 /* RX drops */ 146 {"rx_ucast_drop_bytes", offsetof(struct ionic_lif_stats, 147 rx_ucast_drop_bytes)}, 148 {"rx_ucast_drop_packets", offsetof(struct ionic_lif_stats, 149 rx_ucast_drop_packets)}, 150 {"rx_mcast_drop_bytes", offsetof(struct ionic_lif_stats, 151 rx_mcast_drop_bytes)}, 152 {"rx_mcast_drop_packets", offsetof(struct ionic_lif_stats, 153 rx_mcast_drop_packets)}, 154 {"rx_bcast_drop_bytes", offsetof(struct ionic_lif_stats, 155 rx_bcast_drop_bytes)}, 156 {"rx_bcast_drop_packets", offsetof(struct ionic_lif_stats, 157 rx_bcast_drop_packets)}, 158 {"rx_dma_error", offsetof(struct ionic_lif_stats, 159 rx_dma_error)}, 160 /* TX */ 161 {"tx_ucast_bytes", offsetof(struct ionic_lif_stats, 162 tx_ucast_bytes)}, 163 {"tx_ucast_packets", offsetof(struct ionic_lif_stats, 164 tx_ucast_packets)}, 165 {"tx_mcast_bytes", offsetof(struct ionic_lif_stats, 166 tx_mcast_bytes)}, 167 {"tx_mcast_packets", offsetof(struct ionic_lif_stats, 168 tx_mcast_packets)}, 169 {"tx_bcast_bytes", offsetof(struct ionic_lif_stats, 170 tx_bcast_bytes)}, 171 {"tx_bcast_packets", offsetof(struct ionic_lif_stats, 172 tx_bcast_packets)}, 173 /* TX drops */ 174 {"tx_ucast_drop_bytes", offsetof(struct ionic_lif_stats, 175 tx_ucast_drop_bytes)}, 176 {"tx_ucast_drop_packets", offsetof(struct ionic_lif_stats, 177 tx_ucast_drop_packets)}, 178 {"tx_mcast_drop_bytes", offsetof(struct ionic_lif_stats, 179 tx_mcast_drop_bytes)}, 180 {"tx_mcast_drop_packets", offsetof(struct ionic_lif_stats, 181 tx_mcast_drop_packets)}, 182 {"tx_bcast_drop_bytes", offsetof(struct ionic_lif_stats, 183 tx_bcast_drop_bytes)}, 184 {"tx_bcast_drop_packets", offsetof(struct ionic_lif_stats, 185 tx_bcast_drop_packets)}, 186 {"tx_dma_error", offsetof(struct ionic_lif_stats, 187 tx_dma_error)}, 188 /* Rx Queue/Ring drops */ 189 {"rx_queue_disabled", offsetof(struct ionic_lif_stats, 190 rx_queue_disabled)}, 191 {"rx_queue_empty", offsetof(struct ionic_lif_stats, 192 rx_queue_empty)}, 193 {"rx_queue_error", offsetof(struct ionic_lif_stats, 194 rx_queue_error)}, 195 {"rx_desc_fetch_error", offsetof(struct ionic_lif_stats, 196 rx_desc_fetch_error)}, 197 {"rx_desc_data_error", offsetof(struct ionic_lif_stats, 198 rx_desc_data_error)}, 199 /* Tx Queue/Ring drops */ 200 {"tx_queue_disabled", offsetof(struct ionic_lif_stats, 201 tx_queue_disabled)}, 202 {"tx_queue_error", offsetof(struct ionic_lif_stats, 203 tx_queue_error)}, 204 {"tx_desc_fetch_error", offsetof(struct ionic_lif_stats, 205 tx_desc_fetch_error)}, 206 {"tx_desc_data_error", offsetof(struct ionic_lif_stats, 207 tx_desc_data_error)}, 208 }; 209 210 #define IONIC_NB_HW_STATS RTE_DIM(rte_ionic_xstats_strings) 211 212 static int 213 ionic_dev_fw_version_get(struct rte_eth_dev *eth_dev, 214 char *fw_version, size_t fw_size) 215 { 216 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 217 struct ionic_adapter *adapter = lif->adapter; 218 219 if (fw_version == NULL || fw_size <= 0) 220 return -EINVAL; 221 222 snprintf(fw_version, fw_size, "%s", 223 adapter->fw_version); 224 fw_version[fw_size - 1] = '\0'; 225 226 return 0; 227 } 228 229 /* 230 * Set device link up, enable tx. 231 */ 232 static int 233 ionic_dev_set_link_up(struct rte_eth_dev *eth_dev) 234 { 235 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 236 int err; 237 238 IONIC_PRINT_CALL(); 239 240 err = ionic_lif_start(lif); 241 if (err) 242 IONIC_PRINT(ERR, "Could not start lif to set link up"); 243 244 ionic_dev_link_update(lif->eth_dev, 0); 245 246 return err; 247 } 248 249 /* 250 * Set device link down, disable tx. 251 */ 252 static int 253 ionic_dev_set_link_down(struct rte_eth_dev *eth_dev) 254 { 255 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 256 257 IONIC_PRINT_CALL(); 258 259 ionic_lif_stop(lif); 260 261 ionic_dev_link_update(lif->eth_dev, 0); 262 263 return 0; 264 } 265 266 int 267 ionic_dev_link_update(struct rte_eth_dev *eth_dev, 268 int wait_to_complete __rte_unused) 269 { 270 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 271 struct ionic_adapter *adapter = lif->adapter; 272 struct rte_eth_link link; 273 274 IONIC_PRINT_CALL(); 275 276 /* Initialize */ 277 memset(&link, 0, sizeof(link)); 278 279 if (adapter->idev.port_info->config.an_enable) { 280 link.link_autoneg = ETH_LINK_AUTONEG; 281 } 282 283 if (!adapter->link_up || 284 !(lif->state & IONIC_LIF_F_UP)) { 285 /* Interface is down */ 286 link.link_status = ETH_LINK_DOWN; 287 link.link_duplex = ETH_LINK_HALF_DUPLEX; 288 link.link_speed = ETH_SPEED_NUM_NONE; 289 } else { 290 /* Interface is up */ 291 link.link_status = ETH_LINK_UP; 292 link.link_duplex = ETH_LINK_FULL_DUPLEX; 293 switch (adapter->link_speed) { 294 case 10000: 295 link.link_speed = ETH_SPEED_NUM_10G; 296 break; 297 case 25000: 298 link.link_speed = ETH_SPEED_NUM_25G; 299 break; 300 case 40000: 301 link.link_speed = ETH_SPEED_NUM_40G; 302 break; 303 case 50000: 304 link.link_speed = ETH_SPEED_NUM_50G; 305 break; 306 case 100000: 307 link.link_speed = ETH_SPEED_NUM_100G; 308 break; 309 default: 310 link.link_speed = ETH_SPEED_NUM_NONE; 311 break; 312 } 313 } 314 315 return rte_eth_linkstatus_set(eth_dev, &link); 316 } 317 318 /** 319 * Interrupt handler triggered by NIC for handling 320 * specific interrupt. 321 * 322 * @param param 323 * The address of parameter registered before. 324 * 325 * @return 326 * void 327 */ 328 static void 329 ionic_dev_interrupt_handler(void *param) 330 { 331 struct ionic_adapter *adapter = (struct ionic_adapter *)param; 332 333 IONIC_PRINT(DEBUG, "->"); 334 335 if (adapter->lif) 336 ionic_notifyq_handler(adapter->lif, -1); 337 } 338 339 static int 340 ionic_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) 341 { 342 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 343 uint32_t max_frame_size; 344 int err; 345 346 IONIC_PRINT_CALL(); 347 348 /* 349 * Note: mtu check against IONIC_MIN_MTU, IONIC_MAX_MTU 350 * is done by the the API. 351 */ 352 353 /* 354 * Max frame size is MTU + Ethernet header + VLAN + QinQ 355 * (plus ETHER_CRC_LEN if the adapter is able to keep CRC) 356 */ 357 max_frame_size = mtu + RTE_ETHER_HDR_LEN + 4 + 4; 358 359 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len < max_frame_size) 360 return -EINVAL; 361 362 err = ionic_lif_change_mtu(lif, mtu); 363 if (err) 364 return err; 365 366 return 0; 367 } 368 369 static int 370 ionic_dev_info_get(struct rte_eth_dev *eth_dev, 371 struct rte_eth_dev_info *dev_info) 372 { 373 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 374 struct ionic_adapter *adapter = lif->adapter; 375 struct ionic_identity *ident = &adapter->ident; 376 union ionic_lif_config *cfg = &ident->lif.eth.config; 377 378 IONIC_PRINT_CALL(); 379 380 dev_info->max_rx_queues = (uint16_t) 381 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_RXQ]); 382 dev_info->max_tx_queues = (uint16_t) 383 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ]); 384 385 /* Also add ETHER_CRC_LEN if the adapter is able to keep CRC */ 386 dev_info->min_rx_bufsize = IONIC_MIN_MTU + RTE_ETHER_HDR_LEN; 387 dev_info->max_rx_pktlen = IONIC_MAX_MTU + RTE_ETHER_HDR_LEN; 388 dev_info->max_mac_addrs = adapter->max_mac_addrs; 389 dev_info->min_mtu = IONIC_MIN_MTU; 390 dev_info->max_mtu = IONIC_MAX_MTU; 391 392 dev_info->hash_key_size = IONIC_RSS_HASH_KEY_SIZE; 393 dev_info->reta_size = rte_le_to_cpu_16(ident->lif.eth.rss_ind_tbl_sz); 394 dev_info->flow_type_rss_offloads = IONIC_ETH_RSS_OFFLOAD_ALL; 395 396 dev_info->speed_capa = 397 ETH_LINK_SPEED_10G | 398 ETH_LINK_SPEED_25G | 399 ETH_LINK_SPEED_40G | 400 ETH_LINK_SPEED_50G | 401 ETH_LINK_SPEED_100G; 402 403 /* 404 * Per-queue capabilities 405 * RTE does not support disabling a feature on a queue if it is 406 * enabled globally on the device. Thus the driver does not advertise 407 * capabilities like DEV_TX_OFFLOAD_IPV4_CKSUM as per-queue even 408 * though the driver would be otherwise capable of disabling it on 409 * a per-queue basis. 410 */ 411 412 dev_info->rx_queue_offload_capa = 0; 413 dev_info->tx_queue_offload_capa = 0; 414 415 /* 416 * Per-port capabilities 417 * See ionic_set_features to request and check supported features 418 */ 419 420 dev_info->rx_offload_capa = dev_info->rx_queue_offload_capa | 421 DEV_RX_OFFLOAD_IPV4_CKSUM | 422 DEV_RX_OFFLOAD_UDP_CKSUM | 423 DEV_RX_OFFLOAD_TCP_CKSUM | 424 DEV_RX_OFFLOAD_JUMBO_FRAME | 425 DEV_RX_OFFLOAD_VLAN_FILTER | 426 DEV_RX_OFFLOAD_VLAN_STRIP | 427 DEV_RX_OFFLOAD_SCATTER | 428 DEV_RX_OFFLOAD_RSS_HASH | 429 0; 430 431 dev_info->tx_offload_capa = dev_info->tx_queue_offload_capa | 432 DEV_TX_OFFLOAD_IPV4_CKSUM | 433 DEV_TX_OFFLOAD_UDP_CKSUM | 434 DEV_TX_OFFLOAD_TCP_CKSUM | 435 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 436 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM | 437 DEV_TX_OFFLOAD_MULTI_SEGS | 438 DEV_TX_OFFLOAD_TCP_TSO | 439 DEV_TX_OFFLOAD_VLAN_INSERT | 440 0; 441 442 dev_info->rx_desc_lim = rx_desc_lim; 443 dev_info->tx_desc_lim = tx_desc_lim_v1; 444 445 /* Driver-preferred Rx/Tx parameters */ 446 dev_info->default_rxportconf.burst_size = 32; 447 dev_info->default_txportconf.burst_size = 32; 448 dev_info->default_rxportconf.nb_queues = 1; 449 dev_info->default_txportconf.nb_queues = 1; 450 dev_info->default_rxportconf.ring_size = IONIC_DEF_TXRX_DESC; 451 dev_info->default_txportconf.ring_size = IONIC_DEF_TXRX_DESC; 452 453 dev_info->default_rxconf = (struct rte_eth_rxconf) { 454 /* Packets are always dropped if no desc are available */ 455 .rx_drop_en = 1, 456 }; 457 458 return 0; 459 } 460 461 static int 462 ionic_flow_ctrl_get(struct rte_eth_dev *eth_dev, 463 struct rte_eth_fc_conf *fc_conf) 464 { 465 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 466 struct ionic_adapter *adapter = lif->adapter; 467 struct ionic_dev *idev = &adapter->idev; 468 469 if (idev->port_info) { 470 /* Flow control autoneg not supported */ 471 fc_conf->autoneg = 0; 472 473 if (idev->port_info->config.pause_type) 474 fc_conf->mode = RTE_FC_FULL; 475 else 476 fc_conf->mode = RTE_FC_NONE; 477 } 478 479 return 0; 480 } 481 482 static int 483 ionic_flow_ctrl_set(struct rte_eth_dev *eth_dev, 484 struct rte_eth_fc_conf *fc_conf) 485 { 486 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 487 struct ionic_adapter *adapter = lif->adapter; 488 struct ionic_dev *idev = &adapter->idev; 489 uint8_t pause_type = IONIC_PORT_PAUSE_TYPE_NONE; 490 int err; 491 492 if (fc_conf->autoneg) { 493 IONIC_PRINT(WARNING, "Flow control autoneg not supported"); 494 return -ENOTSUP; 495 } 496 497 switch (fc_conf->mode) { 498 case RTE_FC_NONE: 499 pause_type = IONIC_PORT_PAUSE_TYPE_NONE; 500 break; 501 case RTE_FC_FULL: 502 pause_type = IONIC_PORT_PAUSE_TYPE_LINK; 503 break; 504 case RTE_FC_RX_PAUSE: 505 case RTE_FC_TX_PAUSE: 506 return -ENOTSUP; 507 } 508 509 ionic_dev_cmd_port_pause(idev, pause_type); 510 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 511 if (err) 512 IONIC_PRINT(WARNING, "Failed to configure flow control"); 513 514 return err; 515 } 516 517 static int 518 ionic_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask) 519 { 520 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 521 522 ionic_lif_configure_vlan_offload(lif, mask); 523 524 ionic_lif_set_features(lif); 525 526 return 0; 527 } 528 529 static int 530 ionic_dev_rss_reta_update(struct rte_eth_dev *eth_dev, 531 struct rte_eth_rss_reta_entry64 *reta_conf, 532 uint16_t reta_size) 533 { 534 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 535 struct ionic_adapter *adapter = lif->adapter; 536 struct ionic_identity *ident = &adapter->ident; 537 uint32_t i, j, index, num; 538 uint16_t tbl_sz = rte_le_to_cpu_16(ident->lif.eth.rss_ind_tbl_sz); 539 540 IONIC_PRINT_CALL(); 541 542 if (!lif->rss_ind_tbl) { 543 IONIC_PRINT(ERR, "RSS RETA not initialized, " 544 "can't update the table"); 545 return -EINVAL; 546 } 547 548 if (reta_size != tbl_sz) { 549 IONIC_PRINT(ERR, "The size of hash lookup table configured " 550 "(%d) does not match the number hardware can support " 551 "(%d)", 552 reta_size, tbl_sz); 553 return -EINVAL; 554 } 555 556 num = tbl_sz / RTE_RETA_GROUP_SIZE; 557 558 for (i = 0; i < num; i++) { 559 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++) { 560 if (reta_conf[i].mask & ((uint64_t)1 << j)) { 561 index = (i * RTE_RETA_GROUP_SIZE) + j; 562 lif->rss_ind_tbl[index] = reta_conf[i].reta[j]; 563 } 564 } 565 } 566 567 return ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL); 568 } 569 570 static int 571 ionic_dev_rss_reta_query(struct rte_eth_dev *eth_dev, 572 struct rte_eth_rss_reta_entry64 *reta_conf, 573 uint16_t reta_size) 574 { 575 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 576 struct ionic_adapter *adapter = lif->adapter; 577 struct ionic_identity *ident = &adapter->ident; 578 int i, num; 579 uint16_t tbl_sz = rte_le_to_cpu_16(ident->lif.eth.rss_ind_tbl_sz); 580 581 IONIC_PRINT_CALL(); 582 583 if (reta_size != tbl_sz) { 584 IONIC_PRINT(ERR, "The size of hash lookup table configured " 585 "(%d) does not match the number hardware can support " 586 "(%d)", 587 reta_size, tbl_sz); 588 return -EINVAL; 589 } 590 591 if (!lif->rss_ind_tbl) { 592 IONIC_PRINT(ERR, "RSS RETA has not been built yet"); 593 return -EINVAL; 594 } 595 596 num = reta_size / RTE_RETA_GROUP_SIZE; 597 598 for (i = 0; i < num; i++) { 599 memcpy(reta_conf->reta, 600 &lif->rss_ind_tbl[i * RTE_RETA_GROUP_SIZE], 601 RTE_RETA_GROUP_SIZE); 602 reta_conf++; 603 } 604 605 return 0; 606 } 607 608 static int 609 ionic_dev_rss_hash_conf_get(struct rte_eth_dev *eth_dev, 610 struct rte_eth_rss_conf *rss_conf) 611 { 612 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 613 uint64_t rss_hf = 0; 614 615 IONIC_PRINT_CALL(); 616 617 if (!lif->rss_ind_tbl) { 618 IONIC_PRINT(NOTICE, "RSS not enabled"); 619 return 0; 620 } 621 622 /* Get key value (if not null, rss_key is 40-byte) */ 623 if (rss_conf->rss_key != NULL && 624 rss_conf->rss_key_len >= IONIC_RSS_HASH_KEY_SIZE) 625 memcpy(rss_conf->rss_key, lif->rss_hash_key, 626 IONIC_RSS_HASH_KEY_SIZE); 627 628 if (lif->rss_types & IONIC_RSS_TYPE_IPV4) 629 rss_hf |= ETH_RSS_IPV4; 630 if (lif->rss_types & IONIC_RSS_TYPE_IPV4_TCP) 631 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP; 632 if (lif->rss_types & IONIC_RSS_TYPE_IPV4_UDP) 633 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP; 634 if (lif->rss_types & IONIC_RSS_TYPE_IPV6) 635 rss_hf |= ETH_RSS_IPV6; 636 if (lif->rss_types & IONIC_RSS_TYPE_IPV6_TCP) 637 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP; 638 if (lif->rss_types & IONIC_RSS_TYPE_IPV6_UDP) 639 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP; 640 641 rss_conf->rss_hf = rss_hf; 642 643 return 0; 644 } 645 646 static int 647 ionic_dev_rss_hash_update(struct rte_eth_dev *eth_dev, 648 struct rte_eth_rss_conf *rss_conf) 649 { 650 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 651 uint32_t rss_types = 0; 652 uint8_t *key = NULL; 653 654 IONIC_PRINT_CALL(); 655 656 if (rss_conf->rss_key) 657 key = rss_conf->rss_key; 658 659 if ((rss_conf->rss_hf & IONIC_ETH_RSS_OFFLOAD_ALL) == 0) { 660 /* 661 * Can't disable rss through hash flags, 662 * if it is enabled by default during init 663 */ 664 if (lif->rss_ind_tbl) 665 return -EINVAL; 666 } else { 667 /* Can't enable rss if disabled by default during init */ 668 if (!lif->rss_ind_tbl) 669 return -EINVAL; 670 671 if (rss_conf->rss_hf & ETH_RSS_IPV4) 672 rss_types |= IONIC_RSS_TYPE_IPV4; 673 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) 674 rss_types |= IONIC_RSS_TYPE_IPV4_TCP; 675 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) 676 rss_types |= IONIC_RSS_TYPE_IPV4_UDP; 677 if (rss_conf->rss_hf & ETH_RSS_IPV6) 678 rss_types |= IONIC_RSS_TYPE_IPV6; 679 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) 680 rss_types |= IONIC_RSS_TYPE_IPV6_TCP; 681 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) 682 rss_types |= IONIC_RSS_TYPE_IPV6_UDP; 683 684 ionic_lif_rss_config(lif, rss_types, key, NULL); 685 } 686 687 return 0; 688 } 689 690 static int 691 ionic_dev_stats_get(struct rte_eth_dev *eth_dev, 692 struct rte_eth_stats *stats) 693 { 694 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 695 696 ionic_lif_get_stats(lif, stats); 697 698 return 0; 699 } 700 701 static int 702 ionic_dev_stats_reset(struct rte_eth_dev *eth_dev) 703 { 704 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 705 706 IONIC_PRINT_CALL(); 707 708 ionic_lif_reset_stats(lif); 709 710 return 0; 711 } 712 713 static int 714 ionic_dev_xstats_get_names(__rte_unused struct rte_eth_dev *eth_dev, 715 struct rte_eth_xstat_name *xstats_names, 716 __rte_unused unsigned int size) 717 { 718 unsigned int i; 719 720 if (xstats_names != NULL) { 721 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 722 snprintf(xstats_names[i].name, 723 sizeof(xstats_names[i].name), 724 "%s", rte_ionic_xstats_strings[i].name); 725 } 726 } 727 728 return IONIC_NB_HW_STATS; 729 } 730 731 static int 732 ionic_dev_xstats_get_names_by_id(struct rte_eth_dev *eth_dev, 733 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids, 734 unsigned int limit) 735 { 736 struct rte_eth_xstat_name xstats_names_copy[IONIC_NB_HW_STATS]; 737 uint16_t i; 738 739 if (!ids) { 740 if (xstats_names != NULL) { 741 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 742 snprintf(xstats_names[i].name, 743 sizeof(xstats_names[i].name), 744 "%s", rte_ionic_xstats_strings[i].name); 745 } 746 } 747 748 return IONIC_NB_HW_STATS; 749 } 750 751 ionic_dev_xstats_get_names_by_id(eth_dev, xstats_names_copy, NULL, 752 IONIC_NB_HW_STATS); 753 754 for (i = 0; i < limit; i++) { 755 if (ids[i] >= IONIC_NB_HW_STATS) { 756 IONIC_PRINT(ERR, "id value isn't valid"); 757 return -1; 758 } 759 760 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 761 } 762 763 return limit; 764 } 765 766 static int 767 ionic_dev_xstats_get(struct rte_eth_dev *eth_dev, struct rte_eth_xstat *xstats, 768 unsigned int n) 769 { 770 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 771 struct ionic_lif_stats hw_stats; 772 uint16_t i; 773 774 if (n < IONIC_NB_HW_STATS) 775 return IONIC_NB_HW_STATS; 776 777 ionic_lif_get_hw_stats(lif, &hw_stats); 778 779 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 780 xstats[i].value = *(uint64_t *)(((char *)&hw_stats) + 781 rte_ionic_xstats_strings[i].offset); 782 xstats[i].id = i; 783 } 784 785 return IONIC_NB_HW_STATS; 786 } 787 788 static int 789 ionic_dev_xstats_get_by_id(struct rte_eth_dev *eth_dev, const uint64_t *ids, 790 uint64_t *values, unsigned int n) 791 { 792 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 793 struct ionic_lif_stats hw_stats; 794 uint64_t values_copy[IONIC_NB_HW_STATS]; 795 uint16_t i; 796 797 if (!ids) { 798 if (!ids && n < IONIC_NB_HW_STATS) 799 return IONIC_NB_HW_STATS; 800 801 ionic_lif_get_hw_stats(lif, &hw_stats); 802 803 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 804 values[i] = *(uint64_t *)(((char *)&hw_stats) + 805 rte_ionic_xstats_strings[i].offset); 806 } 807 808 return IONIC_NB_HW_STATS; 809 } 810 811 ionic_dev_xstats_get_by_id(eth_dev, NULL, values_copy, 812 IONIC_NB_HW_STATS); 813 814 for (i = 0; i < n; i++) { 815 if (ids[i] >= IONIC_NB_HW_STATS) { 816 IONIC_PRINT(ERR, "id value isn't valid"); 817 return -1; 818 } 819 820 values[i] = values_copy[ids[i]]; 821 } 822 823 return n; 824 } 825 826 static int 827 ionic_dev_xstats_reset(struct rte_eth_dev *eth_dev) 828 { 829 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 830 831 ionic_lif_reset_hw_stats(lif); 832 833 return 0; 834 } 835 836 static int 837 ionic_dev_configure(struct rte_eth_dev *eth_dev) 838 { 839 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 840 841 IONIC_PRINT_CALL(); 842 843 ionic_lif_configure(lif); 844 845 ionic_lif_set_features(lif); 846 847 return 0; 848 } 849 850 static inline uint32_t 851 ionic_parse_link_speeds(uint16_t link_speeds) 852 { 853 if (link_speeds & ETH_LINK_SPEED_100G) 854 return 100000; 855 else if (link_speeds & ETH_LINK_SPEED_50G) 856 return 50000; 857 else if (link_speeds & ETH_LINK_SPEED_40G) 858 return 40000; 859 else if (link_speeds & ETH_LINK_SPEED_25G) 860 return 25000; 861 else if (link_speeds & ETH_LINK_SPEED_10G) 862 return 10000; 863 else 864 return 0; 865 } 866 867 /* 868 * Configure device link speed and setup link. 869 * It returns 0 on success. 870 */ 871 static int 872 ionic_dev_start(struct rte_eth_dev *eth_dev) 873 { 874 struct rte_eth_conf *dev_conf = ð_dev->data->dev_conf; 875 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 876 struct ionic_adapter *adapter = lif->adapter; 877 struct ionic_dev *idev = &adapter->idev; 878 uint32_t speed = 0, allowed_speeds; 879 uint8_t an_enable; 880 int err; 881 882 IONIC_PRINT_CALL(); 883 884 allowed_speeds = 885 ETH_LINK_SPEED_FIXED | 886 ETH_LINK_SPEED_10G | 887 ETH_LINK_SPEED_25G | 888 ETH_LINK_SPEED_40G | 889 ETH_LINK_SPEED_50G | 890 ETH_LINK_SPEED_100G; 891 892 if (dev_conf->link_speeds & ~allowed_speeds) { 893 IONIC_PRINT(ERR, "Invalid link setting"); 894 return -EINVAL; 895 } 896 897 if (dev_conf->lpbk_mode) 898 IONIC_PRINT(WARNING, "Loopback mode not supported"); 899 900 err = ionic_lif_start(lif); 901 if (err) { 902 IONIC_PRINT(ERR, "Cannot start LIF: %d", err); 903 return err; 904 } 905 906 /* Configure link */ 907 an_enable = (dev_conf->link_speeds & ETH_LINK_SPEED_FIXED) == 0; 908 909 ionic_dev_cmd_port_autoneg(idev, an_enable); 910 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 911 if (err) 912 IONIC_PRINT(WARNING, "Failed to %s autonegotiation", 913 an_enable ? "enable" : "disable"); 914 915 if (!an_enable) 916 speed = ionic_parse_link_speeds(dev_conf->link_speeds); 917 if (speed) { 918 ionic_dev_cmd_port_speed(idev, speed); 919 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 920 if (err) 921 IONIC_PRINT(WARNING, "Failed to set link speed %u", 922 speed); 923 } 924 925 ionic_dev_link_update(eth_dev, 0); 926 927 return 0; 928 } 929 930 /* 931 * Stop device: disable rx and tx functions to allow for reconfiguring. 932 */ 933 static int 934 ionic_dev_stop(struct rte_eth_dev *eth_dev) 935 { 936 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 937 938 IONIC_PRINT_CALL(); 939 940 ionic_lif_stop(lif); 941 942 return 0; 943 } 944 945 static void ionic_unconfigure_intr(struct ionic_adapter *adapter); 946 947 /* 948 * Reset and stop device. 949 */ 950 static int 951 ionic_dev_close(struct rte_eth_dev *eth_dev) 952 { 953 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 954 struct ionic_adapter *adapter = lif->adapter; 955 956 IONIC_PRINT_CALL(); 957 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 958 return 0; 959 960 ionic_lif_stop(lif); 961 962 ionic_lif_free_queues(lif); 963 964 IONIC_PRINT(NOTICE, "Removing device %s", eth_dev->device->name); 965 ionic_unconfigure_intr(adapter); 966 967 rte_eth_dev_destroy(eth_dev, eth_ionic_dev_uninit); 968 969 ionic_port_reset(adapter); 970 ionic_reset(adapter); 971 972 rte_free(adapter); 973 974 return 0; 975 } 976 977 static int 978 eth_ionic_dev_init(struct rte_eth_dev *eth_dev, void *init_params) 979 { 980 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 981 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 982 struct ionic_adapter *adapter = (struct ionic_adapter *)init_params; 983 int err; 984 985 IONIC_PRINT_CALL(); 986 987 eth_dev->dev_ops = &ionic_eth_dev_ops; 988 eth_dev->rx_pkt_burst = &ionic_recv_pkts; 989 eth_dev->tx_pkt_burst = &ionic_xmit_pkts; 990 eth_dev->tx_pkt_prepare = &ionic_prep_pkts; 991 992 /* Multi-process not supported, primary does initialization anyway */ 993 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 994 return 0; 995 996 rte_eth_copy_pci_info(eth_dev, pci_dev); 997 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 998 999 lif->eth_dev = eth_dev; 1000 lif->adapter = adapter; 1001 adapter->lif = lif; 1002 1003 IONIC_PRINT(DEBUG, "Up to %u MAC addresses supported", 1004 adapter->max_mac_addrs); 1005 1006 /* Allocate memory for storing MAC addresses */ 1007 eth_dev->data->mac_addrs = rte_zmalloc("ionic", 1008 RTE_ETHER_ADDR_LEN * adapter->max_mac_addrs, 0); 1009 1010 if (eth_dev->data->mac_addrs == NULL) { 1011 IONIC_PRINT(ERR, "Failed to allocate %u bytes needed to " 1012 "store MAC addresses", 1013 RTE_ETHER_ADDR_LEN * adapter->max_mac_addrs); 1014 err = -ENOMEM; 1015 goto err; 1016 } 1017 1018 err = ionic_lif_alloc(lif); 1019 if (err) { 1020 IONIC_PRINT(ERR, "Cannot allocate LIFs: %d, aborting", 1021 err); 1022 goto err; 1023 } 1024 1025 err = ionic_lif_init(lif); 1026 if (err) { 1027 IONIC_PRINT(ERR, "Cannot init LIFs: %d, aborting", err); 1028 goto err_free_lif; 1029 } 1030 1031 /* Copy the MAC address */ 1032 rte_ether_addr_copy((struct rte_ether_addr *)lif->mac_addr, 1033 ð_dev->data->mac_addrs[0]); 1034 1035 IONIC_PRINT(DEBUG, "Port %u initialized", eth_dev->data->port_id); 1036 1037 return 0; 1038 1039 err_free_lif: 1040 ionic_lif_free(lif); 1041 err: 1042 return err; 1043 } 1044 1045 static int 1046 eth_ionic_dev_uninit(struct rte_eth_dev *eth_dev) 1047 { 1048 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 1049 struct ionic_adapter *adapter = lif->adapter; 1050 1051 IONIC_PRINT_CALL(); 1052 1053 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1054 return 0; 1055 1056 adapter->lif = NULL; 1057 1058 ionic_lif_deinit(lif); 1059 ionic_lif_free(lif); 1060 1061 if (!(lif->state & IONIC_LIF_F_FW_RESET)) 1062 ionic_lif_reset(lif); 1063 1064 return 0; 1065 } 1066 1067 static int 1068 ionic_configure_intr(struct ionic_adapter *adapter) 1069 { 1070 struct rte_pci_device *pci_dev = adapter->pci_dev; 1071 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1072 int err; 1073 1074 IONIC_PRINT(DEBUG, "Configuring %u intrs", adapter->nintrs); 1075 1076 if (rte_intr_efd_enable(intr_handle, adapter->nintrs)) { 1077 IONIC_PRINT(ERR, "Fail to create eventfd"); 1078 return -1; 1079 } 1080 1081 if (rte_intr_dp_is_en(intr_handle)) 1082 IONIC_PRINT(DEBUG, 1083 "Packet I/O interrupt on datapath is enabled"); 1084 1085 if (!intr_handle->intr_vec) { 1086 intr_handle->intr_vec = rte_zmalloc("intr_vec", 1087 adapter->nintrs * sizeof(int), 0); 1088 1089 if (!intr_handle->intr_vec) { 1090 IONIC_PRINT(ERR, "Failed to allocate %u vectors", 1091 adapter->nintrs); 1092 return -ENOMEM; 1093 } 1094 } 1095 1096 err = rte_intr_callback_register(intr_handle, 1097 ionic_dev_interrupt_handler, 1098 adapter); 1099 1100 if (err) { 1101 IONIC_PRINT(ERR, 1102 "Failure registering interrupts handler (%d)", 1103 err); 1104 return err; 1105 } 1106 1107 /* enable intr mapping */ 1108 err = rte_intr_enable(intr_handle); 1109 1110 if (err) { 1111 IONIC_PRINT(ERR, "Failure enabling interrupts (%d)", err); 1112 return err; 1113 } 1114 1115 return 0; 1116 } 1117 1118 static void 1119 ionic_unconfigure_intr(struct ionic_adapter *adapter) 1120 { 1121 struct rte_pci_device *pci_dev = adapter->pci_dev; 1122 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1123 1124 rte_intr_disable(intr_handle); 1125 1126 rte_intr_callback_unregister(intr_handle, 1127 ionic_dev_interrupt_handler, 1128 adapter); 1129 } 1130 1131 static int 1132 eth_ionic_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1133 struct rte_pci_device *pci_dev) 1134 { 1135 char name[RTE_ETH_NAME_MAX_LEN]; 1136 struct rte_mem_resource *resource; 1137 struct ionic_adapter *adapter; 1138 struct ionic_hw *hw; 1139 unsigned long i; 1140 int err; 1141 1142 /* Check structs (trigger error at compilation time) */ 1143 ionic_struct_size_checks(); 1144 1145 /* Multi-process not supported */ 1146 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1147 err = -EPERM; 1148 goto err; 1149 } 1150 1151 IONIC_PRINT(DEBUG, "Initializing device %s", 1152 pci_dev->device.name); 1153 1154 adapter = rte_zmalloc("ionic", sizeof(*adapter), 0); 1155 if (!adapter) { 1156 IONIC_PRINT(ERR, "OOM"); 1157 err = -ENOMEM; 1158 goto err; 1159 } 1160 1161 adapter->pci_dev = pci_dev; 1162 hw = &adapter->hw; 1163 1164 hw->device_id = pci_dev->id.device_id; 1165 hw->vendor_id = pci_dev->id.vendor_id; 1166 1167 err = ionic_init_mac(hw); 1168 if (err != 0) { 1169 IONIC_PRINT(ERR, "Mac init failed: %d", err); 1170 err = -EIO; 1171 goto err_free_adapter; 1172 } 1173 1174 adapter->num_bars = 0; 1175 for (i = 0; i < PCI_MAX_RESOURCE && i < IONIC_BARS_MAX; i++) { 1176 resource = &pci_dev->mem_resource[i]; 1177 if (resource->phys_addr == 0 || resource->len == 0) 1178 continue; 1179 adapter->bars[adapter->num_bars].vaddr = resource->addr; 1180 adapter->bars[adapter->num_bars].bus_addr = resource->phys_addr; 1181 adapter->bars[adapter->num_bars].len = resource->len; 1182 adapter->num_bars++; 1183 } 1184 1185 /* Discover ionic dev resources */ 1186 1187 err = ionic_setup(adapter); 1188 if (err) { 1189 IONIC_PRINT(ERR, "Cannot setup device: %d, aborting", err); 1190 goto err_free_adapter; 1191 } 1192 1193 err = ionic_identify(adapter); 1194 if (err) { 1195 IONIC_PRINT(ERR, "Cannot identify device: %d, aborting", 1196 err); 1197 goto err_free_adapter; 1198 } 1199 1200 err = ionic_init(adapter); 1201 if (err) { 1202 IONIC_PRINT(ERR, "Cannot init device: %d, aborting", err); 1203 goto err_free_adapter; 1204 } 1205 1206 /* Configure the ports */ 1207 err = ionic_port_identify(adapter); 1208 if (err) { 1209 IONIC_PRINT(ERR, "Cannot identify port: %d, aborting", 1210 err); 1211 goto err_free_adapter; 1212 } 1213 1214 err = ionic_port_init(adapter); 1215 if (err) { 1216 IONIC_PRINT(ERR, "Cannot init port: %d, aborting", err); 1217 goto err_free_adapter; 1218 } 1219 1220 /* Configure LIFs */ 1221 err = ionic_lif_identify(adapter); 1222 if (err) { 1223 IONIC_PRINT(ERR, "Cannot identify lif: %d, aborting", err); 1224 goto err_free_adapter; 1225 } 1226 1227 /* Allocate and init LIFs */ 1228 err = ionic_lifs_size(adapter); 1229 if (err) { 1230 IONIC_PRINT(ERR, "Cannot size LIFs: %d, aborting", err); 1231 goto err_free_adapter; 1232 } 1233 1234 adapter->max_mac_addrs = 1235 rte_le_to_cpu_32(adapter->ident.lif.eth.max_ucast_filters); 1236 1237 if (rte_le_to_cpu_32(adapter->ident.dev.nlifs) != 1) { 1238 IONIC_PRINT(ERR, "Unexpected request for %d LIFs", 1239 rte_le_to_cpu_32(adapter->ident.dev.nlifs)); 1240 goto err_free_adapter; 1241 } 1242 1243 snprintf(name, sizeof(name), "%s_lif", pci_dev->device.name); 1244 err = rte_eth_dev_create(&pci_dev->device, 1245 name, sizeof(struct ionic_lif), 1246 NULL, NULL, eth_ionic_dev_init, adapter); 1247 if (err) { 1248 IONIC_PRINT(ERR, "Cannot create eth device for %s", name); 1249 goto err_free_adapter; 1250 } 1251 1252 err = ionic_configure_intr(adapter); 1253 1254 if (err) { 1255 IONIC_PRINT(ERR, "Failed to configure interrupts"); 1256 goto err_free_adapter; 1257 } 1258 1259 return 0; 1260 1261 err_free_adapter: 1262 rte_free(adapter); 1263 err: 1264 return err; 1265 } 1266 1267 static int 1268 eth_ionic_pci_remove(struct rte_pci_device *pci_dev) 1269 { 1270 char name[RTE_ETH_NAME_MAX_LEN]; 1271 struct rte_eth_dev *eth_dev; 1272 1273 /* Adapter lookup is using the eth_dev name */ 1274 snprintf(name, sizeof(name), "%s_lif", pci_dev->device.name); 1275 1276 eth_dev = rte_eth_dev_allocated(name); 1277 if (eth_dev) 1278 ionic_dev_close(eth_dev); 1279 else 1280 IONIC_PRINT(DEBUG, "Cannot find device %s", 1281 pci_dev->device.name); 1282 1283 return 0; 1284 } 1285 1286 static struct rte_pci_driver rte_ionic_pmd = { 1287 .id_table = pci_id_ionic_map, 1288 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 1289 .probe = eth_ionic_pci_probe, 1290 .remove = eth_ionic_pci_remove, 1291 }; 1292 1293 RTE_PMD_REGISTER_PCI(net_ionic, rte_ionic_pmd); 1294 RTE_PMD_REGISTER_PCI_TABLE(net_ionic, pci_id_ionic_map); 1295 RTE_PMD_REGISTER_KMOD_DEP(net_ionic, "* igb_uio | uio_pci_generic | vfio-pci"); 1296 RTE_LOG_REGISTER(ionic_logtype, pmd.net.ionic, NOTICE); 1297