1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018-2022 Advanced Micro Devices, Inc. 3 */ 4 5 #include <rte_ethdev.h> 6 #include <ethdev_driver.h> 7 #include <rte_malloc.h> 8 9 #include "ionic_logs.h" 10 #include "ionic.h" 11 #include "ionic_dev.h" 12 #include "ionic_mac_api.h" 13 #include "ionic_lif.h" 14 #include "ionic_ethdev.h" 15 #include "ionic_rxtx.h" 16 17 static int eth_ionic_dev_init(struct rte_eth_dev *eth_dev, void *init_params); 18 static int eth_ionic_dev_uninit(struct rte_eth_dev *eth_dev); 19 static int ionic_dev_info_get(struct rte_eth_dev *eth_dev, 20 struct rte_eth_dev_info *dev_info); 21 static int ionic_dev_configure(struct rte_eth_dev *dev); 22 static int ionic_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 23 static int ionic_dev_start(struct rte_eth_dev *dev); 24 static int ionic_dev_stop(struct rte_eth_dev *dev); 25 static int ionic_dev_close(struct rte_eth_dev *dev); 26 static int ionic_dev_set_link_up(struct rte_eth_dev *dev); 27 static int ionic_dev_set_link_down(struct rte_eth_dev *dev); 28 static int ionic_flow_ctrl_get(struct rte_eth_dev *eth_dev, 29 struct rte_eth_fc_conf *fc_conf); 30 static int ionic_flow_ctrl_set(struct rte_eth_dev *eth_dev, 31 struct rte_eth_fc_conf *fc_conf); 32 static int ionic_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask); 33 static int ionic_dev_rss_reta_update(struct rte_eth_dev *eth_dev, 34 struct rte_eth_rss_reta_entry64 *reta_conf, uint16_t reta_size); 35 static int ionic_dev_rss_reta_query(struct rte_eth_dev *eth_dev, 36 struct rte_eth_rss_reta_entry64 *reta_conf, uint16_t reta_size); 37 static int ionic_dev_rss_hash_conf_get(struct rte_eth_dev *eth_dev, 38 struct rte_eth_rss_conf *rss_conf); 39 static int ionic_dev_rss_hash_update(struct rte_eth_dev *eth_dev, 40 struct rte_eth_rss_conf *rss_conf); 41 static int ionic_dev_stats_get(struct rte_eth_dev *eth_dev, 42 struct rte_eth_stats *stats); 43 static int ionic_dev_stats_reset(struct rte_eth_dev *eth_dev); 44 static int ionic_dev_xstats_get(struct rte_eth_dev *dev, 45 struct rte_eth_xstat *xstats, unsigned int n); 46 static int ionic_dev_xstats_get_by_id(struct rte_eth_dev *dev, 47 const uint64_t *ids, uint64_t *values, unsigned int n); 48 static int ionic_dev_xstats_reset(struct rte_eth_dev *dev); 49 static int ionic_dev_xstats_get_names(struct rte_eth_dev *dev, 50 struct rte_eth_xstat_name *xstats_names, unsigned int size); 51 static int ionic_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, 52 const uint64_t *ids, struct rte_eth_xstat_name *xstats_names, 53 unsigned int limit); 54 static int ionic_dev_fw_version_get(struct rte_eth_dev *eth_dev, 55 char *fw_version, size_t fw_size); 56 57 static const struct rte_eth_desc_lim rx_desc_lim = { 58 .nb_max = IONIC_MAX_RING_DESC, 59 .nb_min = IONIC_MIN_RING_DESC, 60 .nb_align = 1, 61 }; 62 63 static const struct rte_eth_desc_lim tx_desc_lim_v1 = { 64 .nb_max = IONIC_MAX_RING_DESC, 65 .nb_min = IONIC_MIN_RING_DESC, 66 .nb_align = 1, 67 .nb_seg_max = IONIC_TX_MAX_SG_ELEMS_V1 + 1, 68 .nb_mtu_seg_max = IONIC_TX_MAX_SG_ELEMS_V1 + 1, 69 }; 70 71 static const struct eth_dev_ops ionic_eth_dev_ops = { 72 .dev_infos_get = ionic_dev_info_get, 73 .dev_supported_ptypes_get = ionic_dev_supported_ptypes_get, 74 .dev_configure = ionic_dev_configure, 75 .mtu_set = ionic_dev_mtu_set, 76 .dev_start = ionic_dev_start, 77 .dev_stop = ionic_dev_stop, 78 .dev_close = ionic_dev_close, 79 .link_update = ionic_dev_link_update, 80 .dev_set_link_up = ionic_dev_set_link_up, 81 .dev_set_link_down = ionic_dev_set_link_down, 82 .mac_addr_add = ionic_dev_add_mac, 83 .mac_addr_remove = ionic_dev_remove_mac, 84 .mac_addr_set = ionic_dev_set_mac, 85 .vlan_filter_set = ionic_dev_vlan_filter_set, 86 .promiscuous_enable = ionic_dev_promiscuous_enable, 87 .promiscuous_disable = ionic_dev_promiscuous_disable, 88 .allmulticast_enable = ionic_dev_allmulticast_enable, 89 .allmulticast_disable = ionic_dev_allmulticast_disable, 90 .flow_ctrl_get = ionic_flow_ctrl_get, 91 .flow_ctrl_set = ionic_flow_ctrl_set, 92 .rxq_info_get = ionic_rxq_info_get, 93 .txq_info_get = ionic_txq_info_get, 94 .rx_queue_setup = ionic_dev_rx_queue_setup, 95 .rx_queue_release = ionic_dev_rx_queue_release, 96 .rx_queue_start = ionic_dev_rx_queue_start, 97 .rx_queue_stop = ionic_dev_rx_queue_stop, 98 .tx_queue_setup = ionic_dev_tx_queue_setup, 99 .tx_queue_release = ionic_dev_tx_queue_release, 100 .tx_queue_start = ionic_dev_tx_queue_start, 101 .tx_queue_stop = ionic_dev_tx_queue_stop, 102 .vlan_offload_set = ionic_vlan_offload_set, 103 .reta_update = ionic_dev_rss_reta_update, 104 .reta_query = ionic_dev_rss_reta_query, 105 .rss_hash_conf_get = ionic_dev_rss_hash_conf_get, 106 .rss_hash_update = ionic_dev_rss_hash_update, 107 .stats_get = ionic_dev_stats_get, 108 .stats_reset = ionic_dev_stats_reset, 109 .xstats_get = ionic_dev_xstats_get, 110 .xstats_get_by_id = ionic_dev_xstats_get_by_id, 111 .xstats_reset = ionic_dev_xstats_reset, 112 .xstats_get_names = ionic_dev_xstats_get_names, 113 .xstats_get_names_by_id = ionic_dev_xstats_get_names_by_id, 114 .fw_version_get = ionic_dev_fw_version_get, 115 }; 116 117 struct rte_ionic_xstats_name_off { 118 char name[RTE_ETH_XSTATS_NAME_SIZE]; 119 unsigned int offset; 120 }; 121 122 static const struct rte_ionic_xstats_name_off rte_ionic_xstats_strings[] = { 123 /* RX */ 124 {"rx_ucast_bytes", offsetof(struct ionic_lif_stats, 125 rx_ucast_bytes)}, 126 {"rx_ucast_packets", offsetof(struct ionic_lif_stats, 127 rx_ucast_packets)}, 128 {"rx_mcast_bytes", offsetof(struct ionic_lif_stats, 129 rx_mcast_bytes)}, 130 {"rx_mcast_packets", offsetof(struct ionic_lif_stats, 131 rx_mcast_packets)}, 132 {"rx_bcast_bytes", offsetof(struct ionic_lif_stats, 133 rx_bcast_bytes)}, 134 {"rx_bcast_packets", offsetof(struct ionic_lif_stats, 135 rx_bcast_packets)}, 136 /* RX drops */ 137 {"rx_ucast_drop_bytes", offsetof(struct ionic_lif_stats, 138 rx_ucast_drop_bytes)}, 139 {"rx_ucast_drop_packets", offsetof(struct ionic_lif_stats, 140 rx_ucast_drop_packets)}, 141 {"rx_mcast_drop_bytes", offsetof(struct ionic_lif_stats, 142 rx_mcast_drop_bytes)}, 143 {"rx_mcast_drop_packets", offsetof(struct ionic_lif_stats, 144 rx_mcast_drop_packets)}, 145 {"rx_bcast_drop_bytes", offsetof(struct ionic_lif_stats, 146 rx_bcast_drop_bytes)}, 147 {"rx_bcast_drop_packets", offsetof(struct ionic_lif_stats, 148 rx_bcast_drop_packets)}, 149 {"rx_dma_error", offsetof(struct ionic_lif_stats, 150 rx_dma_error)}, 151 /* TX */ 152 {"tx_ucast_bytes", offsetof(struct ionic_lif_stats, 153 tx_ucast_bytes)}, 154 {"tx_ucast_packets", offsetof(struct ionic_lif_stats, 155 tx_ucast_packets)}, 156 {"tx_mcast_bytes", offsetof(struct ionic_lif_stats, 157 tx_mcast_bytes)}, 158 {"tx_mcast_packets", offsetof(struct ionic_lif_stats, 159 tx_mcast_packets)}, 160 {"tx_bcast_bytes", offsetof(struct ionic_lif_stats, 161 tx_bcast_bytes)}, 162 {"tx_bcast_packets", offsetof(struct ionic_lif_stats, 163 tx_bcast_packets)}, 164 /* TX drops */ 165 {"tx_ucast_drop_bytes", offsetof(struct ionic_lif_stats, 166 tx_ucast_drop_bytes)}, 167 {"tx_ucast_drop_packets", offsetof(struct ionic_lif_stats, 168 tx_ucast_drop_packets)}, 169 {"tx_mcast_drop_bytes", offsetof(struct ionic_lif_stats, 170 tx_mcast_drop_bytes)}, 171 {"tx_mcast_drop_packets", offsetof(struct ionic_lif_stats, 172 tx_mcast_drop_packets)}, 173 {"tx_bcast_drop_bytes", offsetof(struct ionic_lif_stats, 174 tx_bcast_drop_bytes)}, 175 {"tx_bcast_drop_packets", offsetof(struct ionic_lif_stats, 176 tx_bcast_drop_packets)}, 177 {"tx_dma_error", offsetof(struct ionic_lif_stats, 178 tx_dma_error)}, 179 /* Rx Queue/Ring drops */ 180 {"rx_queue_disabled", offsetof(struct ionic_lif_stats, 181 rx_queue_disabled)}, 182 {"rx_queue_empty", offsetof(struct ionic_lif_stats, 183 rx_queue_empty)}, 184 {"rx_queue_error", offsetof(struct ionic_lif_stats, 185 rx_queue_error)}, 186 {"rx_desc_fetch_error", offsetof(struct ionic_lif_stats, 187 rx_desc_fetch_error)}, 188 {"rx_desc_data_error", offsetof(struct ionic_lif_stats, 189 rx_desc_data_error)}, 190 /* Tx Queue/Ring drops */ 191 {"tx_queue_disabled", offsetof(struct ionic_lif_stats, 192 tx_queue_disabled)}, 193 {"tx_queue_error", offsetof(struct ionic_lif_stats, 194 tx_queue_error)}, 195 {"tx_desc_fetch_error", offsetof(struct ionic_lif_stats, 196 tx_desc_fetch_error)}, 197 {"tx_desc_data_error", offsetof(struct ionic_lif_stats, 198 tx_desc_data_error)}, 199 }; 200 201 #define IONIC_NB_HW_STATS RTE_DIM(rte_ionic_xstats_strings) 202 203 static int 204 ionic_dev_fw_version_get(struct rte_eth_dev *eth_dev, 205 char *fw_version, size_t fw_size) 206 { 207 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 208 struct ionic_adapter *adapter = lif->adapter; 209 int ret; 210 211 ret = snprintf(fw_version, fw_size, "%s", 212 adapter->fw_version); 213 if (ret < 0) 214 return -EINVAL; 215 216 ret += 1; /* add the size of '\0' */ 217 if (fw_size < (size_t)ret) 218 return ret; 219 else 220 return 0; 221 } 222 223 /* 224 * Set device link up, enable tx. 225 */ 226 static int 227 ionic_dev_set_link_up(struct rte_eth_dev *eth_dev) 228 { 229 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 230 int err; 231 232 IONIC_PRINT_CALL(); 233 234 err = ionic_lif_start(lif); 235 if (err) 236 IONIC_PRINT(ERR, "Could not start lif to set link up"); 237 238 ionic_dev_link_update(lif->eth_dev, 0); 239 240 return err; 241 } 242 243 /* 244 * Set device link down, disable tx. 245 */ 246 static int 247 ionic_dev_set_link_down(struct rte_eth_dev *eth_dev) 248 { 249 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 250 251 IONIC_PRINT_CALL(); 252 253 ionic_lif_stop(lif); 254 255 ionic_dev_link_update(lif->eth_dev, 0); 256 257 return 0; 258 } 259 260 int 261 ionic_dev_link_update(struct rte_eth_dev *eth_dev, 262 int wait_to_complete __rte_unused) 263 { 264 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 265 struct ionic_adapter *adapter = lif->adapter; 266 struct rte_eth_link link; 267 268 IONIC_PRINT_CALL(); 269 270 /* Initialize */ 271 memset(&link, 0, sizeof(link)); 272 273 if (adapter->idev.port_info->config.an_enable) { 274 link.link_autoneg = RTE_ETH_LINK_AUTONEG; 275 } 276 277 if (!adapter->link_up || 278 !(lif->state & IONIC_LIF_F_UP)) { 279 /* Interface is down */ 280 link.link_status = RTE_ETH_LINK_DOWN; 281 link.link_duplex = RTE_ETH_LINK_HALF_DUPLEX; 282 link.link_speed = RTE_ETH_SPEED_NUM_NONE; 283 } else { 284 /* Interface is up */ 285 link.link_status = RTE_ETH_LINK_UP; 286 link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX; 287 switch (adapter->link_speed) { 288 case 10000: 289 link.link_speed = RTE_ETH_SPEED_NUM_10G; 290 break; 291 case 25000: 292 link.link_speed = RTE_ETH_SPEED_NUM_25G; 293 break; 294 case 40000: 295 link.link_speed = RTE_ETH_SPEED_NUM_40G; 296 break; 297 case 50000: 298 link.link_speed = RTE_ETH_SPEED_NUM_50G; 299 break; 300 case 100000: 301 link.link_speed = RTE_ETH_SPEED_NUM_100G; 302 break; 303 default: 304 link.link_speed = RTE_ETH_SPEED_NUM_NONE; 305 break; 306 } 307 } 308 309 return rte_eth_linkstatus_set(eth_dev, &link); 310 } 311 312 /** 313 * Interrupt handler triggered by NIC for handling 314 * specific interrupt. 315 * 316 * @param param 317 * The address of parameter registered before. 318 * 319 * @return 320 * void 321 */ 322 void 323 ionic_dev_interrupt_handler(void *param) 324 { 325 struct ionic_adapter *adapter = (struct ionic_adapter *)param; 326 327 IONIC_PRINT(DEBUG, "->"); 328 329 if (adapter->lif) 330 ionic_notifyq_handler(adapter->lif, -1); 331 } 332 333 static int 334 ionic_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) 335 { 336 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 337 338 if (lif->state & IONIC_LIF_F_UP) { 339 IONIC_PRINT(ERR, "Stop %s before setting mtu", lif->name); 340 return -EBUSY; 341 } 342 343 /* Note: mtu check against min/max is done by the API */ 344 IONIC_PRINT(INFO, "Setting mtu %u", mtu); 345 346 /* Update the frame size used by the Rx path */ 347 lif->frame_size = mtu + IONIC_ETH_OVERHEAD; 348 349 return 0; 350 } 351 352 static int 353 ionic_dev_info_get(struct rte_eth_dev *eth_dev, 354 struct rte_eth_dev_info *dev_info) 355 { 356 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 357 struct ionic_adapter *adapter = lif->adapter; 358 struct ionic_identity *ident = &adapter->ident; 359 union ionic_lif_config *cfg = &ident->lif.eth.config; 360 361 IONIC_PRINT_CALL(); 362 363 dev_info->max_rx_queues = (uint16_t) 364 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_RXQ]); 365 dev_info->max_tx_queues = (uint16_t) 366 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ]); 367 368 /* Also add ETHER_CRC_LEN if the adapter is able to keep CRC */ 369 dev_info->min_mtu = RTE_MAX((uint32_t)IONIC_MIN_MTU, 370 rte_le_to_cpu_32(ident->lif.eth.min_mtu)); 371 dev_info->max_mtu = RTE_MIN((uint32_t)IONIC_MAX_MTU, 372 rte_le_to_cpu_32(ident->lif.eth.max_mtu)); 373 dev_info->min_rx_bufsize = dev_info->min_mtu + IONIC_ETH_OVERHEAD; 374 dev_info->max_rx_pktlen = dev_info->max_mtu + IONIC_ETH_OVERHEAD; 375 dev_info->max_lro_pkt_size = 376 eth_dev->data->dev_conf.rxmode.max_lro_pkt_size; 377 378 dev_info->max_mac_addrs = adapter->max_mac_addrs; 379 dev_info->hash_key_size = IONIC_RSS_HASH_KEY_SIZE; 380 dev_info->reta_size = rte_le_to_cpu_16(ident->lif.eth.rss_ind_tbl_sz); 381 dev_info->flow_type_rss_offloads = IONIC_ETH_RSS_OFFLOAD_ALL; 382 383 dev_info->speed_capa = 384 RTE_ETH_LINK_SPEED_10G | 385 RTE_ETH_LINK_SPEED_25G | 386 RTE_ETH_LINK_SPEED_40G | 387 RTE_ETH_LINK_SPEED_50G | 388 RTE_ETH_LINK_SPEED_100G; 389 390 /* 391 * Per-queue capabilities 392 * RTE does not support disabling a feature on a queue if it is 393 * enabled globally on the device. Thus the driver does not advertise 394 * capabilities like RTE_ETH_TX_OFFLOAD_IPV4_CKSUM as per-queue even 395 * though the driver would be otherwise capable of disabling it on 396 * a per-queue basis. 397 */ 398 399 dev_info->rx_queue_offload_capa = 0; 400 dev_info->tx_queue_offload_capa = RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE; 401 402 /* 403 * Per-port capabilities 404 * See ionic_set_features to request and check supported features 405 */ 406 407 dev_info->rx_offload_capa = dev_info->rx_queue_offload_capa | 408 RTE_ETH_RX_OFFLOAD_IPV4_CKSUM | 409 RTE_ETH_RX_OFFLOAD_UDP_CKSUM | 410 RTE_ETH_RX_OFFLOAD_TCP_CKSUM | 411 RTE_ETH_RX_OFFLOAD_VLAN_FILTER | 412 RTE_ETH_RX_OFFLOAD_VLAN_STRIP | 413 RTE_ETH_RX_OFFLOAD_SCATTER | 414 RTE_ETH_RX_OFFLOAD_RSS_HASH | 415 0; 416 417 dev_info->tx_offload_capa = dev_info->tx_queue_offload_capa | 418 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | 419 RTE_ETH_TX_OFFLOAD_UDP_CKSUM | 420 RTE_ETH_TX_OFFLOAD_TCP_CKSUM | 421 RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM | 422 RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM | 423 RTE_ETH_TX_OFFLOAD_MULTI_SEGS | 424 RTE_ETH_TX_OFFLOAD_TCP_TSO | 425 RTE_ETH_TX_OFFLOAD_VLAN_INSERT | 426 0; 427 428 dev_info->rx_desc_lim = rx_desc_lim; 429 dev_info->tx_desc_lim = tx_desc_lim_v1; 430 431 /* Driver-preferred Rx/Tx parameters */ 432 dev_info->default_rxportconf.burst_size = IONIC_DEF_TXRX_BURST; 433 dev_info->default_txportconf.burst_size = IONIC_DEF_TXRX_BURST; 434 dev_info->default_rxportconf.nb_queues = 1; 435 dev_info->default_txportconf.nb_queues = 1; 436 dev_info->default_rxportconf.ring_size = IONIC_DEF_TXRX_DESC; 437 dev_info->default_txportconf.ring_size = IONIC_DEF_TXRX_DESC; 438 439 dev_info->default_rxconf = (struct rte_eth_rxconf) { 440 /* Packets are always dropped if no desc are available */ 441 .rx_drop_en = 1, 442 }; 443 444 return 0; 445 } 446 447 static int 448 ionic_flow_ctrl_get(struct rte_eth_dev *eth_dev, 449 struct rte_eth_fc_conf *fc_conf) 450 { 451 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 452 struct ionic_adapter *adapter = lif->adapter; 453 struct ionic_dev *idev = &adapter->idev; 454 455 if (idev->port_info) { 456 /* Flow control autoneg not supported */ 457 fc_conf->autoneg = 0; 458 459 if (idev->port_info->config.pause_type) 460 fc_conf->mode = RTE_ETH_FC_FULL; 461 else 462 fc_conf->mode = RTE_ETH_FC_NONE; 463 } 464 465 return 0; 466 } 467 468 static int 469 ionic_flow_ctrl_set(struct rte_eth_dev *eth_dev, 470 struct rte_eth_fc_conf *fc_conf) 471 { 472 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 473 struct ionic_adapter *adapter = lif->adapter; 474 struct ionic_dev *idev = &adapter->idev; 475 uint8_t pause_type = IONIC_PORT_PAUSE_TYPE_NONE; 476 int err; 477 478 if (fc_conf->autoneg) { 479 IONIC_PRINT(WARNING, "Flow control autoneg not supported"); 480 return -ENOTSUP; 481 } 482 483 switch (fc_conf->mode) { 484 case RTE_ETH_FC_NONE: 485 pause_type = IONIC_PORT_PAUSE_TYPE_NONE; 486 break; 487 case RTE_ETH_FC_FULL: 488 pause_type = IONIC_PORT_PAUSE_TYPE_LINK; 489 break; 490 case RTE_ETH_FC_RX_PAUSE: 491 case RTE_ETH_FC_TX_PAUSE: 492 return -ENOTSUP; 493 } 494 495 ionic_dev_cmd_port_pause(idev, pause_type); 496 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 497 if (err) 498 IONIC_PRINT(WARNING, "Failed to configure flow control"); 499 500 return err; 501 } 502 503 static int 504 ionic_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask) 505 { 506 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 507 508 ionic_lif_configure_vlan_offload(lif, mask); 509 510 ionic_lif_set_features(lif); 511 512 return 0; 513 } 514 515 static int 516 ionic_dev_rss_reta_update(struct rte_eth_dev *eth_dev, 517 struct rte_eth_rss_reta_entry64 *reta_conf, 518 uint16_t reta_size) 519 { 520 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 521 struct ionic_adapter *adapter = lif->adapter; 522 struct ionic_identity *ident = &adapter->ident; 523 uint32_t i, j, index, num; 524 uint16_t tbl_sz = rte_le_to_cpu_16(ident->lif.eth.rss_ind_tbl_sz); 525 526 IONIC_PRINT_CALL(); 527 528 if (!lif->rss_ind_tbl) { 529 IONIC_PRINT(ERR, "RSS RETA not initialized, " 530 "can't update the table"); 531 return -EINVAL; 532 } 533 534 if (reta_size != tbl_sz) { 535 IONIC_PRINT(ERR, "The size of hash lookup table configured " 536 "(%d) does not match the number hardware can support " 537 "(%d)", 538 reta_size, tbl_sz); 539 return -EINVAL; 540 } 541 542 num = tbl_sz / RTE_ETH_RETA_GROUP_SIZE; 543 544 for (i = 0; i < num; i++) { 545 for (j = 0; j < RTE_ETH_RETA_GROUP_SIZE; j++) { 546 if (reta_conf[i].mask & ((uint64_t)1 << j)) { 547 index = (i * RTE_ETH_RETA_GROUP_SIZE) + j; 548 lif->rss_ind_tbl[index] = reta_conf[i].reta[j]; 549 } 550 } 551 } 552 553 return ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL); 554 } 555 556 static int 557 ionic_dev_rss_reta_query(struct rte_eth_dev *eth_dev, 558 struct rte_eth_rss_reta_entry64 *reta_conf, 559 uint16_t reta_size) 560 { 561 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 562 struct ionic_adapter *adapter = lif->adapter; 563 struct ionic_identity *ident = &adapter->ident; 564 int i, j, num; 565 uint16_t tbl_sz = rte_le_to_cpu_16(ident->lif.eth.rss_ind_tbl_sz); 566 567 IONIC_PRINT_CALL(); 568 569 if (reta_size != tbl_sz) { 570 IONIC_PRINT(ERR, "The size of hash lookup table configured " 571 "(%d) does not match the number hardware can support " 572 "(%d)", 573 reta_size, tbl_sz); 574 return -EINVAL; 575 } 576 577 if (!lif->rss_ind_tbl) { 578 IONIC_PRINT(ERR, "RSS RETA has not been built yet"); 579 return -EINVAL; 580 } 581 582 num = reta_size / RTE_ETH_RETA_GROUP_SIZE; 583 584 for (i = 0; i < num; i++) { 585 for (j = 0; j < RTE_ETH_RETA_GROUP_SIZE; j++) { 586 reta_conf->reta[j] = 587 lif->rss_ind_tbl[(i * RTE_ETH_RETA_GROUP_SIZE) + j]; 588 } 589 reta_conf++; 590 } 591 592 return 0; 593 } 594 595 static int 596 ionic_dev_rss_hash_conf_get(struct rte_eth_dev *eth_dev, 597 struct rte_eth_rss_conf *rss_conf) 598 { 599 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 600 uint64_t rss_hf = 0; 601 602 IONIC_PRINT_CALL(); 603 604 if (!lif->rss_ind_tbl) { 605 IONIC_PRINT(NOTICE, "RSS not enabled"); 606 return 0; 607 } 608 609 /* Get key value (if not null, rss_key is 40-byte) */ 610 if (rss_conf->rss_key != NULL && 611 rss_conf->rss_key_len >= IONIC_RSS_HASH_KEY_SIZE) 612 memcpy(rss_conf->rss_key, lif->rss_hash_key, 613 IONIC_RSS_HASH_KEY_SIZE); 614 615 if (lif->rss_types & IONIC_RSS_TYPE_IPV4) 616 rss_hf |= RTE_ETH_RSS_IPV4; 617 if (lif->rss_types & IONIC_RSS_TYPE_IPV4_TCP) 618 rss_hf |= RTE_ETH_RSS_NONFRAG_IPV4_TCP; 619 if (lif->rss_types & IONIC_RSS_TYPE_IPV4_UDP) 620 rss_hf |= RTE_ETH_RSS_NONFRAG_IPV4_UDP; 621 if (lif->rss_types & IONIC_RSS_TYPE_IPV6) 622 rss_hf |= RTE_ETH_RSS_IPV6; 623 if (lif->rss_types & IONIC_RSS_TYPE_IPV6_TCP) 624 rss_hf |= RTE_ETH_RSS_NONFRAG_IPV6_TCP; 625 if (lif->rss_types & IONIC_RSS_TYPE_IPV6_UDP) 626 rss_hf |= RTE_ETH_RSS_NONFRAG_IPV6_UDP; 627 628 rss_conf->rss_hf = rss_hf; 629 630 return 0; 631 } 632 633 static int 634 ionic_dev_rss_hash_update(struct rte_eth_dev *eth_dev, 635 struct rte_eth_rss_conf *rss_conf) 636 { 637 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 638 uint32_t rss_types = 0; 639 uint8_t *key = NULL; 640 641 IONIC_PRINT_CALL(); 642 643 if (rss_conf->rss_key) 644 key = rss_conf->rss_key; 645 646 if ((rss_conf->rss_hf & IONIC_ETH_RSS_OFFLOAD_ALL) == 0) { 647 /* 648 * Can't disable rss through hash flags, 649 * if it is enabled by default during init 650 */ 651 if (lif->rss_ind_tbl) 652 return -EINVAL; 653 } else { 654 /* Can't enable rss if disabled by default during init */ 655 if (!lif->rss_ind_tbl) 656 return -EINVAL; 657 658 if (rss_conf->rss_hf & RTE_ETH_RSS_IPV4) 659 rss_types |= IONIC_RSS_TYPE_IPV4; 660 if (rss_conf->rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_TCP) 661 rss_types |= IONIC_RSS_TYPE_IPV4_TCP; 662 if (rss_conf->rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_UDP) 663 rss_types |= IONIC_RSS_TYPE_IPV4_UDP; 664 if (rss_conf->rss_hf & RTE_ETH_RSS_IPV6) 665 rss_types |= IONIC_RSS_TYPE_IPV6; 666 if (rss_conf->rss_hf & RTE_ETH_RSS_NONFRAG_IPV6_TCP) 667 rss_types |= IONIC_RSS_TYPE_IPV6_TCP; 668 if (rss_conf->rss_hf & RTE_ETH_RSS_NONFRAG_IPV6_UDP) 669 rss_types |= IONIC_RSS_TYPE_IPV6_UDP; 670 671 ionic_lif_rss_config(lif, rss_types, key, NULL); 672 } 673 674 return 0; 675 } 676 677 static int 678 ionic_dev_stats_get(struct rte_eth_dev *eth_dev, 679 struct rte_eth_stats *stats) 680 { 681 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 682 683 ionic_lif_get_stats(lif, stats); 684 685 return 0; 686 } 687 688 static int 689 ionic_dev_stats_reset(struct rte_eth_dev *eth_dev) 690 { 691 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 692 693 IONIC_PRINT_CALL(); 694 695 ionic_lif_reset_stats(lif); 696 697 return 0; 698 } 699 700 static int 701 ionic_dev_xstats_get_names(__rte_unused struct rte_eth_dev *eth_dev, 702 struct rte_eth_xstat_name *xstats_names, 703 __rte_unused unsigned int size) 704 { 705 unsigned int i; 706 707 if (xstats_names != NULL) { 708 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 709 snprintf(xstats_names[i].name, 710 sizeof(xstats_names[i].name), 711 "%s", rte_ionic_xstats_strings[i].name); 712 } 713 } 714 715 return IONIC_NB_HW_STATS; 716 } 717 718 static int 719 ionic_dev_xstats_get_names_by_id(struct rte_eth_dev *eth_dev, 720 const uint64_t *ids, struct rte_eth_xstat_name *xstats_names, 721 unsigned int limit) 722 { 723 struct rte_eth_xstat_name xstats_names_copy[IONIC_NB_HW_STATS]; 724 uint16_t i; 725 726 if (!ids) { 727 if (xstats_names != NULL) { 728 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 729 snprintf(xstats_names[i].name, 730 sizeof(xstats_names[i].name), 731 "%s", rte_ionic_xstats_strings[i].name); 732 } 733 } 734 735 return IONIC_NB_HW_STATS; 736 } 737 738 ionic_dev_xstats_get_names_by_id(eth_dev, NULL, xstats_names_copy, 739 IONIC_NB_HW_STATS); 740 741 for (i = 0; i < limit; i++) { 742 if (ids[i] >= IONIC_NB_HW_STATS) { 743 IONIC_PRINT(ERR, "id value isn't valid"); 744 return -1; 745 } 746 747 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 748 } 749 750 return limit; 751 } 752 753 static int 754 ionic_dev_xstats_get(struct rte_eth_dev *eth_dev, struct rte_eth_xstat *xstats, 755 unsigned int n) 756 { 757 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 758 struct ionic_lif_stats hw_stats; 759 uint16_t i; 760 761 if (n < IONIC_NB_HW_STATS) 762 return IONIC_NB_HW_STATS; 763 764 ionic_lif_get_hw_stats(lif, &hw_stats); 765 766 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 767 xstats[i].value = *(uint64_t *)(((char *)&hw_stats) + 768 rte_ionic_xstats_strings[i].offset); 769 xstats[i].id = i; 770 } 771 772 return IONIC_NB_HW_STATS; 773 } 774 775 static int 776 ionic_dev_xstats_get_by_id(struct rte_eth_dev *eth_dev, const uint64_t *ids, 777 uint64_t *values, unsigned int n) 778 { 779 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 780 struct ionic_lif_stats hw_stats; 781 uint64_t values_copy[IONIC_NB_HW_STATS]; 782 uint16_t i; 783 784 if (!ids) { 785 if (!ids && n < IONIC_NB_HW_STATS) 786 return IONIC_NB_HW_STATS; 787 788 ionic_lif_get_hw_stats(lif, &hw_stats); 789 790 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 791 values[i] = *(uint64_t *)(((char *)&hw_stats) + 792 rte_ionic_xstats_strings[i].offset); 793 } 794 795 return IONIC_NB_HW_STATS; 796 } 797 798 ionic_dev_xstats_get_by_id(eth_dev, NULL, values_copy, 799 IONIC_NB_HW_STATS); 800 801 for (i = 0; i < n; i++) { 802 if (ids[i] >= IONIC_NB_HW_STATS) { 803 IONIC_PRINT(ERR, "id value isn't valid"); 804 return -1; 805 } 806 807 values[i] = values_copy[ids[i]]; 808 } 809 810 return n; 811 } 812 813 static int 814 ionic_dev_xstats_reset(struct rte_eth_dev *eth_dev) 815 { 816 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 817 818 ionic_lif_reset_hw_stats(lif); 819 820 return 0; 821 } 822 823 static int 824 ionic_dev_configure(struct rte_eth_dev *eth_dev) 825 { 826 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 827 828 IONIC_PRINT_CALL(); 829 830 ionic_lif_configure(lif); 831 832 return 0; 833 } 834 835 static inline uint32_t 836 ionic_parse_link_speeds(uint16_t link_speeds) 837 { 838 if (link_speeds & RTE_ETH_LINK_SPEED_100G) 839 return 100000; 840 else if (link_speeds & RTE_ETH_LINK_SPEED_50G) 841 return 50000; 842 else if (link_speeds & RTE_ETH_LINK_SPEED_40G) 843 return 40000; 844 else if (link_speeds & RTE_ETH_LINK_SPEED_25G) 845 return 25000; 846 else if (link_speeds & RTE_ETH_LINK_SPEED_10G) 847 return 10000; 848 else 849 return 0; 850 } 851 852 /* 853 * Configure device link speed and setup link. 854 * It returns 0 on success. 855 */ 856 static int 857 ionic_dev_start(struct rte_eth_dev *eth_dev) 858 { 859 struct rte_eth_conf *dev_conf = ð_dev->data->dev_conf; 860 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 861 struct ionic_adapter *adapter = lif->adapter; 862 struct ionic_dev *idev = &adapter->idev; 863 uint32_t speed = 0, allowed_speeds; 864 uint8_t an_enable; 865 int err; 866 867 IONIC_PRINT_CALL(); 868 869 allowed_speeds = 870 RTE_ETH_LINK_SPEED_FIXED | 871 RTE_ETH_LINK_SPEED_10G | 872 RTE_ETH_LINK_SPEED_25G | 873 RTE_ETH_LINK_SPEED_40G | 874 RTE_ETH_LINK_SPEED_50G | 875 RTE_ETH_LINK_SPEED_100G; 876 877 if (dev_conf->link_speeds & ~allowed_speeds) { 878 IONIC_PRINT(ERR, "Invalid link setting"); 879 return -EINVAL; 880 } 881 882 if (dev_conf->lpbk_mode) 883 IONIC_PRINT(WARNING, "Loopback mode not supported"); 884 885 /* Re-set features in case SG flag was added in rx_queue_setup() */ 886 err = ionic_lif_set_features(lif); 887 if (err) { 888 IONIC_PRINT(ERR, "Cannot set LIF features: %d", err); 889 return err; 890 } 891 892 lif->frame_size = eth_dev->data->mtu + IONIC_ETH_OVERHEAD; 893 894 err = ionic_lif_change_mtu(lif, eth_dev->data->mtu); 895 if (err) { 896 IONIC_PRINT(ERR, "Cannot set LIF frame size %u: %d", 897 lif->frame_size, err); 898 return err; 899 } 900 901 err = ionic_lif_start(lif); 902 if (err) { 903 IONIC_PRINT(ERR, "Cannot start LIF: %d", err); 904 return err; 905 } 906 907 /* Configure link */ 908 an_enable = (dev_conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) == 0; 909 910 ionic_dev_cmd_port_autoneg(idev, an_enable); 911 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 912 if (err) 913 IONIC_PRINT(WARNING, "Failed to %s autonegotiation", 914 an_enable ? "enable" : "disable"); 915 916 if (!an_enable) 917 speed = ionic_parse_link_speeds(dev_conf->link_speeds); 918 if (speed) { 919 ionic_dev_cmd_port_speed(idev, speed); 920 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 921 if (err) 922 IONIC_PRINT(WARNING, "Failed to set link speed %u", 923 speed); 924 } 925 926 if (lif->hw_features & IONIC_ETH_HW_RX_SG) 927 eth_dev->rx_pkt_burst = &ionic_recv_pkts_sg; 928 else 929 eth_dev->rx_pkt_burst = &ionic_recv_pkts; 930 931 if (lif->hw_features & IONIC_ETH_HW_TX_SG) 932 eth_dev->tx_pkt_burst = &ionic_xmit_pkts_sg; 933 else 934 eth_dev->tx_pkt_burst = &ionic_xmit_pkts; 935 936 eth_dev->tx_pkt_prepare = &ionic_prep_pkts; 937 938 ionic_dev_link_update(eth_dev, 0); 939 940 return 0; 941 } 942 943 /* 944 * Stop device: disable rx and tx functions to allow for reconfiguring. 945 */ 946 static int 947 ionic_dev_stop(struct rte_eth_dev *eth_dev) 948 { 949 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 950 951 IONIC_PRINT_CALL(); 952 953 ionic_lif_stop(lif); 954 955 return 0; 956 } 957 958 /* 959 * Reset and stop device. 960 */ 961 static int 962 ionic_dev_close(struct rte_eth_dev *eth_dev) 963 { 964 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 965 struct ionic_adapter *adapter = lif->adapter; 966 967 IONIC_PRINT_CALL(); 968 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 969 return 0; 970 971 ionic_lif_stop(lif); 972 973 ionic_lif_free_queues(lif); 974 975 IONIC_PRINT(NOTICE, "Removing device %s", eth_dev->device->name); 976 if (adapter->intf->unconfigure_intr) 977 (*adapter->intf->unconfigure_intr)(adapter); 978 979 rte_eth_dev_destroy(eth_dev, eth_ionic_dev_uninit); 980 981 ionic_port_reset(adapter); 982 ionic_reset(adapter); 983 if (adapter->intf->unmap_bars) 984 (*adapter->intf->unmap_bars)(adapter); 985 986 rte_free(adapter); 987 988 return 0; 989 } 990 991 int 992 eth_ionic_dev_init(struct rte_eth_dev *eth_dev, void *init_params) 993 { 994 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 995 struct ionic_adapter *adapter = (struct ionic_adapter *)init_params; 996 int err; 997 998 IONIC_PRINT_CALL(); 999 1000 eth_dev->dev_ops = &ionic_eth_dev_ops; 1001 eth_dev->rx_descriptor_status = ionic_dev_rx_descriptor_status; 1002 eth_dev->tx_descriptor_status = ionic_dev_tx_descriptor_status; 1003 1004 /* Multi-process not supported, primary does initialization anyway */ 1005 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1006 return 0; 1007 1008 if (adapter->intf->copy_bus_info) 1009 (*adapter->intf->copy_bus_info)(adapter, eth_dev); 1010 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 1011 1012 lif->eth_dev = eth_dev; 1013 lif->adapter = adapter; 1014 adapter->lif = lif; 1015 1016 IONIC_PRINT(DEBUG, "Up to %u MAC addresses supported", 1017 adapter->max_mac_addrs); 1018 1019 /* Allocate memory for storing MAC addresses */ 1020 eth_dev->data->mac_addrs = rte_calloc("ionic", 1021 adapter->max_mac_addrs, 1022 RTE_ETHER_ADDR_LEN, 1023 RTE_CACHE_LINE_SIZE); 1024 if (eth_dev->data->mac_addrs == NULL) { 1025 IONIC_PRINT(ERR, "Failed to allocate %u bytes needed to " 1026 "store MAC addresses", 1027 RTE_ETHER_ADDR_LEN * adapter->max_mac_addrs); 1028 err = -ENOMEM; 1029 goto err; 1030 } 1031 1032 err = ionic_lif_alloc(lif); 1033 if (err) { 1034 IONIC_PRINT(ERR, "Cannot allocate LIFs: %d, aborting", 1035 err); 1036 goto err; 1037 } 1038 1039 err = ionic_lif_init(lif); 1040 if (err) { 1041 IONIC_PRINT(ERR, "Cannot init LIFs: %d, aborting", err); 1042 goto err_free_lif; 1043 } 1044 1045 /* Copy the MAC address */ 1046 rte_ether_addr_copy((struct rte_ether_addr *)lif->mac_addr, 1047 ð_dev->data->mac_addrs[0]); 1048 1049 IONIC_PRINT(DEBUG, "Port %u initialized", eth_dev->data->port_id); 1050 1051 return 0; 1052 1053 err_free_lif: 1054 ionic_lif_free(lif); 1055 err: 1056 return err; 1057 } 1058 1059 static int 1060 eth_ionic_dev_uninit(struct rte_eth_dev *eth_dev) 1061 { 1062 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 1063 struct ionic_adapter *adapter = lif->adapter; 1064 1065 IONIC_PRINT_CALL(); 1066 1067 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1068 return 0; 1069 1070 adapter->lif = NULL; 1071 1072 ionic_lif_deinit(lif); 1073 ionic_lif_free(lif); 1074 1075 if (!(lif->state & IONIC_LIF_F_FW_RESET)) 1076 ionic_lif_reset(lif); 1077 1078 return 0; 1079 } 1080 1081 int 1082 eth_ionic_dev_probe(void *bus_dev, struct rte_device *rte_dev, 1083 struct ionic_bars *bars, const struct ionic_dev_intf *intf, 1084 uint16_t device_id, uint16_t vendor_id) 1085 { 1086 char name[RTE_ETH_NAME_MAX_LEN]; 1087 struct ionic_adapter *adapter; 1088 struct ionic_hw *hw; 1089 unsigned long i; 1090 int err; 1091 1092 /* Check structs (trigger error at compilation time) */ 1093 ionic_struct_size_checks(); 1094 1095 /* Multi-process not supported */ 1096 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1097 err = -EPERM; 1098 goto err; 1099 } 1100 1101 adapter = rte_zmalloc("ionic", sizeof(*adapter), RTE_CACHE_LINE_SIZE); 1102 if (!adapter) { 1103 IONIC_PRINT(ERR, "OOM"); 1104 err = -ENOMEM; 1105 goto err; 1106 } 1107 1108 adapter->bus_dev = bus_dev; 1109 hw = &adapter->hw; 1110 1111 /* Vendor and Device ID need to be set before init of shared code */ 1112 hw->device_id = device_id; 1113 hw->vendor_id = vendor_id; 1114 1115 err = ionic_init_mac(hw); 1116 if (err != 0) { 1117 IONIC_PRINT(ERR, "Mac init failed: %d", err); 1118 err = -EIO; 1119 goto err_free_adapter; 1120 } 1121 1122 adapter->bars.num_bars = bars->num_bars; 1123 for (i = 0; i < bars->num_bars; i++) { 1124 adapter->bars.bar[i].vaddr = bars->bar[i].vaddr; 1125 adapter->bars.bar[i].bus_addr = bars->bar[i].bus_addr; 1126 adapter->bars.bar[i].len = bars->bar[i].len; 1127 } 1128 1129 if (intf->setup == NULL) { 1130 IONIC_PRINT(ERR, "Device setup function is mandatory"); 1131 goto err_free_adapter; 1132 } 1133 1134 adapter->intf = intf; 1135 1136 /* Parse device arguments */ 1137 if (adapter->intf->devargs) { 1138 err = (*adapter->intf->devargs)(adapter, rte_dev->devargs); 1139 if (err) { 1140 IONIC_PRINT(ERR, "Cannot parse device arguments"); 1141 goto err_free_adapter; 1142 } 1143 } 1144 1145 /* Discover ionic dev resources */ 1146 err = ionic_setup(adapter); 1147 if (err) { 1148 IONIC_PRINT(ERR, "Cannot setup device: %d, aborting", err); 1149 goto err_free_adapter; 1150 } 1151 1152 err = ionic_identify(adapter); 1153 if (err) { 1154 IONIC_PRINT(ERR, "Cannot identify device: %d, aborting", 1155 err); 1156 goto err_free_adapter; 1157 } 1158 1159 err = ionic_init(adapter); 1160 if (err) { 1161 IONIC_PRINT(ERR, "Cannot init device: %d, aborting", err); 1162 goto err_free_adapter; 1163 } 1164 1165 /* Configure the ports */ 1166 err = ionic_port_identify(adapter); 1167 if (err) { 1168 IONIC_PRINT(ERR, "Cannot identify port: %d, aborting", 1169 err); 1170 goto err_free_adapter; 1171 } 1172 1173 err = ionic_port_init(adapter); 1174 if (err) { 1175 IONIC_PRINT(ERR, "Cannot init port: %d, aborting", err); 1176 goto err_free_adapter; 1177 } 1178 1179 /* Configure LIFs */ 1180 err = ionic_lif_identify(adapter); 1181 if (err) { 1182 IONIC_PRINT(ERR, "Cannot identify lif: %d, aborting", err); 1183 goto err_free_adapter; 1184 } 1185 1186 /* Allocate and init LIFs */ 1187 err = ionic_lifs_size(adapter); 1188 if (err) { 1189 IONIC_PRINT(ERR, "Cannot size LIFs: %d, aborting", err); 1190 goto err_free_adapter; 1191 } 1192 1193 adapter->max_mac_addrs = 1194 rte_le_to_cpu_32(adapter->ident.lif.eth.max_ucast_filters); 1195 1196 if (rte_le_to_cpu_32(adapter->ident.dev.nlifs) != 1) { 1197 IONIC_PRINT(ERR, "Unexpected request for %d LIFs", 1198 rte_le_to_cpu_32(adapter->ident.dev.nlifs)); 1199 goto err_free_adapter; 1200 } 1201 1202 snprintf(name, sizeof(name), "%s_lif", rte_dev->name); 1203 err = rte_eth_dev_create(rte_dev, name, sizeof(struct ionic_lif), 1204 NULL, NULL, eth_ionic_dev_init, adapter); 1205 if (err) { 1206 IONIC_PRINT(ERR, "Cannot create eth device for %s", name); 1207 goto err_free_adapter; 1208 } 1209 1210 if (adapter->intf->configure_intr) { 1211 err = (*adapter->intf->configure_intr)(adapter); 1212 if (err) { 1213 IONIC_PRINT(ERR, "Failed to configure interrupts"); 1214 goto err_free_adapter; 1215 } 1216 } 1217 1218 return 0; 1219 1220 err_free_adapter: 1221 rte_free(adapter); 1222 err: 1223 return err; 1224 } 1225 1226 int 1227 eth_ionic_dev_remove(struct rte_device *rte_dev) 1228 { 1229 char name[RTE_ETH_NAME_MAX_LEN]; 1230 struct rte_eth_dev *eth_dev; 1231 1232 /* Adapter lookup is using the eth_dev name */ 1233 snprintf(name, sizeof(name), "%s_lif", rte_dev->name); 1234 1235 eth_dev = rte_eth_dev_allocated(name); 1236 if (eth_dev) 1237 ionic_dev_close(eth_dev); 1238 else 1239 IONIC_PRINT(DEBUG, "Cannot find device %s", rte_dev->name); 1240 1241 return 0; 1242 } 1243 1244 RTE_LOG_REGISTER_DEFAULT(ionic_logtype, NOTICE); 1245