1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) 2 * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved. 3 */ 4 5 #include <rte_pci.h> 6 #include <rte_bus_pci.h> 7 #include <rte_ethdev.h> 8 #include <ethdev_driver.h> 9 #include <rte_malloc.h> 10 #include <ethdev_pci.h> 11 12 #include "ionic_logs.h" 13 #include "ionic.h" 14 #include "ionic_dev.h" 15 #include "ionic_mac_api.h" 16 #include "ionic_lif.h" 17 #include "ionic_ethdev.h" 18 #include "ionic_rxtx.h" 19 20 static int eth_ionic_dev_init(struct rte_eth_dev *eth_dev, void *init_params); 21 static int eth_ionic_dev_uninit(struct rte_eth_dev *eth_dev); 22 static int ionic_dev_info_get(struct rte_eth_dev *eth_dev, 23 struct rte_eth_dev_info *dev_info); 24 static int ionic_dev_configure(struct rte_eth_dev *dev); 25 static int ionic_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 26 static int ionic_dev_start(struct rte_eth_dev *dev); 27 static int ionic_dev_stop(struct rte_eth_dev *dev); 28 static int ionic_dev_close(struct rte_eth_dev *dev); 29 static int ionic_dev_set_link_up(struct rte_eth_dev *dev); 30 static int ionic_dev_set_link_down(struct rte_eth_dev *dev); 31 static int ionic_flow_ctrl_get(struct rte_eth_dev *eth_dev, 32 struct rte_eth_fc_conf *fc_conf); 33 static int ionic_flow_ctrl_set(struct rte_eth_dev *eth_dev, 34 struct rte_eth_fc_conf *fc_conf); 35 static int ionic_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask); 36 static int ionic_dev_rss_reta_update(struct rte_eth_dev *eth_dev, 37 struct rte_eth_rss_reta_entry64 *reta_conf, uint16_t reta_size); 38 static int ionic_dev_rss_reta_query(struct rte_eth_dev *eth_dev, 39 struct rte_eth_rss_reta_entry64 *reta_conf, uint16_t reta_size); 40 static int ionic_dev_rss_hash_conf_get(struct rte_eth_dev *eth_dev, 41 struct rte_eth_rss_conf *rss_conf); 42 static int ionic_dev_rss_hash_update(struct rte_eth_dev *eth_dev, 43 struct rte_eth_rss_conf *rss_conf); 44 static int ionic_dev_stats_get(struct rte_eth_dev *eth_dev, 45 struct rte_eth_stats *stats); 46 static int ionic_dev_stats_reset(struct rte_eth_dev *eth_dev); 47 static int ionic_dev_xstats_get(struct rte_eth_dev *dev, 48 struct rte_eth_xstat *xstats, unsigned int n); 49 static int ionic_dev_xstats_get_by_id(struct rte_eth_dev *dev, 50 const uint64_t *ids, uint64_t *values, unsigned int n); 51 static int ionic_dev_xstats_reset(struct rte_eth_dev *dev); 52 static int ionic_dev_xstats_get_names(struct rte_eth_dev *dev, 53 struct rte_eth_xstat_name *xstats_names, unsigned int size); 54 static int ionic_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, 55 const uint64_t *ids, struct rte_eth_xstat_name *xstats_names, 56 unsigned int limit); 57 static int ionic_dev_fw_version_get(struct rte_eth_dev *eth_dev, 58 char *fw_version, size_t fw_size); 59 60 static const struct rte_pci_id pci_id_ionic_map[] = { 61 { RTE_PCI_DEVICE(IONIC_PENSANDO_VENDOR_ID, IONIC_DEV_ID_ETH_PF) }, 62 { RTE_PCI_DEVICE(IONIC_PENSANDO_VENDOR_ID, IONIC_DEV_ID_ETH_VF) }, 63 { RTE_PCI_DEVICE(IONIC_PENSANDO_VENDOR_ID, IONIC_DEV_ID_ETH_MGMT) }, 64 { .vendor_id = 0, /* sentinel */ }, 65 }; 66 67 static const struct rte_eth_desc_lim rx_desc_lim = { 68 .nb_max = IONIC_MAX_RING_DESC, 69 .nb_min = IONIC_MIN_RING_DESC, 70 .nb_align = 1, 71 }; 72 73 static const struct rte_eth_desc_lim tx_desc_lim_v1 = { 74 .nb_max = IONIC_MAX_RING_DESC, 75 .nb_min = IONIC_MIN_RING_DESC, 76 .nb_align = 1, 77 .nb_seg_max = IONIC_TX_MAX_SG_ELEMS_V1 + 1, 78 .nb_mtu_seg_max = IONIC_TX_MAX_SG_ELEMS_V1 + 1, 79 }; 80 81 static const struct eth_dev_ops ionic_eth_dev_ops = { 82 .dev_infos_get = ionic_dev_info_get, 83 .dev_configure = ionic_dev_configure, 84 .mtu_set = ionic_dev_mtu_set, 85 .dev_start = ionic_dev_start, 86 .dev_stop = ionic_dev_stop, 87 .dev_close = ionic_dev_close, 88 .link_update = ionic_dev_link_update, 89 .dev_set_link_up = ionic_dev_set_link_up, 90 .dev_set_link_down = ionic_dev_set_link_down, 91 .mac_addr_add = ionic_dev_add_mac, 92 .mac_addr_remove = ionic_dev_remove_mac, 93 .mac_addr_set = ionic_dev_set_mac, 94 .vlan_filter_set = ionic_dev_vlan_filter_set, 95 .promiscuous_enable = ionic_dev_promiscuous_enable, 96 .promiscuous_disable = ionic_dev_promiscuous_disable, 97 .allmulticast_enable = ionic_dev_allmulticast_enable, 98 .allmulticast_disable = ionic_dev_allmulticast_disable, 99 .flow_ctrl_get = ionic_flow_ctrl_get, 100 .flow_ctrl_set = ionic_flow_ctrl_set, 101 .rxq_info_get = ionic_rxq_info_get, 102 .txq_info_get = ionic_txq_info_get, 103 .rx_queue_setup = ionic_dev_rx_queue_setup, 104 .rx_queue_release = ionic_dev_rx_queue_release, 105 .rx_queue_start = ionic_dev_rx_queue_start, 106 .rx_queue_stop = ionic_dev_rx_queue_stop, 107 .tx_queue_setup = ionic_dev_tx_queue_setup, 108 .tx_queue_release = ionic_dev_tx_queue_release, 109 .tx_queue_start = ionic_dev_tx_queue_start, 110 .tx_queue_stop = ionic_dev_tx_queue_stop, 111 .vlan_offload_set = ionic_vlan_offload_set, 112 .reta_update = ionic_dev_rss_reta_update, 113 .reta_query = ionic_dev_rss_reta_query, 114 .rss_hash_conf_get = ionic_dev_rss_hash_conf_get, 115 .rss_hash_update = ionic_dev_rss_hash_update, 116 .stats_get = ionic_dev_stats_get, 117 .stats_reset = ionic_dev_stats_reset, 118 .xstats_get = ionic_dev_xstats_get, 119 .xstats_get_by_id = ionic_dev_xstats_get_by_id, 120 .xstats_reset = ionic_dev_xstats_reset, 121 .xstats_get_names = ionic_dev_xstats_get_names, 122 .xstats_get_names_by_id = ionic_dev_xstats_get_names_by_id, 123 .fw_version_get = ionic_dev_fw_version_get, 124 }; 125 126 struct rte_ionic_xstats_name_off { 127 char name[RTE_ETH_XSTATS_NAME_SIZE]; 128 unsigned int offset; 129 }; 130 131 static const struct rte_ionic_xstats_name_off rte_ionic_xstats_strings[] = { 132 /* RX */ 133 {"rx_ucast_bytes", offsetof(struct ionic_lif_stats, 134 rx_ucast_bytes)}, 135 {"rx_ucast_packets", offsetof(struct ionic_lif_stats, 136 rx_ucast_packets)}, 137 {"rx_mcast_bytes", offsetof(struct ionic_lif_stats, 138 rx_mcast_bytes)}, 139 {"rx_mcast_packets", offsetof(struct ionic_lif_stats, 140 rx_mcast_packets)}, 141 {"rx_bcast_bytes", offsetof(struct ionic_lif_stats, 142 rx_bcast_bytes)}, 143 {"rx_bcast_packets", offsetof(struct ionic_lif_stats, 144 rx_bcast_packets)}, 145 /* RX drops */ 146 {"rx_ucast_drop_bytes", offsetof(struct ionic_lif_stats, 147 rx_ucast_drop_bytes)}, 148 {"rx_ucast_drop_packets", offsetof(struct ionic_lif_stats, 149 rx_ucast_drop_packets)}, 150 {"rx_mcast_drop_bytes", offsetof(struct ionic_lif_stats, 151 rx_mcast_drop_bytes)}, 152 {"rx_mcast_drop_packets", offsetof(struct ionic_lif_stats, 153 rx_mcast_drop_packets)}, 154 {"rx_bcast_drop_bytes", offsetof(struct ionic_lif_stats, 155 rx_bcast_drop_bytes)}, 156 {"rx_bcast_drop_packets", offsetof(struct ionic_lif_stats, 157 rx_bcast_drop_packets)}, 158 {"rx_dma_error", offsetof(struct ionic_lif_stats, 159 rx_dma_error)}, 160 /* TX */ 161 {"tx_ucast_bytes", offsetof(struct ionic_lif_stats, 162 tx_ucast_bytes)}, 163 {"tx_ucast_packets", offsetof(struct ionic_lif_stats, 164 tx_ucast_packets)}, 165 {"tx_mcast_bytes", offsetof(struct ionic_lif_stats, 166 tx_mcast_bytes)}, 167 {"tx_mcast_packets", offsetof(struct ionic_lif_stats, 168 tx_mcast_packets)}, 169 {"tx_bcast_bytes", offsetof(struct ionic_lif_stats, 170 tx_bcast_bytes)}, 171 {"tx_bcast_packets", offsetof(struct ionic_lif_stats, 172 tx_bcast_packets)}, 173 /* TX drops */ 174 {"tx_ucast_drop_bytes", offsetof(struct ionic_lif_stats, 175 tx_ucast_drop_bytes)}, 176 {"tx_ucast_drop_packets", offsetof(struct ionic_lif_stats, 177 tx_ucast_drop_packets)}, 178 {"tx_mcast_drop_bytes", offsetof(struct ionic_lif_stats, 179 tx_mcast_drop_bytes)}, 180 {"tx_mcast_drop_packets", offsetof(struct ionic_lif_stats, 181 tx_mcast_drop_packets)}, 182 {"tx_bcast_drop_bytes", offsetof(struct ionic_lif_stats, 183 tx_bcast_drop_bytes)}, 184 {"tx_bcast_drop_packets", offsetof(struct ionic_lif_stats, 185 tx_bcast_drop_packets)}, 186 {"tx_dma_error", offsetof(struct ionic_lif_stats, 187 tx_dma_error)}, 188 /* Rx Queue/Ring drops */ 189 {"rx_queue_disabled", offsetof(struct ionic_lif_stats, 190 rx_queue_disabled)}, 191 {"rx_queue_empty", offsetof(struct ionic_lif_stats, 192 rx_queue_empty)}, 193 {"rx_queue_error", offsetof(struct ionic_lif_stats, 194 rx_queue_error)}, 195 {"rx_desc_fetch_error", offsetof(struct ionic_lif_stats, 196 rx_desc_fetch_error)}, 197 {"rx_desc_data_error", offsetof(struct ionic_lif_stats, 198 rx_desc_data_error)}, 199 /* Tx Queue/Ring drops */ 200 {"tx_queue_disabled", offsetof(struct ionic_lif_stats, 201 tx_queue_disabled)}, 202 {"tx_queue_error", offsetof(struct ionic_lif_stats, 203 tx_queue_error)}, 204 {"tx_desc_fetch_error", offsetof(struct ionic_lif_stats, 205 tx_desc_fetch_error)}, 206 {"tx_desc_data_error", offsetof(struct ionic_lif_stats, 207 tx_desc_data_error)}, 208 }; 209 210 #define IONIC_NB_HW_STATS RTE_DIM(rte_ionic_xstats_strings) 211 212 static int 213 ionic_dev_fw_version_get(struct rte_eth_dev *eth_dev, 214 char *fw_version, size_t fw_size) 215 { 216 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 217 struct ionic_adapter *adapter = lif->adapter; 218 int ret; 219 220 ret = snprintf(fw_version, fw_size, "%s", 221 adapter->fw_version); 222 if (ret < 0) 223 return -EINVAL; 224 225 ret += 1; /* add the size of '\0' */ 226 if (fw_size < (size_t)ret) 227 return ret; 228 else 229 return 0; 230 } 231 232 /* 233 * Set device link up, enable tx. 234 */ 235 static int 236 ionic_dev_set_link_up(struct rte_eth_dev *eth_dev) 237 { 238 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 239 int err; 240 241 IONIC_PRINT_CALL(); 242 243 err = ionic_lif_start(lif); 244 if (err) 245 IONIC_PRINT(ERR, "Could not start lif to set link up"); 246 247 ionic_dev_link_update(lif->eth_dev, 0); 248 249 return err; 250 } 251 252 /* 253 * Set device link down, disable tx. 254 */ 255 static int 256 ionic_dev_set_link_down(struct rte_eth_dev *eth_dev) 257 { 258 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 259 260 IONIC_PRINT_CALL(); 261 262 ionic_lif_stop(lif); 263 264 ionic_dev_link_update(lif->eth_dev, 0); 265 266 return 0; 267 } 268 269 int 270 ionic_dev_link_update(struct rte_eth_dev *eth_dev, 271 int wait_to_complete __rte_unused) 272 { 273 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 274 struct ionic_adapter *adapter = lif->adapter; 275 struct rte_eth_link link; 276 277 IONIC_PRINT_CALL(); 278 279 /* Initialize */ 280 memset(&link, 0, sizeof(link)); 281 282 if (adapter->idev.port_info->config.an_enable) { 283 link.link_autoneg = ETH_LINK_AUTONEG; 284 } 285 286 if (!adapter->link_up || 287 !(lif->state & IONIC_LIF_F_UP)) { 288 /* Interface is down */ 289 link.link_status = ETH_LINK_DOWN; 290 link.link_duplex = ETH_LINK_HALF_DUPLEX; 291 link.link_speed = ETH_SPEED_NUM_NONE; 292 } else { 293 /* Interface is up */ 294 link.link_status = ETH_LINK_UP; 295 link.link_duplex = ETH_LINK_FULL_DUPLEX; 296 switch (adapter->link_speed) { 297 case 10000: 298 link.link_speed = ETH_SPEED_NUM_10G; 299 break; 300 case 25000: 301 link.link_speed = ETH_SPEED_NUM_25G; 302 break; 303 case 40000: 304 link.link_speed = ETH_SPEED_NUM_40G; 305 break; 306 case 50000: 307 link.link_speed = ETH_SPEED_NUM_50G; 308 break; 309 case 100000: 310 link.link_speed = ETH_SPEED_NUM_100G; 311 break; 312 default: 313 link.link_speed = ETH_SPEED_NUM_NONE; 314 break; 315 } 316 } 317 318 return rte_eth_linkstatus_set(eth_dev, &link); 319 } 320 321 /** 322 * Interrupt handler triggered by NIC for handling 323 * specific interrupt. 324 * 325 * @param param 326 * The address of parameter registered before. 327 * 328 * @return 329 * void 330 */ 331 static void 332 ionic_dev_interrupt_handler(void *param) 333 { 334 struct ionic_adapter *adapter = (struct ionic_adapter *)param; 335 336 IONIC_PRINT(DEBUG, "->"); 337 338 if (adapter->lif) 339 ionic_notifyq_handler(adapter->lif, -1); 340 } 341 342 static int 343 ionic_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) 344 { 345 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 346 uint32_t max_frame_size; 347 int err; 348 349 IONIC_PRINT_CALL(); 350 351 /* 352 * Note: mtu check against IONIC_MIN_MTU, IONIC_MAX_MTU 353 * is done by the the API. 354 */ 355 356 /* 357 * Max frame size is MTU + Ethernet header + VLAN + QinQ 358 * (plus ETHER_CRC_LEN if the adapter is able to keep CRC) 359 */ 360 max_frame_size = mtu + RTE_ETHER_HDR_LEN + 4 + 4; 361 362 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len < max_frame_size) 363 return -EINVAL; 364 365 err = ionic_lif_change_mtu(lif, mtu); 366 if (err) 367 return err; 368 369 return 0; 370 } 371 372 static int 373 ionic_dev_info_get(struct rte_eth_dev *eth_dev, 374 struct rte_eth_dev_info *dev_info) 375 { 376 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 377 struct ionic_adapter *adapter = lif->adapter; 378 struct ionic_identity *ident = &adapter->ident; 379 union ionic_lif_config *cfg = &ident->lif.eth.config; 380 381 IONIC_PRINT_CALL(); 382 383 dev_info->max_rx_queues = (uint16_t) 384 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_RXQ]); 385 dev_info->max_tx_queues = (uint16_t) 386 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ]); 387 388 /* Also add ETHER_CRC_LEN if the adapter is able to keep CRC */ 389 dev_info->min_rx_bufsize = IONIC_MIN_MTU + RTE_ETHER_HDR_LEN; 390 dev_info->max_rx_pktlen = IONIC_MAX_MTU + RTE_ETHER_HDR_LEN; 391 dev_info->max_mac_addrs = adapter->max_mac_addrs; 392 dev_info->min_mtu = IONIC_MIN_MTU; 393 dev_info->max_mtu = IONIC_MAX_MTU; 394 395 dev_info->hash_key_size = IONIC_RSS_HASH_KEY_SIZE; 396 dev_info->reta_size = rte_le_to_cpu_16(ident->lif.eth.rss_ind_tbl_sz); 397 dev_info->flow_type_rss_offloads = IONIC_ETH_RSS_OFFLOAD_ALL; 398 399 dev_info->speed_capa = 400 ETH_LINK_SPEED_10G | 401 ETH_LINK_SPEED_25G | 402 ETH_LINK_SPEED_40G | 403 ETH_LINK_SPEED_50G | 404 ETH_LINK_SPEED_100G; 405 406 /* 407 * Per-queue capabilities 408 * RTE does not support disabling a feature on a queue if it is 409 * enabled globally on the device. Thus the driver does not advertise 410 * capabilities like DEV_TX_OFFLOAD_IPV4_CKSUM as per-queue even 411 * though the driver would be otherwise capable of disabling it on 412 * a per-queue basis. 413 */ 414 415 dev_info->rx_queue_offload_capa = 0; 416 dev_info->tx_queue_offload_capa = 0; 417 418 /* 419 * Per-port capabilities 420 * See ionic_set_features to request and check supported features 421 */ 422 423 dev_info->rx_offload_capa = dev_info->rx_queue_offload_capa | 424 DEV_RX_OFFLOAD_IPV4_CKSUM | 425 DEV_RX_OFFLOAD_UDP_CKSUM | 426 DEV_RX_OFFLOAD_TCP_CKSUM | 427 DEV_RX_OFFLOAD_JUMBO_FRAME | 428 DEV_RX_OFFLOAD_VLAN_FILTER | 429 DEV_RX_OFFLOAD_VLAN_STRIP | 430 DEV_RX_OFFLOAD_SCATTER | 431 DEV_RX_OFFLOAD_RSS_HASH | 432 0; 433 434 dev_info->tx_offload_capa = dev_info->tx_queue_offload_capa | 435 DEV_TX_OFFLOAD_IPV4_CKSUM | 436 DEV_TX_OFFLOAD_UDP_CKSUM | 437 DEV_TX_OFFLOAD_TCP_CKSUM | 438 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 439 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM | 440 DEV_TX_OFFLOAD_MULTI_SEGS | 441 DEV_TX_OFFLOAD_TCP_TSO | 442 DEV_TX_OFFLOAD_VLAN_INSERT | 443 0; 444 445 dev_info->rx_desc_lim = rx_desc_lim; 446 dev_info->tx_desc_lim = tx_desc_lim_v1; 447 448 /* Driver-preferred Rx/Tx parameters */ 449 dev_info->default_rxportconf.burst_size = 32; 450 dev_info->default_txportconf.burst_size = 32; 451 dev_info->default_rxportconf.nb_queues = 1; 452 dev_info->default_txportconf.nb_queues = 1; 453 dev_info->default_rxportconf.ring_size = IONIC_DEF_TXRX_DESC; 454 dev_info->default_txportconf.ring_size = IONIC_DEF_TXRX_DESC; 455 456 dev_info->default_rxconf = (struct rte_eth_rxconf) { 457 /* Packets are always dropped if no desc are available */ 458 .rx_drop_en = 1, 459 }; 460 461 return 0; 462 } 463 464 static int 465 ionic_flow_ctrl_get(struct rte_eth_dev *eth_dev, 466 struct rte_eth_fc_conf *fc_conf) 467 { 468 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 469 struct ionic_adapter *adapter = lif->adapter; 470 struct ionic_dev *idev = &adapter->idev; 471 472 if (idev->port_info) { 473 /* Flow control autoneg not supported */ 474 fc_conf->autoneg = 0; 475 476 if (idev->port_info->config.pause_type) 477 fc_conf->mode = RTE_FC_FULL; 478 else 479 fc_conf->mode = RTE_FC_NONE; 480 } 481 482 return 0; 483 } 484 485 static int 486 ionic_flow_ctrl_set(struct rte_eth_dev *eth_dev, 487 struct rte_eth_fc_conf *fc_conf) 488 { 489 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 490 struct ionic_adapter *adapter = lif->adapter; 491 struct ionic_dev *idev = &adapter->idev; 492 uint8_t pause_type = IONIC_PORT_PAUSE_TYPE_NONE; 493 int err; 494 495 if (fc_conf->autoneg) { 496 IONIC_PRINT(WARNING, "Flow control autoneg not supported"); 497 return -ENOTSUP; 498 } 499 500 switch (fc_conf->mode) { 501 case RTE_FC_NONE: 502 pause_type = IONIC_PORT_PAUSE_TYPE_NONE; 503 break; 504 case RTE_FC_FULL: 505 pause_type = IONIC_PORT_PAUSE_TYPE_LINK; 506 break; 507 case RTE_FC_RX_PAUSE: 508 case RTE_FC_TX_PAUSE: 509 return -ENOTSUP; 510 } 511 512 ionic_dev_cmd_port_pause(idev, pause_type); 513 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 514 if (err) 515 IONIC_PRINT(WARNING, "Failed to configure flow control"); 516 517 return err; 518 } 519 520 static int 521 ionic_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask) 522 { 523 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 524 525 ionic_lif_configure_vlan_offload(lif, mask); 526 527 ionic_lif_set_features(lif); 528 529 return 0; 530 } 531 532 static int 533 ionic_dev_rss_reta_update(struct rte_eth_dev *eth_dev, 534 struct rte_eth_rss_reta_entry64 *reta_conf, 535 uint16_t reta_size) 536 { 537 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 538 struct ionic_adapter *adapter = lif->adapter; 539 struct ionic_identity *ident = &adapter->ident; 540 uint32_t i, j, index, num; 541 uint16_t tbl_sz = rte_le_to_cpu_16(ident->lif.eth.rss_ind_tbl_sz); 542 543 IONIC_PRINT_CALL(); 544 545 if (!lif->rss_ind_tbl) { 546 IONIC_PRINT(ERR, "RSS RETA not initialized, " 547 "can't update the table"); 548 return -EINVAL; 549 } 550 551 if (reta_size != tbl_sz) { 552 IONIC_PRINT(ERR, "The size of hash lookup table configured " 553 "(%d) does not match the number hardware can support " 554 "(%d)", 555 reta_size, tbl_sz); 556 return -EINVAL; 557 } 558 559 num = tbl_sz / RTE_RETA_GROUP_SIZE; 560 561 for (i = 0; i < num; i++) { 562 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++) { 563 if (reta_conf[i].mask & ((uint64_t)1 << j)) { 564 index = (i * RTE_RETA_GROUP_SIZE) + j; 565 lif->rss_ind_tbl[index] = reta_conf[i].reta[j]; 566 } 567 } 568 } 569 570 return ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL); 571 } 572 573 static int 574 ionic_dev_rss_reta_query(struct rte_eth_dev *eth_dev, 575 struct rte_eth_rss_reta_entry64 *reta_conf, 576 uint16_t reta_size) 577 { 578 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 579 struct ionic_adapter *adapter = lif->adapter; 580 struct ionic_identity *ident = &adapter->ident; 581 int i, num; 582 uint16_t tbl_sz = rte_le_to_cpu_16(ident->lif.eth.rss_ind_tbl_sz); 583 584 IONIC_PRINT_CALL(); 585 586 if (reta_size != tbl_sz) { 587 IONIC_PRINT(ERR, "The size of hash lookup table configured " 588 "(%d) does not match the number hardware can support " 589 "(%d)", 590 reta_size, tbl_sz); 591 return -EINVAL; 592 } 593 594 if (!lif->rss_ind_tbl) { 595 IONIC_PRINT(ERR, "RSS RETA has not been built yet"); 596 return -EINVAL; 597 } 598 599 num = reta_size / RTE_RETA_GROUP_SIZE; 600 601 for (i = 0; i < num; i++) { 602 memcpy(reta_conf->reta, 603 &lif->rss_ind_tbl[i * RTE_RETA_GROUP_SIZE], 604 RTE_RETA_GROUP_SIZE); 605 reta_conf++; 606 } 607 608 return 0; 609 } 610 611 static int 612 ionic_dev_rss_hash_conf_get(struct rte_eth_dev *eth_dev, 613 struct rte_eth_rss_conf *rss_conf) 614 { 615 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 616 uint64_t rss_hf = 0; 617 618 IONIC_PRINT_CALL(); 619 620 if (!lif->rss_ind_tbl) { 621 IONIC_PRINT(NOTICE, "RSS not enabled"); 622 return 0; 623 } 624 625 /* Get key value (if not null, rss_key is 40-byte) */ 626 if (rss_conf->rss_key != NULL && 627 rss_conf->rss_key_len >= IONIC_RSS_HASH_KEY_SIZE) 628 memcpy(rss_conf->rss_key, lif->rss_hash_key, 629 IONIC_RSS_HASH_KEY_SIZE); 630 631 if (lif->rss_types & IONIC_RSS_TYPE_IPV4) 632 rss_hf |= ETH_RSS_IPV4; 633 if (lif->rss_types & IONIC_RSS_TYPE_IPV4_TCP) 634 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP; 635 if (lif->rss_types & IONIC_RSS_TYPE_IPV4_UDP) 636 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP; 637 if (lif->rss_types & IONIC_RSS_TYPE_IPV6) 638 rss_hf |= ETH_RSS_IPV6; 639 if (lif->rss_types & IONIC_RSS_TYPE_IPV6_TCP) 640 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP; 641 if (lif->rss_types & IONIC_RSS_TYPE_IPV6_UDP) 642 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP; 643 644 rss_conf->rss_hf = rss_hf; 645 646 return 0; 647 } 648 649 static int 650 ionic_dev_rss_hash_update(struct rte_eth_dev *eth_dev, 651 struct rte_eth_rss_conf *rss_conf) 652 { 653 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 654 uint32_t rss_types = 0; 655 uint8_t *key = NULL; 656 657 IONIC_PRINT_CALL(); 658 659 if (rss_conf->rss_key) 660 key = rss_conf->rss_key; 661 662 if ((rss_conf->rss_hf & IONIC_ETH_RSS_OFFLOAD_ALL) == 0) { 663 /* 664 * Can't disable rss through hash flags, 665 * if it is enabled by default during init 666 */ 667 if (lif->rss_ind_tbl) 668 return -EINVAL; 669 } else { 670 /* Can't enable rss if disabled by default during init */ 671 if (!lif->rss_ind_tbl) 672 return -EINVAL; 673 674 if (rss_conf->rss_hf & ETH_RSS_IPV4) 675 rss_types |= IONIC_RSS_TYPE_IPV4; 676 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) 677 rss_types |= IONIC_RSS_TYPE_IPV4_TCP; 678 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) 679 rss_types |= IONIC_RSS_TYPE_IPV4_UDP; 680 if (rss_conf->rss_hf & ETH_RSS_IPV6) 681 rss_types |= IONIC_RSS_TYPE_IPV6; 682 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) 683 rss_types |= IONIC_RSS_TYPE_IPV6_TCP; 684 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) 685 rss_types |= IONIC_RSS_TYPE_IPV6_UDP; 686 687 ionic_lif_rss_config(lif, rss_types, key, NULL); 688 } 689 690 return 0; 691 } 692 693 static int 694 ionic_dev_stats_get(struct rte_eth_dev *eth_dev, 695 struct rte_eth_stats *stats) 696 { 697 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 698 699 ionic_lif_get_stats(lif, stats); 700 701 return 0; 702 } 703 704 static int 705 ionic_dev_stats_reset(struct rte_eth_dev *eth_dev) 706 { 707 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 708 709 IONIC_PRINT_CALL(); 710 711 ionic_lif_reset_stats(lif); 712 713 return 0; 714 } 715 716 static int 717 ionic_dev_xstats_get_names(__rte_unused struct rte_eth_dev *eth_dev, 718 struct rte_eth_xstat_name *xstats_names, 719 __rte_unused unsigned int size) 720 { 721 unsigned int i; 722 723 if (xstats_names != NULL) { 724 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 725 snprintf(xstats_names[i].name, 726 sizeof(xstats_names[i].name), 727 "%s", rte_ionic_xstats_strings[i].name); 728 } 729 } 730 731 return IONIC_NB_HW_STATS; 732 } 733 734 static int 735 ionic_dev_xstats_get_names_by_id(struct rte_eth_dev *eth_dev, 736 const uint64_t *ids, struct rte_eth_xstat_name *xstats_names, 737 unsigned int limit) 738 { 739 struct rte_eth_xstat_name xstats_names_copy[IONIC_NB_HW_STATS]; 740 uint16_t i; 741 742 if (!ids) { 743 if (xstats_names != NULL) { 744 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 745 snprintf(xstats_names[i].name, 746 sizeof(xstats_names[i].name), 747 "%s", rte_ionic_xstats_strings[i].name); 748 } 749 } 750 751 return IONIC_NB_HW_STATS; 752 } 753 754 ionic_dev_xstats_get_names_by_id(eth_dev, NULL, xstats_names_copy, 755 IONIC_NB_HW_STATS); 756 757 for (i = 0; i < limit; i++) { 758 if (ids[i] >= IONIC_NB_HW_STATS) { 759 IONIC_PRINT(ERR, "id value isn't valid"); 760 return -1; 761 } 762 763 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 764 } 765 766 return limit; 767 } 768 769 static int 770 ionic_dev_xstats_get(struct rte_eth_dev *eth_dev, struct rte_eth_xstat *xstats, 771 unsigned int n) 772 { 773 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 774 struct ionic_lif_stats hw_stats; 775 uint16_t i; 776 777 if (n < IONIC_NB_HW_STATS) 778 return IONIC_NB_HW_STATS; 779 780 ionic_lif_get_hw_stats(lif, &hw_stats); 781 782 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 783 xstats[i].value = *(uint64_t *)(((char *)&hw_stats) + 784 rte_ionic_xstats_strings[i].offset); 785 xstats[i].id = i; 786 } 787 788 return IONIC_NB_HW_STATS; 789 } 790 791 static int 792 ionic_dev_xstats_get_by_id(struct rte_eth_dev *eth_dev, const uint64_t *ids, 793 uint64_t *values, unsigned int n) 794 { 795 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 796 struct ionic_lif_stats hw_stats; 797 uint64_t values_copy[IONIC_NB_HW_STATS]; 798 uint16_t i; 799 800 if (!ids) { 801 if (!ids && n < IONIC_NB_HW_STATS) 802 return IONIC_NB_HW_STATS; 803 804 ionic_lif_get_hw_stats(lif, &hw_stats); 805 806 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 807 values[i] = *(uint64_t *)(((char *)&hw_stats) + 808 rte_ionic_xstats_strings[i].offset); 809 } 810 811 return IONIC_NB_HW_STATS; 812 } 813 814 ionic_dev_xstats_get_by_id(eth_dev, NULL, values_copy, 815 IONIC_NB_HW_STATS); 816 817 for (i = 0; i < n; i++) { 818 if (ids[i] >= IONIC_NB_HW_STATS) { 819 IONIC_PRINT(ERR, "id value isn't valid"); 820 return -1; 821 } 822 823 values[i] = values_copy[ids[i]]; 824 } 825 826 return n; 827 } 828 829 static int 830 ionic_dev_xstats_reset(struct rte_eth_dev *eth_dev) 831 { 832 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 833 834 ionic_lif_reset_hw_stats(lif); 835 836 return 0; 837 } 838 839 static int 840 ionic_dev_configure(struct rte_eth_dev *eth_dev) 841 { 842 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 843 844 IONIC_PRINT_CALL(); 845 846 ionic_lif_configure(lif); 847 848 ionic_lif_set_features(lif); 849 850 return 0; 851 } 852 853 static inline uint32_t 854 ionic_parse_link_speeds(uint16_t link_speeds) 855 { 856 if (link_speeds & ETH_LINK_SPEED_100G) 857 return 100000; 858 else if (link_speeds & ETH_LINK_SPEED_50G) 859 return 50000; 860 else if (link_speeds & ETH_LINK_SPEED_40G) 861 return 40000; 862 else if (link_speeds & ETH_LINK_SPEED_25G) 863 return 25000; 864 else if (link_speeds & ETH_LINK_SPEED_10G) 865 return 10000; 866 else 867 return 0; 868 } 869 870 /* 871 * Configure device link speed and setup link. 872 * It returns 0 on success. 873 */ 874 static int 875 ionic_dev_start(struct rte_eth_dev *eth_dev) 876 { 877 struct rte_eth_conf *dev_conf = ð_dev->data->dev_conf; 878 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 879 struct ionic_adapter *adapter = lif->adapter; 880 struct ionic_dev *idev = &adapter->idev; 881 uint32_t speed = 0, allowed_speeds; 882 uint8_t an_enable; 883 int err; 884 885 IONIC_PRINT_CALL(); 886 887 allowed_speeds = 888 ETH_LINK_SPEED_FIXED | 889 ETH_LINK_SPEED_10G | 890 ETH_LINK_SPEED_25G | 891 ETH_LINK_SPEED_40G | 892 ETH_LINK_SPEED_50G | 893 ETH_LINK_SPEED_100G; 894 895 if (dev_conf->link_speeds & ~allowed_speeds) { 896 IONIC_PRINT(ERR, "Invalid link setting"); 897 return -EINVAL; 898 } 899 900 if (dev_conf->lpbk_mode) 901 IONIC_PRINT(WARNING, "Loopback mode not supported"); 902 903 err = ionic_lif_start(lif); 904 if (err) { 905 IONIC_PRINT(ERR, "Cannot start LIF: %d", err); 906 return err; 907 } 908 909 /* Configure link */ 910 an_enable = (dev_conf->link_speeds & ETH_LINK_SPEED_FIXED) == 0; 911 912 ionic_dev_cmd_port_autoneg(idev, an_enable); 913 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 914 if (err) 915 IONIC_PRINT(WARNING, "Failed to %s autonegotiation", 916 an_enable ? "enable" : "disable"); 917 918 if (!an_enable) 919 speed = ionic_parse_link_speeds(dev_conf->link_speeds); 920 if (speed) { 921 ionic_dev_cmd_port_speed(idev, speed); 922 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 923 if (err) 924 IONIC_PRINT(WARNING, "Failed to set link speed %u", 925 speed); 926 } 927 928 ionic_dev_link_update(eth_dev, 0); 929 930 return 0; 931 } 932 933 /* 934 * Stop device: disable rx and tx functions to allow for reconfiguring. 935 */ 936 static int 937 ionic_dev_stop(struct rte_eth_dev *eth_dev) 938 { 939 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 940 941 IONIC_PRINT_CALL(); 942 943 ionic_lif_stop(lif); 944 945 return 0; 946 } 947 948 static void ionic_unconfigure_intr(struct ionic_adapter *adapter); 949 950 /* 951 * Reset and stop device. 952 */ 953 static int 954 ionic_dev_close(struct rte_eth_dev *eth_dev) 955 { 956 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 957 struct ionic_adapter *adapter = lif->adapter; 958 959 IONIC_PRINT_CALL(); 960 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 961 return 0; 962 963 ionic_lif_stop(lif); 964 965 ionic_lif_free_queues(lif); 966 967 IONIC_PRINT(NOTICE, "Removing device %s", eth_dev->device->name); 968 ionic_unconfigure_intr(adapter); 969 970 rte_eth_dev_destroy(eth_dev, eth_ionic_dev_uninit); 971 972 ionic_port_reset(adapter); 973 ionic_reset(adapter); 974 975 rte_free(adapter); 976 977 return 0; 978 } 979 980 static int 981 eth_ionic_dev_init(struct rte_eth_dev *eth_dev, void *init_params) 982 { 983 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 984 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 985 struct ionic_adapter *adapter = (struct ionic_adapter *)init_params; 986 int err; 987 988 IONIC_PRINT_CALL(); 989 990 eth_dev->dev_ops = &ionic_eth_dev_ops; 991 eth_dev->rx_pkt_burst = &ionic_recv_pkts; 992 eth_dev->tx_pkt_burst = &ionic_xmit_pkts; 993 eth_dev->tx_pkt_prepare = &ionic_prep_pkts; 994 995 /* Multi-process not supported, primary does initialization anyway */ 996 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 997 return 0; 998 999 rte_eth_copy_pci_info(eth_dev, pci_dev); 1000 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 1001 1002 lif->eth_dev = eth_dev; 1003 lif->adapter = adapter; 1004 adapter->lif = lif; 1005 1006 IONIC_PRINT(DEBUG, "Up to %u MAC addresses supported", 1007 adapter->max_mac_addrs); 1008 1009 /* Allocate memory for storing MAC addresses */ 1010 eth_dev->data->mac_addrs = rte_zmalloc("ionic", 1011 RTE_ETHER_ADDR_LEN * adapter->max_mac_addrs, 0); 1012 1013 if (eth_dev->data->mac_addrs == NULL) { 1014 IONIC_PRINT(ERR, "Failed to allocate %u bytes needed to " 1015 "store MAC addresses", 1016 RTE_ETHER_ADDR_LEN * adapter->max_mac_addrs); 1017 err = -ENOMEM; 1018 goto err; 1019 } 1020 1021 err = ionic_lif_alloc(lif); 1022 if (err) { 1023 IONIC_PRINT(ERR, "Cannot allocate LIFs: %d, aborting", 1024 err); 1025 goto err; 1026 } 1027 1028 err = ionic_lif_init(lif); 1029 if (err) { 1030 IONIC_PRINT(ERR, "Cannot init LIFs: %d, aborting", err); 1031 goto err_free_lif; 1032 } 1033 1034 /* Copy the MAC address */ 1035 rte_ether_addr_copy((struct rte_ether_addr *)lif->mac_addr, 1036 ð_dev->data->mac_addrs[0]); 1037 1038 IONIC_PRINT(DEBUG, "Port %u initialized", eth_dev->data->port_id); 1039 1040 return 0; 1041 1042 err_free_lif: 1043 ionic_lif_free(lif); 1044 err: 1045 return err; 1046 } 1047 1048 static int 1049 eth_ionic_dev_uninit(struct rte_eth_dev *eth_dev) 1050 { 1051 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 1052 struct ionic_adapter *adapter = lif->adapter; 1053 1054 IONIC_PRINT_CALL(); 1055 1056 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1057 return 0; 1058 1059 adapter->lif = NULL; 1060 1061 ionic_lif_deinit(lif); 1062 ionic_lif_free(lif); 1063 1064 if (!(lif->state & IONIC_LIF_F_FW_RESET)) 1065 ionic_lif_reset(lif); 1066 1067 return 0; 1068 } 1069 1070 static int 1071 ionic_configure_intr(struct ionic_adapter *adapter) 1072 { 1073 struct rte_pci_device *pci_dev = adapter->pci_dev; 1074 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1075 int err; 1076 1077 IONIC_PRINT(DEBUG, "Configuring %u intrs", adapter->nintrs); 1078 1079 if (rte_intr_efd_enable(intr_handle, adapter->nintrs)) { 1080 IONIC_PRINT(ERR, "Fail to create eventfd"); 1081 return -1; 1082 } 1083 1084 if (rte_intr_dp_is_en(intr_handle)) 1085 IONIC_PRINT(DEBUG, 1086 "Packet I/O interrupt on datapath is enabled"); 1087 1088 if (!intr_handle->intr_vec) { 1089 intr_handle->intr_vec = rte_zmalloc("intr_vec", 1090 adapter->nintrs * sizeof(int), 0); 1091 1092 if (!intr_handle->intr_vec) { 1093 IONIC_PRINT(ERR, "Failed to allocate %u vectors", 1094 adapter->nintrs); 1095 return -ENOMEM; 1096 } 1097 } 1098 1099 err = rte_intr_callback_register(intr_handle, 1100 ionic_dev_interrupt_handler, 1101 adapter); 1102 1103 if (err) { 1104 IONIC_PRINT(ERR, 1105 "Failure registering interrupts handler (%d)", 1106 err); 1107 return err; 1108 } 1109 1110 /* enable intr mapping */ 1111 err = rte_intr_enable(intr_handle); 1112 1113 if (err) { 1114 IONIC_PRINT(ERR, "Failure enabling interrupts (%d)", err); 1115 return err; 1116 } 1117 1118 return 0; 1119 } 1120 1121 static void 1122 ionic_unconfigure_intr(struct ionic_adapter *adapter) 1123 { 1124 struct rte_pci_device *pci_dev = adapter->pci_dev; 1125 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1126 1127 rte_intr_disable(intr_handle); 1128 1129 rte_intr_callback_unregister(intr_handle, 1130 ionic_dev_interrupt_handler, 1131 adapter); 1132 } 1133 1134 static int 1135 eth_ionic_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1136 struct rte_pci_device *pci_dev) 1137 { 1138 char name[RTE_ETH_NAME_MAX_LEN]; 1139 struct rte_mem_resource *resource; 1140 struct ionic_adapter *adapter; 1141 struct ionic_hw *hw; 1142 unsigned long i; 1143 int err; 1144 1145 /* Check structs (trigger error at compilation time) */ 1146 ionic_struct_size_checks(); 1147 1148 /* Multi-process not supported */ 1149 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1150 err = -EPERM; 1151 goto err; 1152 } 1153 1154 IONIC_PRINT(DEBUG, "Initializing device %s", 1155 pci_dev->device.name); 1156 1157 adapter = rte_zmalloc("ionic", sizeof(*adapter), 0); 1158 if (!adapter) { 1159 IONIC_PRINT(ERR, "OOM"); 1160 err = -ENOMEM; 1161 goto err; 1162 } 1163 1164 adapter->pci_dev = pci_dev; 1165 hw = &adapter->hw; 1166 1167 hw->device_id = pci_dev->id.device_id; 1168 hw->vendor_id = pci_dev->id.vendor_id; 1169 1170 err = ionic_init_mac(hw); 1171 if (err != 0) { 1172 IONIC_PRINT(ERR, "Mac init failed: %d", err); 1173 err = -EIO; 1174 goto err_free_adapter; 1175 } 1176 1177 adapter->num_bars = 0; 1178 for (i = 0; i < PCI_MAX_RESOURCE && i < IONIC_BARS_MAX; i++) { 1179 resource = &pci_dev->mem_resource[i]; 1180 if (resource->phys_addr == 0 || resource->len == 0) 1181 continue; 1182 adapter->bars[adapter->num_bars].vaddr = resource->addr; 1183 adapter->bars[adapter->num_bars].bus_addr = resource->phys_addr; 1184 adapter->bars[adapter->num_bars].len = resource->len; 1185 adapter->num_bars++; 1186 } 1187 1188 /* Discover ionic dev resources */ 1189 1190 err = ionic_setup(adapter); 1191 if (err) { 1192 IONIC_PRINT(ERR, "Cannot setup device: %d, aborting", err); 1193 goto err_free_adapter; 1194 } 1195 1196 err = ionic_identify(adapter); 1197 if (err) { 1198 IONIC_PRINT(ERR, "Cannot identify device: %d, aborting", 1199 err); 1200 goto err_free_adapter; 1201 } 1202 1203 err = ionic_init(adapter); 1204 if (err) { 1205 IONIC_PRINT(ERR, "Cannot init device: %d, aborting", err); 1206 goto err_free_adapter; 1207 } 1208 1209 /* Configure the ports */ 1210 err = ionic_port_identify(adapter); 1211 if (err) { 1212 IONIC_PRINT(ERR, "Cannot identify port: %d, aborting", 1213 err); 1214 goto err_free_adapter; 1215 } 1216 1217 err = ionic_port_init(adapter); 1218 if (err) { 1219 IONIC_PRINT(ERR, "Cannot init port: %d, aborting", err); 1220 goto err_free_adapter; 1221 } 1222 1223 /* Configure LIFs */ 1224 err = ionic_lif_identify(adapter); 1225 if (err) { 1226 IONIC_PRINT(ERR, "Cannot identify lif: %d, aborting", err); 1227 goto err_free_adapter; 1228 } 1229 1230 /* Allocate and init LIFs */ 1231 err = ionic_lifs_size(adapter); 1232 if (err) { 1233 IONIC_PRINT(ERR, "Cannot size LIFs: %d, aborting", err); 1234 goto err_free_adapter; 1235 } 1236 1237 adapter->max_mac_addrs = 1238 rte_le_to_cpu_32(adapter->ident.lif.eth.max_ucast_filters); 1239 1240 if (rte_le_to_cpu_32(adapter->ident.dev.nlifs) != 1) { 1241 IONIC_PRINT(ERR, "Unexpected request for %d LIFs", 1242 rte_le_to_cpu_32(adapter->ident.dev.nlifs)); 1243 goto err_free_adapter; 1244 } 1245 1246 snprintf(name, sizeof(name), "%s_lif", pci_dev->device.name); 1247 err = rte_eth_dev_create(&pci_dev->device, 1248 name, sizeof(struct ionic_lif), 1249 NULL, NULL, eth_ionic_dev_init, adapter); 1250 if (err) { 1251 IONIC_PRINT(ERR, "Cannot create eth device for %s", name); 1252 goto err_free_adapter; 1253 } 1254 1255 err = ionic_configure_intr(adapter); 1256 1257 if (err) { 1258 IONIC_PRINT(ERR, "Failed to configure interrupts"); 1259 goto err_free_adapter; 1260 } 1261 1262 return 0; 1263 1264 err_free_adapter: 1265 rte_free(adapter); 1266 err: 1267 return err; 1268 } 1269 1270 static int 1271 eth_ionic_pci_remove(struct rte_pci_device *pci_dev) 1272 { 1273 char name[RTE_ETH_NAME_MAX_LEN]; 1274 struct rte_eth_dev *eth_dev; 1275 1276 /* Adapter lookup is using the eth_dev name */ 1277 snprintf(name, sizeof(name), "%s_lif", pci_dev->device.name); 1278 1279 eth_dev = rte_eth_dev_allocated(name); 1280 if (eth_dev) 1281 ionic_dev_close(eth_dev); 1282 else 1283 IONIC_PRINT(DEBUG, "Cannot find device %s", 1284 pci_dev->device.name); 1285 1286 return 0; 1287 } 1288 1289 static struct rte_pci_driver rte_ionic_pmd = { 1290 .id_table = pci_id_ionic_map, 1291 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 1292 .probe = eth_ionic_pci_probe, 1293 .remove = eth_ionic_pci_remove, 1294 }; 1295 1296 RTE_PMD_REGISTER_PCI(net_ionic, rte_ionic_pmd); 1297 RTE_PMD_REGISTER_PCI_TABLE(net_ionic, pci_id_ionic_map); 1298 RTE_PMD_REGISTER_KMOD_DEP(net_ionic, "* igb_uio | uio_pci_generic | vfio-pci"); 1299 RTE_LOG_REGISTER_DEFAULT(ionic_logtype, NOTICE); 1300