1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018-2022 Advanced Micro Devices, Inc. 3 */ 4 5 #include <rte_ethdev.h> 6 #include <ethdev_driver.h> 7 #include <rte_malloc.h> 8 9 #include "ionic_logs.h" 10 #include "ionic.h" 11 #include "ionic_dev.h" 12 #include "ionic_mac_api.h" 13 #include "ionic_lif.h" 14 #include "ionic_ethdev.h" 15 #include "ionic_rxtx.h" 16 17 static int eth_ionic_dev_init(struct rte_eth_dev *eth_dev, void *init_params); 18 static int eth_ionic_dev_uninit(struct rte_eth_dev *eth_dev); 19 static int ionic_dev_info_get(struct rte_eth_dev *eth_dev, 20 struct rte_eth_dev_info *dev_info); 21 static int ionic_dev_configure(struct rte_eth_dev *dev); 22 static int ionic_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 23 static int ionic_dev_start(struct rte_eth_dev *dev); 24 static int ionic_dev_stop(struct rte_eth_dev *dev); 25 static int ionic_dev_close(struct rte_eth_dev *dev); 26 static int ionic_dev_set_link_up(struct rte_eth_dev *dev); 27 static int ionic_dev_set_link_down(struct rte_eth_dev *dev); 28 static int ionic_flow_ctrl_get(struct rte_eth_dev *eth_dev, 29 struct rte_eth_fc_conf *fc_conf); 30 static int ionic_flow_ctrl_set(struct rte_eth_dev *eth_dev, 31 struct rte_eth_fc_conf *fc_conf); 32 static int ionic_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask); 33 static int ionic_dev_rss_reta_update(struct rte_eth_dev *eth_dev, 34 struct rte_eth_rss_reta_entry64 *reta_conf, uint16_t reta_size); 35 static int ionic_dev_rss_reta_query(struct rte_eth_dev *eth_dev, 36 struct rte_eth_rss_reta_entry64 *reta_conf, uint16_t reta_size); 37 static int ionic_dev_rss_hash_conf_get(struct rte_eth_dev *eth_dev, 38 struct rte_eth_rss_conf *rss_conf); 39 static int ionic_dev_rss_hash_update(struct rte_eth_dev *eth_dev, 40 struct rte_eth_rss_conf *rss_conf); 41 static int ionic_dev_stats_get(struct rte_eth_dev *eth_dev, 42 struct rte_eth_stats *stats); 43 static int ionic_dev_stats_reset(struct rte_eth_dev *eth_dev); 44 static int ionic_dev_xstats_get(struct rte_eth_dev *dev, 45 struct rte_eth_xstat *xstats, unsigned int n); 46 static int ionic_dev_xstats_get_by_id(struct rte_eth_dev *dev, 47 const uint64_t *ids, uint64_t *values, unsigned int n); 48 static int ionic_dev_xstats_reset(struct rte_eth_dev *dev); 49 static int ionic_dev_xstats_get_names(struct rte_eth_dev *dev, 50 struct rte_eth_xstat_name *xstats_names, unsigned int size); 51 static int ionic_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, 52 const uint64_t *ids, struct rte_eth_xstat_name *xstats_names, 53 unsigned int limit); 54 static int ionic_dev_fw_version_get(struct rte_eth_dev *eth_dev, 55 char *fw_version, size_t fw_size); 56 57 static const struct rte_eth_desc_lim rx_desc_lim = { 58 .nb_max = IONIC_MAX_RING_DESC, 59 .nb_min = IONIC_MIN_RING_DESC, 60 .nb_align = 1, 61 }; 62 63 static const struct rte_eth_desc_lim tx_desc_lim_v1 = { 64 .nb_max = IONIC_MAX_RING_DESC, 65 .nb_min = IONIC_MIN_RING_DESC, 66 .nb_align = 1, 67 .nb_seg_max = IONIC_TX_MAX_SG_ELEMS_V1 + 1, 68 .nb_mtu_seg_max = IONIC_TX_MAX_SG_ELEMS_V1 + 1, 69 }; 70 71 static const struct eth_dev_ops ionic_eth_dev_ops = { 72 .dev_infos_get = ionic_dev_info_get, 73 .dev_supported_ptypes_get = ionic_dev_supported_ptypes_get, 74 .dev_configure = ionic_dev_configure, 75 .mtu_set = ionic_dev_mtu_set, 76 .dev_start = ionic_dev_start, 77 .dev_stop = ionic_dev_stop, 78 .dev_close = ionic_dev_close, 79 .link_update = ionic_dev_link_update, 80 .dev_set_link_up = ionic_dev_set_link_up, 81 .dev_set_link_down = ionic_dev_set_link_down, 82 .mac_addr_add = ionic_dev_add_mac, 83 .mac_addr_remove = ionic_dev_remove_mac, 84 .mac_addr_set = ionic_dev_set_mac, 85 .vlan_filter_set = ionic_dev_vlan_filter_set, 86 .promiscuous_enable = ionic_dev_promiscuous_enable, 87 .promiscuous_disable = ionic_dev_promiscuous_disable, 88 .allmulticast_enable = ionic_dev_allmulticast_enable, 89 .allmulticast_disable = ionic_dev_allmulticast_disable, 90 .flow_ctrl_get = ionic_flow_ctrl_get, 91 .flow_ctrl_set = ionic_flow_ctrl_set, 92 .rxq_info_get = ionic_rxq_info_get, 93 .txq_info_get = ionic_txq_info_get, 94 .rx_queue_setup = ionic_dev_rx_queue_setup, 95 .rx_queue_release = ionic_dev_rx_queue_release, 96 .rx_queue_start = ionic_dev_rx_queue_start, 97 .rx_queue_stop = ionic_dev_rx_queue_stop, 98 .tx_queue_setup = ionic_dev_tx_queue_setup, 99 .tx_queue_release = ionic_dev_tx_queue_release, 100 .tx_queue_start = ionic_dev_tx_queue_start, 101 .tx_queue_stop = ionic_dev_tx_queue_stop, 102 .vlan_offload_set = ionic_vlan_offload_set, 103 .reta_update = ionic_dev_rss_reta_update, 104 .reta_query = ionic_dev_rss_reta_query, 105 .rss_hash_conf_get = ionic_dev_rss_hash_conf_get, 106 .rss_hash_update = ionic_dev_rss_hash_update, 107 .stats_get = ionic_dev_stats_get, 108 .stats_reset = ionic_dev_stats_reset, 109 .xstats_get = ionic_dev_xstats_get, 110 .xstats_get_by_id = ionic_dev_xstats_get_by_id, 111 .xstats_reset = ionic_dev_xstats_reset, 112 .xstats_get_names = ionic_dev_xstats_get_names, 113 .xstats_get_names_by_id = ionic_dev_xstats_get_names_by_id, 114 .fw_version_get = ionic_dev_fw_version_get, 115 }; 116 117 struct rte_ionic_xstats_name_off { 118 char name[RTE_ETH_XSTATS_NAME_SIZE]; 119 unsigned int offset; 120 }; 121 122 static const struct rte_ionic_xstats_name_off rte_ionic_xstats_strings[] = { 123 /* RX */ 124 {"rx_ucast_bytes", offsetof(struct ionic_lif_stats, 125 rx_ucast_bytes)}, 126 {"rx_ucast_packets", offsetof(struct ionic_lif_stats, 127 rx_ucast_packets)}, 128 {"rx_mcast_bytes", offsetof(struct ionic_lif_stats, 129 rx_mcast_bytes)}, 130 {"rx_mcast_packets", offsetof(struct ionic_lif_stats, 131 rx_mcast_packets)}, 132 {"rx_bcast_bytes", offsetof(struct ionic_lif_stats, 133 rx_bcast_bytes)}, 134 {"rx_bcast_packets", offsetof(struct ionic_lif_stats, 135 rx_bcast_packets)}, 136 /* RX drops */ 137 {"rx_ucast_drop_bytes", offsetof(struct ionic_lif_stats, 138 rx_ucast_drop_bytes)}, 139 {"rx_ucast_drop_packets", offsetof(struct ionic_lif_stats, 140 rx_ucast_drop_packets)}, 141 {"rx_mcast_drop_bytes", offsetof(struct ionic_lif_stats, 142 rx_mcast_drop_bytes)}, 143 {"rx_mcast_drop_packets", offsetof(struct ionic_lif_stats, 144 rx_mcast_drop_packets)}, 145 {"rx_bcast_drop_bytes", offsetof(struct ionic_lif_stats, 146 rx_bcast_drop_bytes)}, 147 {"rx_bcast_drop_packets", offsetof(struct ionic_lif_stats, 148 rx_bcast_drop_packets)}, 149 {"rx_dma_error", offsetof(struct ionic_lif_stats, 150 rx_dma_error)}, 151 /* TX */ 152 {"tx_ucast_bytes", offsetof(struct ionic_lif_stats, 153 tx_ucast_bytes)}, 154 {"tx_ucast_packets", offsetof(struct ionic_lif_stats, 155 tx_ucast_packets)}, 156 {"tx_mcast_bytes", offsetof(struct ionic_lif_stats, 157 tx_mcast_bytes)}, 158 {"tx_mcast_packets", offsetof(struct ionic_lif_stats, 159 tx_mcast_packets)}, 160 {"tx_bcast_bytes", offsetof(struct ionic_lif_stats, 161 tx_bcast_bytes)}, 162 {"tx_bcast_packets", offsetof(struct ionic_lif_stats, 163 tx_bcast_packets)}, 164 /* TX drops */ 165 {"tx_ucast_drop_bytes", offsetof(struct ionic_lif_stats, 166 tx_ucast_drop_bytes)}, 167 {"tx_ucast_drop_packets", offsetof(struct ionic_lif_stats, 168 tx_ucast_drop_packets)}, 169 {"tx_mcast_drop_bytes", offsetof(struct ionic_lif_stats, 170 tx_mcast_drop_bytes)}, 171 {"tx_mcast_drop_packets", offsetof(struct ionic_lif_stats, 172 tx_mcast_drop_packets)}, 173 {"tx_bcast_drop_bytes", offsetof(struct ionic_lif_stats, 174 tx_bcast_drop_bytes)}, 175 {"tx_bcast_drop_packets", offsetof(struct ionic_lif_stats, 176 tx_bcast_drop_packets)}, 177 {"tx_dma_error", offsetof(struct ionic_lif_stats, 178 tx_dma_error)}, 179 /* Rx Queue/Ring drops */ 180 {"rx_queue_disabled", offsetof(struct ionic_lif_stats, 181 rx_queue_disabled)}, 182 {"rx_queue_empty", offsetof(struct ionic_lif_stats, 183 rx_queue_empty)}, 184 {"rx_queue_error", offsetof(struct ionic_lif_stats, 185 rx_queue_error)}, 186 {"rx_desc_fetch_error", offsetof(struct ionic_lif_stats, 187 rx_desc_fetch_error)}, 188 {"rx_desc_data_error", offsetof(struct ionic_lif_stats, 189 rx_desc_data_error)}, 190 /* Tx Queue/Ring drops */ 191 {"tx_queue_disabled", offsetof(struct ionic_lif_stats, 192 tx_queue_disabled)}, 193 {"tx_queue_error", offsetof(struct ionic_lif_stats, 194 tx_queue_error)}, 195 {"tx_desc_fetch_error", offsetof(struct ionic_lif_stats, 196 tx_desc_fetch_error)}, 197 {"tx_desc_data_error", offsetof(struct ionic_lif_stats, 198 tx_desc_data_error)}, 199 }; 200 201 #define IONIC_NB_HW_STATS RTE_DIM(rte_ionic_xstats_strings) 202 203 static int 204 ionic_dev_fw_version_get(struct rte_eth_dev *eth_dev, 205 char *fw_version, size_t fw_size) 206 { 207 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 208 struct ionic_adapter *adapter = lif->adapter; 209 int ret; 210 211 ret = snprintf(fw_version, fw_size, "%s", 212 adapter->fw_version); 213 if (ret < 0) 214 return -EINVAL; 215 216 ret += 1; /* add the size of '\0' */ 217 if (fw_size < (size_t)ret) 218 return ret; 219 else 220 return 0; 221 } 222 223 /* 224 * Set device link up, enable tx. 225 */ 226 static int 227 ionic_dev_set_link_up(struct rte_eth_dev *eth_dev) 228 { 229 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 230 int err; 231 232 IONIC_PRINT_CALL(); 233 234 err = ionic_lif_start(lif); 235 if (err) 236 IONIC_PRINT(ERR, "Could not start lif to set link up"); 237 238 ionic_dev_link_update(lif->eth_dev, 0); 239 240 return err; 241 } 242 243 /* 244 * Set device link down, disable tx. 245 */ 246 static int 247 ionic_dev_set_link_down(struct rte_eth_dev *eth_dev) 248 { 249 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 250 251 IONIC_PRINT_CALL(); 252 253 ionic_lif_stop(lif); 254 255 ionic_dev_link_update(lif->eth_dev, 0); 256 257 return 0; 258 } 259 260 int 261 ionic_dev_link_update(struct rte_eth_dev *eth_dev, 262 int wait_to_complete __rte_unused) 263 { 264 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 265 struct ionic_adapter *adapter = lif->adapter; 266 struct rte_eth_link link; 267 268 IONIC_PRINT_CALL(); 269 270 /* Initialize */ 271 memset(&link, 0, sizeof(link)); 272 273 if (adapter->idev.port_info->config.an_enable) { 274 link.link_autoneg = RTE_ETH_LINK_AUTONEG; 275 } 276 277 if (!adapter->link_up || 278 !(lif->state & IONIC_LIF_F_UP)) { 279 /* Interface is down */ 280 link.link_status = RTE_ETH_LINK_DOWN; 281 link.link_duplex = RTE_ETH_LINK_HALF_DUPLEX; 282 link.link_speed = RTE_ETH_SPEED_NUM_NONE; 283 } else { 284 /* Interface is up */ 285 link.link_status = RTE_ETH_LINK_UP; 286 link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX; 287 switch (adapter->link_speed) { 288 case 10000: 289 link.link_speed = RTE_ETH_SPEED_NUM_10G; 290 break; 291 case 25000: 292 link.link_speed = RTE_ETH_SPEED_NUM_25G; 293 break; 294 case 40000: 295 link.link_speed = RTE_ETH_SPEED_NUM_40G; 296 break; 297 case 50000: 298 link.link_speed = RTE_ETH_SPEED_NUM_50G; 299 break; 300 case 100000: 301 link.link_speed = RTE_ETH_SPEED_NUM_100G; 302 break; 303 default: 304 link.link_speed = RTE_ETH_SPEED_NUM_NONE; 305 break; 306 } 307 } 308 309 return rte_eth_linkstatus_set(eth_dev, &link); 310 } 311 312 /** 313 * Interrupt handler triggered by NIC for handling 314 * specific interrupt. 315 * 316 * @param param 317 * The address of parameter registered before. 318 * 319 * @return 320 * void 321 */ 322 void 323 ionic_dev_interrupt_handler(void *param) 324 { 325 struct ionic_adapter *adapter = (struct ionic_adapter *)param; 326 327 IONIC_PRINT(DEBUG, "->"); 328 329 if (adapter->lif) 330 ionic_notifyq_handler(adapter->lif, -1); 331 } 332 333 static int 334 ionic_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) 335 { 336 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 337 338 if (lif->state & IONIC_LIF_F_UP) { 339 IONIC_PRINT(ERR, "Stop %s before setting mtu", lif->name); 340 return -EBUSY; 341 } 342 343 /* Note: mtu check against min/max is done by the API */ 344 IONIC_PRINT(INFO, "Setting mtu %u", mtu); 345 346 /* Update the frame size used by the Rx path */ 347 lif->frame_size = mtu + IONIC_ETH_OVERHEAD; 348 349 return 0; 350 } 351 352 static int 353 ionic_dev_info_get(struct rte_eth_dev *eth_dev, 354 struct rte_eth_dev_info *dev_info) 355 { 356 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 357 struct ionic_adapter *adapter = lif->adapter; 358 struct ionic_identity *ident = &adapter->ident; 359 union ionic_lif_config *cfg = &ident->lif.eth.config; 360 361 IONIC_PRINT_CALL(); 362 363 dev_info->max_rx_queues = (uint16_t) 364 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_RXQ]); 365 dev_info->max_tx_queues = (uint16_t) 366 rte_le_to_cpu_32(cfg->queue_count[IONIC_QTYPE_TXQ]); 367 368 /* Also add ETHER_CRC_LEN if the adapter is able to keep CRC */ 369 dev_info->min_mtu = RTE_MAX((uint32_t)IONIC_MIN_MTU, 370 rte_le_to_cpu_32(ident->lif.eth.min_mtu)); 371 dev_info->max_mtu = RTE_MIN((uint32_t)IONIC_MAX_MTU, 372 rte_le_to_cpu_32(ident->lif.eth.max_mtu)); 373 dev_info->min_rx_bufsize = dev_info->min_mtu + IONIC_ETH_OVERHEAD; 374 dev_info->max_rx_pktlen = dev_info->max_mtu + IONIC_ETH_OVERHEAD; 375 dev_info->max_lro_pkt_size = 376 eth_dev->data->dev_conf.rxmode.max_lro_pkt_size; 377 378 dev_info->max_mac_addrs = adapter->max_mac_addrs; 379 dev_info->hash_key_size = IONIC_RSS_HASH_KEY_SIZE; 380 dev_info->reta_size = rte_le_to_cpu_16(ident->lif.eth.rss_ind_tbl_sz); 381 dev_info->flow_type_rss_offloads = IONIC_ETH_RSS_OFFLOAD_ALL; 382 383 dev_info->speed_capa = 384 RTE_ETH_LINK_SPEED_10G | 385 RTE_ETH_LINK_SPEED_25G | 386 RTE_ETH_LINK_SPEED_40G | 387 RTE_ETH_LINK_SPEED_50G | 388 RTE_ETH_LINK_SPEED_100G; 389 390 /* 391 * Per-queue capabilities 392 * RTE does not support disabling a feature on a queue if it is 393 * enabled globally on the device. Thus the driver does not advertise 394 * capabilities like RTE_ETH_TX_OFFLOAD_IPV4_CKSUM as per-queue even 395 * though the driver would be otherwise capable of disabling it on 396 * a per-queue basis. 397 */ 398 399 dev_info->rx_queue_offload_capa = 0; 400 dev_info->tx_queue_offload_capa = RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE; 401 402 /* 403 * Per-port capabilities 404 * See ionic_set_features to request and check supported features 405 */ 406 407 dev_info->rx_offload_capa = dev_info->rx_queue_offload_capa | 408 RTE_ETH_RX_OFFLOAD_IPV4_CKSUM | 409 RTE_ETH_RX_OFFLOAD_UDP_CKSUM | 410 RTE_ETH_RX_OFFLOAD_TCP_CKSUM | 411 RTE_ETH_RX_OFFLOAD_VLAN_FILTER | 412 RTE_ETH_RX_OFFLOAD_VLAN_STRIP | 413 RTE_ETH_RX_OFFLOAD_SCATTER | 414 RTE_ETH_RX_OFFLOAD_RSS_HASH | 415 0; 416 417 dev_info->tx_offload_capa = dev_info->tx_queue_offload_capa | 418 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | 419 RTE_ETH_TX_OFFLOAD_UDP_CKSUM | 420 RTE_ETH_TX_OFFLOAD_TCP_CKSUM | 421 RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM | 422 RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM | 423 RTE_ETH_TX_OFFLOAD_MULTI_SEGS | 424 RTE_ETH_TX_OFFLOAD_TCP_TSO | 425 RTE_ETH_TX_OFFLOAD_VLAN_INSERT | 426 0; 427 428 dev_info->rx_desc_lim = rx_desc_lim; 429 dev_info->tx_desc_lim = tx_desc_lim_v1; 430 431 /* Driver-preferred Rx/Tx parameters */ 432 dev_info->default_rxportconf.burst_size = 32; 433 dev_info->default_txportconf.burst_size = 32; 434 dev_info->default_rxportconf.nb_queues = 1; 435 dev_info->default_txportconf.nb_queues = 1; 436 dev_info->default_rxportconf.ring_size = IONIC_DEF_TXRX_DESC; 437 dev_info->default_txportconf.ring_size = IONIC_DEF_TXRX_DESC; 438 439 dev_info->default_rxconf = (struct rte_eth_rxconf) { 440 /* Packets are always dropped if no desc are available */ 441 .rx_drop_en = 1, 442 }; 443 444 return 0; 445 } 446 447 static int 448 ionic_flow_ctrl_get(struct rte_eth_dev *eth_dev, 449 struct rte_eth_fc_conf *fc_conf) 450 { 451 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 452 struct ionic_adapter *adapter = lif->adapter; 453 struct ionic_dev *idev = &adapter->idev; 454 455 if (idev->port_info) { 456 /* Flow control autoneg not supported */ 457 fc_conf->autoneg = 0; 458 459 if (idev->port_info->config.pause_type) 460 fc_conf->mode = RTE_ETH_FC_FULL; 461 else 462 fc_conf->mode = RTE_ETH_FC_NONE; 463 } 464 465 return 0; 466 } 467 468 static int 469 ionic_flow_ctrl_set(struct rte_eth_dev *eth_dev, 470 struct rte_eth_fc_conf *fc_conf) 471 { 472 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 473 struct ionic_adapter *adapter = lif->adapter; 474 struct ionic_dev *idev = &adapter->idev; 475 uint8_t pause_type = IONIC_PORT_PAUSE_TYPE_NONE; 476 int err; 477 478 if (fc_conf->autoneg) { 479 IONIC_PRINT(WARNING, "Flow control autoneg not supported"); 480 return -ENOTSUP; 481 } 482 483 switch (fc_conf->mode) { 484 case RTE_ETH_FC_NONE: 485 pause_type = IONIC_PORT_PAUSE_TYPE_NONE; 486 break; 487 case RTE_ETH_FC_FULL: 488 pause_type = IONIC_PORT_PAUSE_TYPE_LINK; 489 break; 490 case RTE_ETH_FC_RX_PAUSE: 491 case RTE_ETH_FC_TX_PAUSE: 492 return -ENOTSUP; 493 } 494 495 ionic_dev_cmd_port_pause(idev, pause_type); 496 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 497 if (err) 498 IONIC_PRINT(WARNING, "Failed to configure flow control"); 499 500 return err; 501 } 502 503 static int 504 ionic_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask) 505 { 506 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 507 508 ionic_lif_configure_vlan_offload(lif, mask); 509 510 ionic_lif_set_features(lif); 511 512 return 0; 513 } 514 515 static int 516 ionic_dev_rss_reta_update(struct rte_eth_dev *eth_dev, 517 struct rte_eth_rss_reta_entry64 *reta_conf, 518 uint16_t reta_size) 519 { 520 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 521 struct ionic_adapter *adapter = lif->adapter; 522 struct ionic_identity *ident = &adapter->ident; 523 uint32_t i, j, index, num; 524 uint16_t tbl_sz = rte_le_to_cpu_16(ident->lif.eth.rss_ind_tbl_sz); 525 526 IONIC_PRINT_CALL(); 527 528 if (!lif->rss_ind_tbl) { 529 IONIC_PRINT(ERR, "RSS RETA not initialized, " 530 "can't update the table"); 531 return -EINVAL; 532 } 533 534 if (reta_size != tbl_sz) { 535 IONIC_PRINT(ERR, "The size of hash lookup table configured " 536 "(%d) does not match the number hardware can support " 537 "(%d)", 538 reta_size, tbl_sz); 539 return -EINVAL; 540 } 541 542 num = tbl_sz / RTE_ETH_RETA_GROUP_SIZE; 543 544 for (i = 0; i < num; i++) { 545 for (j = 0; j < RTE_ETH_RETA_GROUP_SIZE; j++) { 546 if (reta_conf[i].mask & ((uint64_t)1 << j)) { 547 index = (i * RTE_ETH_RETA_GROUP_SIZE) + j; 548 lif->rss_ind_tbl[index] = reta_conf[i].reta[j]; 549 } 550 } 551 } 552 553 return ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL); 554 } 555 556 static int 557 ionic_dev_rss_reta_query(struct rte_eth_dev *eth_dev, 558 struct rte_eth_rss_reta_entry64 *reta_conf, 559 uint16_t reta_size) 560 { 561 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 562 struct ionic_adapter *adapter = lif->adapter; 563 struct ionic_identity *ident = &adapter->ident; 564 int i, num; 565 uint16_t tbl_sz = rte_le_to_cpu_16(ident->lif.eth.rss_ind_tbl_sz); 566 567 IONIC_PRINT_CALL(); 568 569 if (reta_size != tbl_sz) { 570 IONIC_PRINT(ERR, "The size of hash lookup table configured " 571 "(%d) does not match the number hardware can support " 572 "(%d)", 573 reta_size, tbl_sz); 574 return -EINVAL; 575 } 576 577 if (!lif->rss_ind_tbl) { 578 IONIC_PRINT(ERR, "RSS RETA has not been built yet"); 579 return -EINVAL; 580 } 581 582 num = reta_size / RTE_ETH_RETA_GROUP_SIZE; 583 584 for (i = 0; i < num; i++) { 585 memcpy(reta_conf->reta, 586 &lif->rss_ind_tbl[i * RTE_ETH_RETA_GROUP_SIZE], 587 RTE_ETH_RETA_GROUP_SIZE); 588 reta_conf++; 589 } 590 591 return 0; 592 } 593 594 static int 595 ionic_dev_rss_hash_conf_get(struct rte_eth_dev *eth_dev, 596 struct rte_eth_rss_conf *rss_conf) 597 { 598 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 599 uint64_t rss_hf = 0; 600 601 IONIC_PRINT_CALL(); 602 603 if (!lif->rss_ind_tbl) { 604 IONIC_PRINT(NOTICE, "RSS not enabled"); 605 return 0; 606 } 607 608 /* Get key value (if not null, rss_key is 40-byte) */ 609 if (rss_conf->rss_key != NULL && 610 rss_conf->rss_key_len >= IONIC_RSS_HASH_KEY_SIZE) 611 memcpy(rss_conf->rss_key, lif->rss_hash_key, 612 IONIC_RSS_HASH_KEY_SIZE); 613 614 if (lif->rss_types & IONIC_RSS_TYPE_IPV4) 615 rss_hf |= RTE_ETH_RSS_IPV4; 616 if (lif->rss_types & IONIC_RSS_TYPE_IPV4_TCP) 617 rss_hf |= RTE_ETH_RSS_NONFRAG_IPV4_TCP; 618 if (lif->rss_types & IONIC_RSS_TYPE_IPV4_UDP) 619 rss_hf |= RTE_ETH_RSS_NONFRAG_IPV4_UDP; 620 if (lif->rss_types & IONIC_RSS_TYPE_IPV6) 621 rss_hf |= RTE_ETH_RSS_IPV6; 622 if (lif->rss_types & IONIC_RSS_TYPE_IPV6_TCP) 623 rss_hf |= RTE_ETH_RSS_NONFRAG_IPV6_TCP; 624 if (lif->rss_types & IONIC_RSS_TYPE_IPV6_UDP) 625 rss_hf |= RTE_ETH_RSS_NONFRAG_IPV6_UDP; 626 627 rss_conf->rss_hf = rss_hf; 628 629 return 0; 630 } 631 632 static int 633 ionic_dev_rss_hash_update(struct rte_eth_dev *eth_dev, 634 struct rte_eth_rss_conf *rss_conf) 635 { 636 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 637 uint32_t rss_types = 0; 638 uint8_t *key = NULL; 639 640 IONIC_PRINT_CALL(); 641 642 if (rss_conf->rss_key) 643 key = rss_conf->rss_key; 644 645 if ((rss_conf->rss_hf & IONIC_ETH_RSS_OFFLOAD_ALL) == 0) { 646 /* 647 * Can't disable rss through hash flags, 648 * if it is enabled by default during init 649 */ 650 if (lif->rss_ind_tbl) 651 return -EINVAL; 652 } else { 653 /* Can't enable rss if disabled by default during init */ 654 if (!lif->rss_ind_tbl) 655 return -EINVAL; 656 657 if (rss_conf->rss_hf & RTE_ETH_RSS_IPV4) 658 rss_types |= IONIC_RSS_TYPE_IPV4; 659 if (rss_conf->rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_TCP) 660 rss_types |= IONIC_RSS_TYPE_IPV4_TCP; 661 if (rss_conf->rss_hf & RTE_ETH_RSS_NONFRAG_IPV4_UDP) 662 rss_types |= IONIC_RSS_TYPE_IPV4_UDP; 663 if (rss_conf->rss_hf & RTE_ETH_RSS_IPV6) 664 rss_types |= IONIC_RSS_TYPE_IPV6; 665 if (rss_conf->rss_hf & RTE_ETH_RSS_NONFRAG_IPV6_TCP) 666 rss_types |= IONIC_RSS_TYPE_IPV6_TCP; 667 if (rss_conf->rss_hf & RTE_ETH_RSS_NONFRAG_IPV6_UDP) 668 rss_types |= IONIC_RSS_TYPE_IPV6_UDP; 669 670 ionic_lif_rss_config(lif, rss_types, key, NULL); 671 } 672 673 return 0; 674 } 675 676 static int 677 ionic_dev_stats_get(struct rte_eth_dev *eth_dev, 678 struct rte_eth_stats *stats) 679 { 680 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 681 682 ionic_lif_get_stats(lif, stats); 683 684 return 0; 685 } 686 687 static int 688 ionic_dev_stats_reset(struct rte_eth_dev *eth_dev) 689 { 690 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 691 692 IONIC_PRINT_CALL(); 693 694 ionic_lif_reset_stats(lif); 695 696 return 0; 697 } 698 699 static int 700 ionic_dev_xstats_get_names(__rte_unused struct rte_eth_dev *eth_dev, 701 struct rte_eth_xstat_name *xstats_names, 702 __rte_unused unsigned int size) 703 { 704 unsigned int i; 705 706 if (xstats_names != NULL) { 707 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 708 snprintf(xstats_names[i].name, 709 sizeof(xstats_names[i].name), 710 "%s", rte_ionic_xstats_strings[i].name); 711 } 712 } 713 714 return IONIC_NB_HW_STATS; 715 } 716 717 static int 718 ionic_dev_xstats_get_names_by_id(struct rte_eth_dev *eth_dev, 719 const uint64_t *ids, struct rte_eth_xstat_name *xstats_names, 720 unsigned int limit) 721 { 722 struct rte_eth_xstat_name xstats_names_copy[IONIC_NB_HW_STATS]; 723 uint16_t i; 724 725 if (!ids) { 726 if (xstats_names != NULL) { 727 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 728 snprintf(xstats_names[i].name, 729 sizeof(xstats_names[i].name), 730 "%s", rte_ionic_xstats_strings[i].name); 731 } 732 } 733 734 return IONIC_NB_HW_STATS; 735 } 736 737 ionic_dev_xstats_get_names_by_id(eth_dev, NULL, xstats_names_copy, 738 IONIC_NB_HW_STATS); 739 740 for (i = 0; i < limit; i++) { 741 if (ids[i] >= IONIC_NB_HW_STATS) { 742 IONIC_PRINT(ERR, "id value isn't valid"); 743 return -1; 744 } 745 746 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 747 } 748 749 return limit; 750 } 751 752 static int 753 ionic_dev_xstats_get(struct rte_eth_dev *eth_dev, struct rte_eth_xstat *xstats, 754 unsigned int n) 755 { 756 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 757 struct ionic_lif_stats hw_stats; 758 uint16_t i; 759 760 if (n < IONIC_NB_HW_STATS) 761 return IONIC_NB_HW_STATS; 762 763 ionic_lif_get_hw_stats(lif, &hw_stats); 764 765 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 766 xstats[i].value = *(uint64_t *)(((char *)&hw_stats) + 767 rte_ionic_xstats_strings[i].offset); 768 xstats[i].id = i; 769 } 770 771 return IONIC_NB_HW_STATS; 772 } 773 774 static int 775 ionic_dev_xstats_get_by_id(struct rte_eth_dev *eth_dev, const uint64_t *ids, 776 uint64_t *values, unsigned int n) 777 { 778 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 779 struct ionic_lif_stats hw_stats; 780 uint64_t values_copy[IONIC_NB_HW_STATS]; 781 uint16_t i; 782 783 if (!ids) { 784 if (!ids && n < IONIC_NB_HW_STATS) 785 return IONIC_NB_HW_STATS; 786 787 ionic_lif_get_hw_stats(lif, &hw_stats); 788 789 for (i = 0; i < IONIC_NB_HW_STATS; i++) { 790 values[i] = *(uint64_t *)(((char *)&hw_stats) + 791 rte_ionic_xstats_strings[i].offset); 792 } 793 794 return IONIC_NB_HW_STATS; 795 } 796 797 ionic_dev_xstats_get_by_id(eth_dev, NULL, values_copy, 798 IONIC_NB_HW_STATS); 799 800 for (i = 0; i < n; i++) { 801 if (ids[i] >= IONIC_NB_HW_STATS) { 802 IONIC_PRINT(ERR, "id value isn't valid"); 803 return -1; 804 } 805 806 values[i] = values_copy[ids[i]]; 807 } 808 809 return n; 810 } 811 812 static int 813 ionic_dev_xstats_reset(struct rte_eth_dev *eth_dev) 814 { 815 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 816 817 ionic_lif_reset_hw_stats(lif); 818 819 return 0; 820 } 821 822 static int 823 ionic_dev_configure(struct rte_eth_dev *eth_dev) 824 { 825 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 826 827 IONIC_PRINT_CALL(); 828 829 ionic_lif_configure(lif); 830 831 ionic_lif_set_features(lif); 832 833 return 0; 834 } 835 836 static inline uint32_t 837 ionic_parse_link_speeds(uint16_t link_speeds) 838 { 839 if (link_speeds & RTE_ETH_LINK_SPEED_100G) 840 return 100000; 841 else if (link_speeds & RTE_ETH_LINK_SPEED_50G) 842 return 50000; 843 else if (link_speeds & RTE_ETH_LINK_SPEED_40G) 844 return 40000; 845 else if (link_speeds & RTE_ETH_LINK_SPEED_25G) 846 return 25000; 847 else if (link_speeds & RTE_ETH_LINK_SPEED_10G) 848 return 10000; 849 else 850 return 0; 851 } 852 853 /* 854 * Configure device link speed and setup link. 855 * It returns 0 on success. 856 */ 857 static int 858 ionic_dev_start(struct rte_eth_dev *eth_dev) 859 { 860 struct rte_eth_conf *dev_conf = ð_dev->data->dev_conf; 861 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 862 struct ionic_adapter *adapter = lif->adapter; 863 struct ionic_dev *idev = &adapter->idev; 864 uint32_t speed = 0, allowed_speeds; 865 uint8_t an_enable; 866 int err; 867 868 IONIC_PRINT_CALL(); 869 870 allowed_speeds = 871 RTE_ETH_LINK_SPEED_FIXED | 872 RTE_ETH_LINK_SPEED_10G | 873 RTE_ETH_LINK_SPEED_25G | 874 RTE_ETH_LINK_SPEED_40G | 875 RTE_ETH_LINK_SPEED_50G | 876 RTE_ETH_LINK_SPEED_100G; 877 878 if (dev_conf->link_speeds & ~allowed_speeds) { 879 IONIC_PRINT(ERR, "Invalid link setting"); 880 return -EINVAL; 881 } 882 883 if (dev_conf->lpbk_mode) 884 IONIC_PRINT(WARNING, "Loopback mode not supported"); 885 886 lif->frame_size = eth_dev->data->mtu + IONIC_ETH_OVERHEAD; 887 888 err = ionic_lif_change_mtu(lif, eth_dev->data->mtu); 889 if (err) { 890 IONIC_PRINT(ERR, "Cannot set LIF frame size %u: %d", 891 lif->frame_size, err); 892 return err; 893 } 894 895 err = ionic_lif_start(lif); 896 if (err) { 897 IONIC_PRINT(ERR, "Cannot start LIF: %d", err); 898 return err; 899 } 900 901 /* Configure link */ 902 an_enable = (dev_conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) == 0; 903 904 ionic_dev_cmd_port_autoneg(idev, an_enable); 905 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 906 if (err) 907 IONIC_PRINT(WARNING, "Failed to %s autonegotiation", 908 an_enable ? "enable" : "disable"); 909 910 if (!an_enable) 911 speed = ionic_parse_link_speeds(dev_conf->link_speeds); 912 if (speed) { 913 ionic_dev_cmd_port_speed(idev, speed); 914 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT); 915 if (err) 916 IONIC_PRINT(WARNING, "Failed to set link speed %u", 917 speed); 918 } 919 920 ionic_dev_link_update(eth_dev, 0); 921 922 return 0; 923 } 924 925 /* 926 * Stop device: disable rx and tx functions to allow for reconfiguring. 927 */ 928 static int 929 ionic_dev_stop(struct rte_eth_dev *eth_dev) 930 { 931 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 932 933 IONIC_PRINT_CALL(); 934 935 ionic_lif_stop(lif); 936 937 return 0; 938 } 939 940 /* 941 * Reset and stop device. 942 */ 943 static int 944 ionic_dev_close(struct rte_eth_dev *eth_dev) 945 { 946 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 947 struct ionic_adapter *adapter = lif->adapter; 948 949 IONIC_PRINT_CALL(); 950 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 951 return 0; 952 953 ionic_lif_stop(lif); 954 955 ionic_lif_free_queues(lif); 956 957 IONIC_PRINT(NOTICE, "Removing device %s", eth_dev->device->name); 958 if (adapter->intf->unconfigure_intr) 959 (*adapter->intf->unconfigure_intr)(adapter); 960 961 rte_eth_dev_destroy(eth_dev, eth_ionic_dev_uninit); 962 963 ionic_port_reset(adapter); 964 ionic_reset(adapter); 965 if (adapter->intf->unmap_bars) 966 (*adapter->intf->unmap_bars)(adapter); 967 968 rte_free(adapter); 969 970 return 0; 971 } 972 973 int 974 eth_ionic_dev_init(struct rte_eth_dev *eth_dev, void *init_params) 975 { 976 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 977 struct ionic_adapter *adapter = (struct ionic_adapter *)init_params; 978 int err; 979 980 IONIC_PRINT_CALL(); 981 982 eth_dev->dev_ops = &ionic_eth_dev_ops; 983 eth_dev->rx_pkt_burst = &ionic_recv_pkts; 984 eth_dev->tx_pkt_burst = &ionic_xmit_pkts; 985 eth_dev->tx_pkt_prepare = &ionic_prep_pkts; 986 987 eth_dev->rx_descriptor_status = ionic_dev_rx_descriptor_status; 988 989 /* Multi-process not supported, primary does initialization anyway */ 990 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 991 return 0; 992 993 if (adapter->intf->copy_bus_info) 994 (*adapter->intf->copy_bus_info)(adapter, eth_dev); 995 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 996 997 lif->eth_dev = eth_dev; 998 lif->adapter = adapter; 999 adapter->lif = lif; 1000 1001 IONIC_PRINT(DEBUG, "Up to %u MAC addresses supported", 1002 adapter->max_mac_addrs); 1003 1004 /* Allocate memory for storing MAC addresses */ 1005 eth_dev->data->mac_addrs = rte_zmalloc("ionic", 1006 RTE_ETHER_ADDR_LEN * adapter->max_mac_addrs, 0); 1007 1008 if (eth_dev->data->mac_addrs == NULL) { 1009 IONIC_PRINT(ERR, "Failed to allocate %u bytes needed to " 1010 "store MAC addresses", 1011 RTE_ETHER_ADDR_LEN * adapter->max_mac_addrs); 1012 err = -ENOMEM; 1013 goto err; 1014 } 1015 1016 err = ionic_lif_alloc(lif); 1017 if (err) { 1018 IONIC_PRINT(ERR, "Cannot allocate LIFs: %d, aborting", 1019 err); 1020 goto err; 1021 } 1022 1023 err = ionic_lif_init(lif); 1024 if (err) { 1025 IONIC_PRINT(ERR, "Cannot init LIFs: %d, aborting", err); 1026 goto err_free_lif; 1027 } 1028 1029 /* Copy the MAC address */ 1030 rte_ether_addr_copy((struct rte_ether_addr *)lif->mac_addr, 1031 ð_dev->data->mac_addrs[0]); 1032 1033 IONIC_PRINT(DEBUG, "Port %u initialized", eth_dev->data->port_id); 1034 1035 return 0; 1036 1037 err_free_lif: 1038 ionic_lif_free(lif); 1039 err: 1040 return err; 1041 } 1042 1043 static int 1044 eth_ionic_dev_uninit(struct rte_eth_dev *eth_dev) 1045 { 1046 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev); 1047 struct ionic_adapter *adapter = lif->adapter; 1048 1049 IONIC_PRINT_CALL(); 1050 1051 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1052 return 0; 1053 1054 adapter->lif = NULL; 1055 1056 ionic_lif_deinit(lif); 1057 ionic_lif_free(lif); 1058 1059 if (!(lif->state & IONIC_LIF_F_FW_RESET)) 1060 ionic_lif_reset(lif); 1061 1062 return 0; 1063 } 1064 1065 int 1066 eth_ionic_dev_probe(void *bus_dev, struct rte_device *rte_dev, 1067 struct ionic_bars *bars, const struct ionic_dev_intf *intf, 1068 uint16_t device_id, uint16_t vendor_id) 1069 { 1070 char name[RTE_ETH_NAME_MAX_LEN]; 1071 struct ionic_adapter *adapter; 1072 struct ionic_hw *hw; 1073 unsigned long i; 1074 int err; 1075 1076 /* Check structs (trigger error at compilation time) */ 1077 ionic_struct_size_checks(); 1078 1079 /* Multi-process not supported */ 1080 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1081 err = -EPERM; 1082 goto err; 1083 } 1084 1085 adapter = rte_zmalloc("ionic", sizeof(*adapter), 0); 1086 if (!adapter) { 1087 IONIC_PRINT(ERR, "OOM"); 1088 err = -ENOMEM; 1089 goto err; 1090 } 1091 1092 adapter->bus_dev = bus_dev; 1093 hw = &adapter->hw; 1094 1095 /* Vendor and Device ID need to be set before init of shared code */ 1096 hw->device_id = device_id; 1097 hw->vendor_id = vendor_id; 1098 1099 err = ionic_init_mac(hw); 1100 if (err != 0) { 1101 IONIC_PRINT(ERR, "Mac init failed: %d", err); 1102 err = -EIO; 1103 goto err_free_adapter; 1104 } 1105 1106 adapter->bars.num_bars = bars->num_bars; 1107 for (i = 0; i < bars->num_bars; i++) { 1108 adapter->bars.bar[i].vaddr = bars->bar[i].vaddr; 1109 adapter->bars.bar[i].bus_addr = bars->bar[i].bus_addr; 1110 adapter->bars.bar[i].len = bars->bar[i].len; 1111 } 1112 1113 if (intf->setup == NULL) { 1114 IONIC_PRINT(ERR, "Device setup function is mandatory"); 1115 goto err_free_adapter; 1116 } 1117 1118 adapter->intf = intf; 1119 1120 /* Discover ionic dev resources */ 1121 err = ionic_setup(adapter); 1122 if (err) { 1123 IONIC_PRINT(ERR, "Cannot setup device: %d, aborting", err); 1124 goto err_free_adapter; 1125 } 1126 1127 err = ionic_identify(adapter); 1128 if (err) { 1129 IONIC_PRINT(ERR, "Cannot identify device: %d, aborting", 1130 err); 1131 goto err_free_adapter; 1132 } 1133 1134 err = ionic_init(adapter); 1135 if (err) { 1136 IONIC_PRINT(ERR, "Cannot init device: %d, aborting", err); 1137 goto err_free_adapter; 1138 } 1139 1140 /* Configure the ports */ 1141 err = ionic_port_identify(adapter); 1142 if (err) { 1143 IONIC_PRINT(ERR, "Cannot identify port: %d, aborting", 1144 err); 1145 goto err_free_adapter; 1146 } 1147 1148 err = ionic_port_init(adapter); 1149 if (err) { 1150 IONIC_PRINT(ERR, "Cannot init port: %d, aborting", err); 1151 goto err_free_adapter; 1152 } 1153 1154 /* Configure LIFs */ 1155 err = ionic_lif_identify(adapter); 1156 if (err) { 1157 IONIC_PRINT(ERR, "Cannot identify lif: %d, aborting", err); 1158 goto err_free_adapter; 1159 } 1160 1161 /* Allocate and init LIFs */ 1162 err = ionic_lifs_size(adapter); 1163 if (err) { 1164 IONIC_PRINT(ERR, "Cannot size LIFs: %d, aborting", err); 1165 goto err_free_adapter; 1166 } 1167 1168 adapter->max_mac_addrs = 1169 rte_le_to_cpu_32(adapter->ident.lif.eth.max_ucast_filters); 1170 1171 if (rte_le_to_cpu_32(adapter->ident.dev.nlifs) != 1) { 1172 IONIC_PRINT(ERR, "Unexpected request for %d LIFs", 1173 rte_le_to_cpu_32(adapter->ident.dev.nlifs)); 1174 goto err_free_adapter; 1175 } 1176 1177 snprintf(name, sizeof(name), "%s_lif", rte_dev->name); 1178 err = rte_eth_dev_create(rte_dev, name, sizeof(struct ionic_lif), 1179 NULL, NULL, eth_ionic_dev_init, adapter); 1180 if (err) { 1181 IONIC_PRINT(ERR, "Cannot create eth device for %s", name); 1182 goto err_free_adapter; 1183 } 1184 1185 if (adapter->intf->configure_intr) { 1186 err = (*adapter->intf->configure_intr)(adapter); 1187 if (err) { 1188 IONIC_PRINT(ERR, "Failed to configure interrupts"); 1189 goto err_free_adapter; 1190 } 1191 } 1192 1193 return 0; 1194 1195 err_free_adapter: 1196 rte_free(adapter); 1197 err: 1198 return err; 1199 } 1200 1201 int 1202 eth_ionic_dev_remove(struct rte_device *rte_dev) 1203 { 1204 char name[RTE_ETH_NAME_MAX_LEN]; 1205 struct rte_eth_dev *eth_dev; 1206 1207 /* Adapter lookup is using the eth_dev name */ 1208 snprintf(name, sizeof(name), "%s_lif", rte_dev->name); 1209 1210 eth_dev = rte_eth_dev_allocated(name); 1211 if (eth_dev) 1212 ionic_dev_close(eth_dev); 1213 else 1214 IONIC_PRINT(DEBUG, "Cannot find device %s", rte_dev->name); 1215 1216 return 0; 1217 } 1218 1219 RTE_LOG_REGISTER_DEFAULT(ionic_logtype, NOTICE); 1220