1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018-2022 Advanced Micro Devices, Inc. 3 */ 4 5 #ifndef _IONIC_DEV_H_ 6 #define _IONIC_DEV_H_ 7 8 #include <stdbool.h> 9 10 #include "ionic_osdep.h" 11 #include "ionic_if.h" 12 #include "ionic_regs.h" 13 14 #define VLAN_TAG_SIZE 4 15 16 #define IONIC_MIN_MTU RTE_ETHER_MIN_MTU 17 #define IONIC_MAX_MTU 9378 18 #define IONIC_ETH_OVERHEAD (RTE_ETHER_HDR_LEN + VLAN_TAG_SIZE) 19 20 #define IONIC_MAX_RING_DESC 32768 21 #define IONIC_MIN_RING_DESC 16 22 #define IONIC_DEF_TXRX_DESC 4096 23 24 #define IONIC_LIFS_MAX 1024 25 26 #define IONIC_DEVCMD_TIMEOUT 5 /* devcmd_timeout */ 27 #define IONIC_DEVCMD_CHECK_PERIOD_US 10 /* devcmd status chk period */ 28 29 #define IONIC_ALIGN 4096 30 31 struct ionic_adapter; 32 33 struct ionic_dev_bar { 34 void __iomem *vaddr; 35 rte_iova_t bus_addr; 36 unsigned long len; 37 }; 38 39 static inline void ionic_struct_size_checks(void) 40 { 41 RTE_BUILD_BUG_ON(sizeof(struct ionic_doorbell) != 8); 42 RTE_BUILD_BUG_ON(sizeof(struct ionic_intr) != 32); 43 RTE_BUILD_BUG_ON(sizeof(struct ionic_intr_status) != 8); 44 45 RTE_BUILD_BUG_ON(sizeof(union ionic_dev_regs) != 4096); 46 RTE_BUILD_BUG_ON(sizeof(union ionic_dev_info_regs) != 2048); 47 RTE_BUILD_BUG_ON(sizeof(union ionic_dev_cmd_regs) != 2048); 48 49 RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_stats) != 1024); 50 51 RTE_BUILD_BUG_ON(sizeof(struct ionic_admin_cmd) != 64); 52 RTE_BUILD_BUG_ON(sizeof(struct ionic_admin_comp) != 16); 53 RTE_BUILD_BUG_ON(sizeof(struct ionic_nop_cmd) != 64); 54 RTE_BUILD_BUG_ON(sizeof(struct ionic_nop_comp) != 16); 55 56 /* Device commands */ 57 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_identify_cmd) != 64); 58 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_identify_comp) != 16); 59 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_init_cmd) != 64); 60 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_init_comp) != 16); 61 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_reset_cmd) != 64); 62 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_reset_comp) != 16); 63 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_getattr_cmd) != 64); 64 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_getattr_comp) != 16); 65 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_setattr_cmd) != 64); 66 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_setattr_comp) != 16); 67 68 /* Port commands */ 69 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_identify_cmd) != 64); 70 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_identify_comp) != 16); 71 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_init_cmd) != 64); 72 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_init_comp) != 16); 73 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_reset_cmd) != 64); 74 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_reset_comp) != 16); 75 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_getattr_cmd) != 64); 76 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_getattr_comp) != 16); 77 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_setattr_cmd) != 64); 78 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_setattr_comp) != 16); 79 80 /* LIF commands */ 81 RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_init_cmd) != 64); 82 RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_init_comp) != 16); 83 RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_reset_cmd) != 64); 84 RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_getattr_cmd) != 64); 85 RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_getattr_comp) != 16); 86 RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_setattr_cmd) != 64); 87 RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_setattr_comp) != 16); 88 89 RTE_BUILD_BUG_ON(sizeof(struct ionic_q_init_cmd) != 64); 90 RTE_BUILD_BUG_ON(sizeof(struct ionic_q_init_comp) != 16); 91 RTE_BUILD_BUG_ON(sizeof(struct ionic_q_control_cmd) != 64); 92 93 RTE_BUILD_BUG_ON(sizeof(struct ionic_rx_mode_set_cmd) != 64); 94 RTE_BUILD_BUG_ON(sizeof(struct ionic_rx_filter_add_cmd) != 64); 95 RTE_BUILD_BUG_ON(sizeof(struct ionic_rx_filter_add_comp) != 16); 96 97 /* RDMA commands */ 98 RTE_BUILD_BUG_ON(sizeof(struct ionic_rdma_reset_cmd) != 64); 99 RTE_BUILD_BUG_ON(sizeof(struct ionic_rdma_queue_cmd) != 64); 100 101 /* Events */ 102 RTE_BUILD_BUG_ON(sizeof(struct ionic_notifyq_cmd) != 4); 103 RTE_BUILD_BUG_ON(sizeof(union ionic_notifyq_comp) != 64); 104 RTE_BUILD_BUG_ON(sizeof(struct ionic_notifyq_event) != 64); 105 RTE_BUILD_BUG_ON(sizeof(struct ionic_link_change_event) != 64); 106 RTE_BUILD_BUG_ON(sizeof(struct ionic_reset_event) != 64); 107 RTE_BUILD_BUG_ON(sizeof(struct ionic_heartbeat_event) != 64); 108 RTE_BUILD_BUG_ON(sizeof(struct ionic_log_event) != 64); 109 110 /* I/O */ 111 RTE_BUILD_BUG_ON(sizeof(struct ionic_txq_desc) != 16); 112 RTE_BUILD_BUG_ON(sizeof(struct ionic_txq_sg_desc_v1) != 256); 113 RTE_BUILD_BUG_ON(sizeof(struct ionic_txq_comp) != 16); 114 115 RTE_BUILD_BUG_ON(sizeof(struct ionic_rxq_desc) != 16); 116 RTE_BUILD_BUG_ON(sizeof(struct ionic_rxq_sg_desc) != 128); 117 RTE_BUILD_BUG_ON(sizeof(struct ionic_rxq_comp) != 16); 118 } 119 120 struct ionic_dev { 121 union ionic_dev_info_regs __iomem *dev_info; 122 union ionic_dev_cmd_regs __iomem *dev_cmd; 123 124 struct ionic_doorbell __iomem *db_pages; 125 struct ionic_intr __iomem *intr_ctrl; 126 struct ionic_intr_status __iomem *intr_status; 127 128 struct ionic_port_info *port_info; 129 const struct rte_memzone *port_info_z; 130 rte_iova_t port_info_pa; 131 uint32_t port_info_sz; 132 }; 133 134 #define Q_NEXT_TO_POST(_q, _n) (((_q)->head_idx + (_n)) & ((_q)->size_mask)) 135 #define Q_NEXT_TO_SRVC(_q, _n) (((_q)->tail_idx + (_n)) & ((_q)->size_mask)) 136 137 #define IONIC_INFO_IDX(_q, _i) (_i) 138 #define IONIC_INFO_PTR(_q, _i) (&(_q)->info[IONIC_INFO_IDX((_q), _i)]) 139 140 struct ionic_queue { 141 uint16_t num_descs; 142 uint16_t head_idx; 143 uint16_t tail_idx; 144 uint16_t size_mask; 145 uint8_t type; 146 uint8_t hw_type; 147 void *base; 148 void *sg_base; 149 struct ionic_doorbell __iomem *db; 150 void **info; 151 152 uint32_t index; 153 uint32_t hw_index; 154 rte_iova_t base_pa; 155 rte_iova_t sg_base_pa; 156 }; 157 158 #define IONIC_INTR_NONE (-1) 159 160 struct ionic_intr_info { 161 int index; 162 uint32_t vector; 163 struct ionic_intr __iomem *ctrl; 164 }; 165 166 struct ionic_cq { 167 uint16_t tail_idx; 168 uint16_t num_descs; 169 uint16_t size_mask; 170 bool done_color; 171 void *base; 172 rte_iova_t base_pa; 173 }; 174 175 struct ionic_lif; 176 struct ionic_adapter; 177 struct ionic_qcq; 178 179 void ionic_intr_init(struct ionic_dev *idev, struct ionic_intr_info *intr, 180 unsigned long index); 181 182 const char *ionic_opcode_to_str(enum ionic_cmd_opcode opcode); 183 184 int ionic_dev_setup(struct ionic_adapter *adapter); 185 186 void ionic_dev_cmd_go(struct ionic_dev *idev, union ionic_dev_cmd *cmd); 187 uint8_t ionic_dev_cmd_status(struct ionic_dev *idev); 188 bool ionic_dev_cmd_done(struct ionic_dev *idev); 189 void ionic_dev_cmd_comp(struct ionic_dev *idev, void *mem); 190 191 void ionic_dev_cmd_identify(struct ionic_dev *idev, uint8_t ver); 192 void ionic_dev_cmd_init(struct ionic_dev *idev); 193 void ionic_dev_cmd_reset(struct ionic_dev *idev); 194 195 void ionic_dev_cmd_port_identify(struct ionic_dev *idev); 196 void ionic_dev_cmd_port_init(struct ionic_dev *idev); 197 void ionic_dev_cmd_port_reset(struct ionic_dev *idev); 198 void ionic_dev_cmd_port_state(struct ionic_dev *idev, uint8_t state); 199 void ionic_dev_cmd_port_speed(struct ionic_dev *idev, uint32_t speed); 200 void ionic_dev_cmd_port_mtu(struct ionic_dev *idev, uint32_t mtu); 201 void ionic_dev_cmd_port_autoneg(struct ionic_dev *idev, uint8_t an_enable); 202 void ionic_dev_cmd_port_fec(struct ionic_dev *idev, uint8_t fec_type); 203 void ionic_dev_cmd_port_pause(struct ionic_dev *idev, uint8_t pause_type); 204 void ionic_dev_cmd_port_loopback(struct ionic_dev *idev, 205 uint8_t loopback_mode); 206 207 void ionic_dev_cmd_queue_identify(struct ionic_dev *idev, 208 uint16_t lif_type, uint8_t qtype, uint8_t qver); 209 210 void ionic_dev_cmd_lif_identify(struct ionic_dev *idev, uint8_t type, 211 uint8_t ver); 212 void ionic_dev_cmd_lif_init(struct ionic_dev *idev, rte_iova_t addr); 213 void ionic_dev_cmd_lif_reset(struct ionic_dev *idev); 214 215 void ionic_dev_cmd_adminq_init(struct ionic_dev *idev, struct ionic_qcq *qcq); 216 217 struct ionic_doorbell __iomem *ionic_db_map(struct ionic_lif *lif, 218 struct ionic_queue *q); 219 220 int ionic_cq_init(struct ionic_cq *cq, uint16_t num_descs); 221 void ionic_cq_map(struct ionic_cq *cq, void *base, rte_iova_t base_pa); 222 typedef bool (*ionic_cq_cb)(struct ionic_cq *cq, uint16_t cq_desc_index, 223 void *cb_arg); 224 uint32_t ionic_cq_service(struct ionic_cq *cq, uint32_t work_to_do, 225 ionic_cq_cb cb, void *cb_arg); 226 227 int ionic_q_init(struct ionic_queue *q, uint32_t index, uint16_t num_descs); 228 void ionic_q_map(struct ionic_queue *q, void *base, rte_iova_t base_pa); 229 void ionic_q_sg_map(struct ionic_queue *q, void *base, rte_iova_t base_pa); 230 231 static inline uint16_t 232 ionic_q_space_avail(struct ionic_queue *q) 233 { 234 uint16_t avail = q->tail_idx; 235 236 if (q->head_idx >= avail) 237 avail += q->num_descs - q->head_idx - 1; 238 else 239 avail -= q->head_idx + 1; 240 241 return avail; 242 } 243 244 static inline void 245 ionic_q_flush(struct ionic_queue *q) 246 { 247 uint64_t val = IONIC_DBELL_QID(q->hw_index) | q->head_idx; 248 249 rte_write64(rte_cpu_to_le_64(val), q->db); 250 } 251 252 #endif /* _IONIC_DEV_H_ */ 253