1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018-2022 Advanced Micro Devices, Inc. 3 */ 4 5 #ifndef _IONIC_DEV_H_ 6 #define _IONIC_DEV_H_ 7 8 #include <stdbool.h> 9 10 #include "ionic_osdep.h" 11 #include "ionic_if.h" 12 #include "ionic_regs.h" 13 14 #define VLAN_TAG_SIZE 4 15 16 #define IONIC_MIN_MTU RTE_ETHER_MIN_MTU 17 #define IONIC_MAX_MTU 9378 18 #define IONIC_ETH_OVERHEAD (RTE_ETHER_HDR_LEN + VLAN_TAG_SIZE) 19 20 #define IONIC_MAX_RING_DESC 32768 21 #define IONIC_MIN_RING_DESC 16 22 #define IONIC_DEF_TXRX_DESC 4096 23 #define IONIC_DEF_TXRX_BURST 32 24 25 #define IONIC_DEVCMD_TIMEOUT 5 /* devcmd_timeout */ 26 #define IONIC_DEVCMD_CHECK_PERIOD_US 10 /* devcmd status chk period */ 27 #define IONIC_DEVCMD_RETRY_WAIT_US 20000 28 29 #define IONIC_Q_WDOG_MS 10 /* 10ms */ 30 #define IONIC_Q_WDOG_MAX_MS 5000 /* 5s */ 31 #define IONIC_ADMINQ_WDOG_MS 500 /* 500ms */ 32 33 #define IONIC_ALIGN 4096 34 35 struct ionic_adapter; 36 37 struct ionic_dev_bar { 38 void __iomem *vaddr; 39 rte_iova_t bus_addr; 40 unsigned long len; 41 }; 42 43 static inline void ionic_struct_size_checks(void) 44 { 45 RTE_BUILD_BUG_ON(sizeof(struct ionic_doorbell) != 8); 46 RTE_BUILD_BUG_ON(sizeof(struct ionic_intr) != 32); 47 RTE_BUILD_BUG_ON(sizeof(struct ionic_intr_status) != 8); 48 49 RTE_BUILD_BUG_ON(sizeof(union ionic_dev_regs) != 4096); 50 RTE_BUILD_BUG_ON(sizeof(union ionic_dev_info_regs) != 2048); 51 RTE_BUILD_BUG_ON(sizeof(union ionic_dev_cmd_regs) != 2048); 52 53 RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_stats) != 1024); 54 55 RTE_BUILD_BUG_ON(sizeof(struct ionic_admin_cmd) != 64); 56 RTE_BUILD_BUG_ON(sizeof(struct ionic_admin_comp) != 16); 57 RTE_BUILD_BUG_ON(sizeof(struct ionic_nop_cmd) != 64); 58 RTE_BUILD_BUG_ON(sizeof(struct ionic_nop_comp) != 16); 59 60 /* Device commands */ 61 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_identify_cmd) != 64); 62 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_identify_comp) != 16); 63 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_init_cmd) != 64); 64 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_init_comp) != 16); 65 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_reset_cmd) != 64); 66 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_reset_comp) != 16); 67 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_getattr_cmd) != 64); 68 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_getattr_comp) != 16); 69 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_setattr_cmd) != 64); 70 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_setattr_comp) != 16); 71 72 /* Port commands */ 73 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_identify_cmd) != 64); 74 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_identify_comp) != 16); 75 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_init_cmd) != 64); 76 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_init_comp) != 16); 77 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_reset_cmd) != 64); 78 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_reset_comp) != 16); 79 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_getattr_cmd) != 64); 80 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_getattr_comp) != 16); 81 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_setattr_cmd) != 64); 82 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_setattr_comp) != 16); 83 84 /* LIF commands */ 85 RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_init_cmd) != 64); 86 RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_init_comp) != 16); 87 RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_reset_cmd) != 64); 88 RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_getattr_cmd) != 64); 89 RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_getattr_comp) != 16); 90 RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_setattr_cmd) != 64); 91 RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_setattr_comp) != 16); 92 93 RTE_BUILD_BUG_ON(sizeof(struct ionic_q_init_cmd) != 64); 94 RTE_BUILD_BUG_ON(sizeof(struct ionic_q_init_comp) != 16); 95 RTE_BUILD_BUG_ON(sizeof(struct ionic_q_control_cmd) != 64); 96 97 RTE_BUILD_BUG_ON(sizeof(struct ionic_rx_mode_set_cmd) != 64); 98 RTE_BUILD_BUG_ON(sizeof(struct ionic_rx_filter_add_cmd) != 64); 99 RTE_BUILD_BUG_ON(sizeof(struct ionic_rx_filter_add_comp) != 16); 100 101 /* RDMA commands */ 102 RTE_BUILD_BUG_ON(sizeof(struct ionic_rdma_reset_cmd) != 64); 103 RTE_BUILD_BUG_ON(sizeof(struct ionic_rdma_queue_cmd) != 64); 104 105 /* Events */ 106 RTE_BUILD_BUG_ON(sizeof(struct ionic_notifyq_cmd) != 4); 107 RTE_BUILD_BUG_ON(sizeof(union ionic_notifyq_comp) != 64); 108 RTE_BUILD_BUG_ON(sizeof(struct ionic_notifyq_event) != 64); 109 RTE_BUILD_BUG_ON(sizeof(struct ionic_link_change_event) != 64); 110 RTE_BUILD_BUG_ON(sizeof(struct ionic_reset_event) != 64); 111 RTE_BUILD_BUG_ON(sizeof(struct ionic_heartbeat_event) != 64); 112 RTE_BUILD_BUG_ON(sizeof(struct ionic_log_event) != 64); 113 114 /* I/O */ 115 RTE_BUILD_BUG_ON(sizeof(struct ionic_txq_desc) != 16); 116 RTE_BUILD_BUG_ON(sizeof(struct ionic_txq_sg_desc_v1) != 256); 117 RTE_BUILD_BUG_ON(sizeof(struct ionic_txq_comp) != 16); 118 119 RTE_BUILD_BUG_ON(sizeof(struct ionic_rxq_desc) != 16); 120 RTE_BUILD_BUG_ON(sizeof(struct ionic_rxq_sg_desc) != 128); 121 RTE_BUILD_BUG_ON(sizeof(struct ionic_rxq_comp) != 16); 122 } 123 124 struct ionic_dev { 125 union ionic_dev_info_regs __iomem *dev_info; 126 union ionic_dev_cmd_regs __iomem *dev_cmd; 127 128 struct ionic_doorbell __iomem *db_pages; 129 struct ionic_intr __iomem *intr_ctrl; 130 struct ionic_intr_status __iomem *intr_status; 131 132 struct ionic_port_info *port_info; 133 const struct rte_memzone *port_info_z; 134 rte_iova_t port_info_pa; 135 uint32_t port_info_sz; 136 }; 137 138 #define Q_NEXT_TO_POST(_q, _n) (((_q)->head_idx + (_n)) & ((_q)->size_mask)) 139 #define Q_NEXT_TO_SRVC(_q, _n) (((_q)->tail_idx + (_n)) & ((_q)->size_mask)) 140 141 #define IONIC_INFO_IDX(_q, _i) ((_i) * (_q)->num_segs) 142 #define IONIC_INFO_PTR(_q, _i) (&(_q)->info[IONIC_INFO_IDX((_q), _i)]) 143 144 struct ionic_queue { 145 uint16_t num_descs; 146 uint16_t num_segs; 147 uint16_t head_idx; 148 uint16_t tail_idx; 149 uint16_t size_mask; 150 uint8_t type; 151 uint8_t hw_type; 152 void *base; 153 void *sg_base; 154 struct ionic_doorbell __iomem *db; 155 void **info; 156 157 uint32_t index; 158 uint32_t hw_index; 159 rte_iova_t base_pa; 160 rte_iova_t sg_base_pa; 161 }; 162 163 #define IONIC_INTR_NONE (-1) 164 165 struct ionic_intr_info { 166 int index; 167 uint32_t vector; 168 struct ionic_intr __iomem *ctrl; 169 }; 170 171 struct ionic_cq { 172 uint16_t tail_idx; 173 uint16_t num_descs; 174 uint16_t size_mask; 175 bool done_color; 176 void *base; 177 rte_iova_t base_pa; 178 }; 179 180 struct ionic_lif; 181 struct ionic_adapter; 182 struct ionic_qcq; 183 struct rte_mempool; 184 struct rte_eth_dev; 185 struct rte_devargs; 186 187 struct ionic_dev_intf { 188 int (*setup)(struct ionic_adapter *adapter); 189 int (*devargs)(struct ionic_adapter *adapter, 190 struct rte_devargs *devargs); 191 void (*copy_bus_info)(struct ionic_adapter *adapter, 192 struct rte_eth_dev *eth_dev); 193 int (*configure_intr)(struct ionic_adapter *adapter); 194 void (*unconfigure_intr)(struct ionic_adapter *adapter); 195 void (*unmap_bars)(struct ionic_adapter *adapter); 196 }; 197 198 void ionic_intr_init(struct ionic_dev *idev, struct ionic_intr_info *intr, 199 unsigned long index); 200 201 const char *ionic_opcode_to_str(enum ionic_cmd_opcode opcode); 202 203 void ionic_dev_cmd_go(struct ionic_dev *idev, union ionic_dev_cmd *cmd); 204 uint8_t ionic_dev_cmd_status(struct ionic_dev *idev); 205 bool ionic_dev_cmd_done(struct ionic_dev *idev); 206 void ionic_dev_cmd_comp(struct ionic_dev *idev, void *mem); 207 208 void ionic_dev_cmd_identify(struct ionic_dev *idev, uint8_t ver); 209 void ionic_dev_cmd_init(struct ionic_dev *idev); 210 void ionic_dev_cmd_reset(struct ionic_dev *idev); 211 212 void ionic_dev_cmd_port_identify(struct ionic_dev *idev); 213 void ionic_dev_cmd_port_init(struct ionic_dev *idev); 214 void ionic_dev_cmd_port_reset(struct ionic_dev *idev); 215 void ionic_dev_cmd_port_state(struct ionic_dev *idev, uint8_t state); 216 void ionic_dev_cmd_port_speed(struct ionic_dev *idev, uint32_t speed); 217 void ionic_dev_cmd_port_mtu(struct ionic_dev *idev, uint32_t mtu); 218 void ionic_dev_cmd_port_autoneg(struct ionic_dev *idev, uint8_t an_enable); 219 void ionic_dev_cmd_port_fec(struct ionic_dev *idev, uint8_t fec_type); 220 void ionic_dev_cmd_port_pause(struct ionic_dev *idev, uint8_t pause_type); 221 void ionic_dev_cmd_port_loopback(struct ionic_dev *idev, 222 uint8_t loopback_mode); 223 224 void ionic_dev_cmd_queue_identify(struct ionic_dev *idev, 225 uint16_t lif_type, uint8_t qtype, uint8_t qver); 226 227 void ionic_dev_cmd_lif_identify(struct ionic_dev *idev, uint8_t type, 228 uint8_t ver); 229 void ionic_dev_cmd_lif_init(struct ionic_dev *idev, rte_iova_t addr); 230 void ionic_dev_cmd_lif_reset(struct ionic_dev *idev); 231 232 void ionic_dev_cmd_adminq_init(struct ionic_dev *idev, struct ionic_qcq *qcq); 233 234 struct ionic_doorbell __iomem *ionic_db_map(struct ionic_lif *lif, 235 struct ionic_queue *q); 236 237 int ionic_cq_init(struct ionic_cq *cq, uint16_t num_descs); 238 void ionic_cq_reset(struct ionic_cq *cq); 239 void ionic_cq_map(struct ionic_cq *cq, void *base, rte_iova_t base_pa); 240 typedef bool (*ionic_cq_cb)(struct ionic_cq *cq, uint16_t cq_desc_index, 241 void *cb_arg); 242 uint32_t ionic_cq_service(struct ionic_cq *cq, uint32_t work_to_do, 243 ionic_cq_cb cb, void *cb_arg); 244 245 int ionic_q_init(struct ionic_queue *q, uint32_t index, uint16_t num_descs); 246 void ionic_q_reset(struct ionic_queue *q); 247 void ionic_q_map(struct ionic_queue *q, void *base, rte_iova_t base_pa); 248 void ionic_q_sg_map(struct ionic_queue *q, void *base, rte_iova_t base_pa); 249 250 static inline uint16_t 251 ionic_q_space_avail(struct ionic_queue *q) 252 { 253 uint16_t avail = q->tail_idx; 254 255 if (q->head_idx >= avail) 256 avail += q->num_descs - q->head_idx - 1; 257 else 258 avail -= q->head_idx + 1; 259 260 return avail; 261 } 262 263 static inline void 264 ionic_q_flush(struct ionic_queue *q) 265 { 266 uint64_t val = IONIC_DBELL_QID(q->hw_index) | q->head_idx; 267 268 rte_write64(rte_cpu_to_le_64(val), q->db); 269 } 270 271 #endif /* _IONIC_DEV_H_ */ 272