1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018-2022 Advanced Micro Devices, Inc. 3 */ 4 5 #ifndef _IONIC_DEV_H_ 6 #define _IONIC_DEV_H_ 7 8 #include <stdbool.h> 9 10 #include "ionic_osdep.h" 11 #include "ionic_if.h" 12 #include "ionic_regs.h" 13 14 #define VLAN_TAG_SIZE 4 15 16 #define IONIC_MIN_MTU RTE_ETHER_MIN_MTU 17 #define IONIC_MAX_MTU 9378 18 #define IONIC_ETH_OVERHEAD (RTE_ETHER_HDR_LEN + VLAN_TAG_SIZE) 19 20 #define IONIC_MAX_RING_DESC 32768 21 #define IONIC_MIN_RING_DESC 16 22 #define IONIC_DEF_TXRX_DESC 4096 23 24 #define IONIC_DEVCMD_TIMEOUT 5 /* devcmd_timeout */ 25 #define IONIC_DEVCMD_CHECK_PERIOD_US 10 /* devcmd status chk period */ 26 27 #define IONIC_ALIGN 4096 28 29 struct ionic_adapter; 30 31 struct ionic_dev_bar { 32 void __iomem *vaddr; 33 rte_iova_t bus_addr; 34 unsigned long len; 35 }; 36 37 static inline void ionic_struct_size_checks(void) 38 { 39 RTE_BUILD_BUG_ON(sizeof(struct ionic_doorbell) != 8); 40 RTE_BUILD_BUG_ON(sizeof(struct ionic_intr) != 32); 41 RTE_BUILD_BUG_ON(sizeof(struct ionic_intr_status) != 8); 42 43 RTE_BUILD_BUG_ON(sizeof(union ionic_dev_regs) != 4096); 44 RTE_BUILD_BUG_ON(sizeof(union ionic_dev_info_regs) != 2048); 45 RTE_BUILD_BUG_ON(sizeof(union ionic_dev_cmd_regs) != 2048); 46 47 RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_stats) != 1024); 48 49 RTE_BUILD_BUG_ON(sizeof(struct ionic_admin_cmd) != 64); 50 RTE_BUILD_BUG_ON(sizeof(struct ionic_admin_comp) != 16); 51 RTE_BUILD_BUG_ON(sizeof(struct ionic_nop_cmd) != 64); 52 RTE_BUILD_BUG_ON(sizeof(struct ionic_nop_comp) != 16); 53 54 /* Device commands */ 55 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_identify_cmd) != 64); 56 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_identify_comp) != 16); 57 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_init_cmd) != 64); 58 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_init_comp) != 16); 59 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_reset_cmd) != 64); 60 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_reset_comp) != 16); 61 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_getattr_cmd) != 64); 62 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_getattr_comp) != 16); 63 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_setattr_cmd) != 64); 64 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_setattr_comp) != 16); 65 66 /* Port commands */ 67 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_identify_cmd) != 64); 68 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_identify_comp) != 16); 69 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_init_cmd) != 64); 70 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_init_comp) != 16); 71 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_reset_cmd) != 64); 72 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_reset_comp) != 16); 73 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_getattr_cmd) != 64); 74 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_getattr_comp) != 16); 75 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_setattr_cmd) != 64); 76 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_setattr_comp) != 16); 77 78 /* LIF commands */ 79 RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_init_cmd) != 64); 80 RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_init_comp) != 16); 81 RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_reset_cmd) != 64); 82 RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_getattr_cmd) != 64); 83 RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_getattr_comp) != 16); 84 RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_setattr_cmd) != 64); 85 RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_setattr_comp) != 16); 86 87 RTE_BUILD_BUG_ON(sizeof(struct ionic_q_init_cmd) != 64); 88 RTE_BUILD_BUG_ON(sizeof(struct ionic_q_init_comp) != 16); 89 RTE_BUILD_BUG_ON(sizeof(struct ionic_q_control_cmd) != 64); 90 91 RTE_BUILD_BUG_ON(sizeof(struct ionic_rx_mode_set_cmd) != 64); 92 RTE_BUILD_BUG_ON(sizeof(struct ionic_rx_filter_add_cmd) != 64); 93 RTE_BUILD_BUG_ON(sizeof(struct ionic_rx_filter_add_comp) != 16); 94 95 /* RDMA commands */ 96 RTE_BUILD_BUG_ON(sizeof(struct ionic_rdma_reset_cmd) != 64); 97 RTE_BUILD_BUG_ON(sizeof(struct ionic_rdma_queue_cmd) != 64); 98 99 /* Events */ 100 RTE_BUILD_BUG_ON(sizeof(struct ionic_notifyq_cmd) != 4); 101 RTE_BUILD_BUG_ON(sizeof(union ionic_notifyq_comp) != 64); 102 RTE_BUILD_BUG_ON(sizeof(struct ionic_notifyq_event) != 64); 103 RTE_BUILD_BUG_ON(sizeof(struct ionic_link_change_event) != 64); 104 RTE_BUILD_BUG_ON(sizeof(struct ionic_reset_event) != 64); 105 RTE_BUILD_BUG_ON(sizeof(struct ionic_heartbeat_event) != 64); 106 RTE_BUILD_BUG_ON(sizeof(struct ionic_log_event) != 64); 107 108 /* I/O */ 109 RTE_BUILD_BUG_ON(sizeof(struct ionic_txq_desc) != 16); 110 RTE_BUILD_BUG_ON(sizeof(struct ionic_txq_sg_desc_v1) != 256); 111 RTE_BUILD_BUG_ON(sizeof(struct ionic_txq_comp) != 16); 112 113 RTE_BUILD_BUG_ON(sizeof(struct ionic_rxq_desc) != 16); 114 RTE_BUILD_BUG_ON(sizeof(struct ionic_rxq_sg_desc) != 128); 115 RTE_BUILD_BUG_ON(sizeof(struct ionic_rxq_comp) != 16); 116 } 117 118 struct ionic_dev { 119 union ionic_dev_info_regs __iomem *dev_info; 120 union ionic_dev_cmd_regs __iomem *dev_cmd; 121 122 struct ionic_doorbell __iomem *db_pages; 123 struct ionic_intr __iomem *intr_ctrl; 124 struct ionic_intr_status __iomem *intr_status; 125 126 struct ionic_port_info *port_info; 127 const struct rte_memzone *port_info_z; 128 rte_iova_t port_info_pa; 129 uint32_t port_info_sz; 130 }; 131 132 #define Q_NEXT_TO_POST(_q, _n) (((_q)->head_idx + (_n)) & ((_q)->size_mask)) 133 #define Q_NEXT_TO_SRVC(_q, _n) (((_q)->tail_idx + (_n)) & ((_q)->size_mask)) 134 135 #define IONIC_INFO_IDX(_q, _i) (_i) 136 #define IONIC_INFO_PTR(_q, _i) (&(_q)->info[IONIC_INFO_IDX((_q), _i)]) 137 138 struct ionic_queue { 139 uint16_t num_descs; 140 uint16_t head_idx; 141 uint16_t tail_idx; 142 uint16_t size_mask; 143 uint8_t type; 144 uint8_t hw_type; 145 void *base; 146 void *sg_base; 147 struct ionic_doorbell __iomem *db; 148 void **info; 149 150 uint32_t index; 151 uint32_t hw_index; 152 rte_iova_t base_pa; 153 rte_iova_t sg_base_pa; 154 }; 155 156 #define IONIC_INTR_NONE (-1) 157 158 struct ionic_intr_info { 159 int index; 160 uint32_t vector; 161 struct ionic_intr __iomem *ctrl; 162 }; 163 164 struct ionic_cq { 165 uint16_t tail_idx; 166 uint16_t num_descs; 167 uint16_t size_mask; 168 bool done_color; 169 void *base; 170 rte_iova_t base_pa; 171 }; 172 173 struct ionic_lif; 174 struct ionic_adapter; 175 struct ionic_qcq; 176 struct rte_mempool; 177 struct rte_eth_dev; 178 179 struct ionic_dev_intf { 180 int (*setup)(struct ionic_adapter *adapter); 181 void (*copy_bus_info)(struct ionic_adapter *adapter, 182 struct rte_eth_dev *eth_dev); 183 int (*configure_intr)(struct ionic_adapter *adapter); 184 void (*unconfigure_intr)(struct ionic_adapter *adapter); 185 void (*unmap_bars)(struct ionic_adapter *adapter); 186 }; 187 188 void ionic_intr_init(struct ionic_dev *idev, struct ionic_intr_info *intr, 189 unsigned long index); 190 191 const char *ionic_opcode_to_str(enum ionic_cmd_opcode opcode); 192 193 void ionic_dev_cmd_go(struct ionic_dev *idev, union ionic_dev_cmd *cmd); 194 uint8_t ionic_dev_cmd_status(struct ionic_dev *idev); 195 bool ionic_dev_cmd_done(struct ionic_dev *idev); 196 void ionic_dev_cmd_comp(struct ionic_dev *idev, void *mem); 197 198 void ionic_dev_cmd_identify(struct ionic_dev *idev, uint8_t ver); 199 void ionic_dev_cmd_init(struct ionic_dev *idev); 200 void ionic_dev_cmd_reset(struct ionic_dev *idev); 201 202 void ionic_dev_cmd_port_identify(struct ionic_dev *idev); 203 void ionic_dev_cmd_port_init(struct ionic_dev *idev); 204 void ionic_dev_cmd_port_reset(struct ionic_dev *idev); 205 void ionic_dev_cmd_port_state(struct ionic_dev *idev, uint8_t state); 206 void ionic_dev_cmd_port_speed(struct ionic_dev *idev, uint32_t speed); 207 void ionic_dev_cmd_port_mtu(struct ionic_dev *idev, uint32_t mtu); 208 void ionic_dev_cmd_port_autoneg(struct ionic_dev *idev, uint8_t an_enable); 209 void ionic_dev_cmd_port_fec(struct ionic_dev *idev, uint8_t fec_type); 210 void ionic_dev_cmd_port_pause(struct ionic_dev *idev, uint8_t pause_type); 211 void ionic_dev_cmd_port_loopback(struct ionic_dev *idev, 212 uint8_t loopback_mode); 213 214 void ionic_dev_cmd_queue_identify(struct ionic_dev *idev, 215 uint16_t lif_type, uint8_t qtype, uint8_t qver); 216 217 void ionic_dev_cmd_lif_identify(struct ionic_dev *idev, uint8_t type, 218 uint8_t ver); 219 void ionic_dev_cmd_lif_init(struct ionic_dev *idev, rte_iova_t addr); 220 void ionic_dev_cmd_lif_reset(struct ionic_dev *idev); 221 222 void ionic_dev_cmd_adminq_init(struct ionic_dev *idev, struct ionic_qcq *qcq); 223 224 struct ionic_doorbell __iomem *ionic_db_map(struct ionic_lif *lif, 225 struct ionic_queue *q); 226 227 int ionic_cq_init(struct ionic_cq *cq, uint16_t num_descs); 228 void ionic_cq_map(struct ionic_cq *cq, void *base, rte_iova_t base_pa); 229 typedef bool (*ionic_cq_cb)(struct ionic_cq *cq, uint16_t cq_desc_index, 230 void *cb_arg); 231 uint32_t ionic_cq_service(struct ionic_cq *cq, uint32_t work_to_do, 232 ionic_cq_cb cb, void *cb_arg); 233 234 int ionic_q_init(struct ionic_queue *q, uint32_t index, uint16_t num_descs); 235 void ionic_q_map(struct ionic_queue *q, void *base, rte_iova_t base_pa); 236 void ionic_q_sg_map(struct ionic_queue *q, void *base, rte_iova_t base_pa); 237 238 static inline uint16_t 239 ionic_q_space_avail(struct ionic_queue *q) 240 { 241 uint16_t avail = q->tail_idx; 242 243 if (q->head_idx >= avail) 244 avail += q->num_descs - q->head_idx - 1; 245 else 246 avail -= q->head_idx + 1; 247 248 return avail; 249 } 250 251 static inline void 252 ionic_q_flush(struct ionic_queue *q) 253 { 254 uint64_t val = IONIC_DBELL_QID(q->hw_index) | q->head_idx; 255 256 rte_write64(rte_cpu_to_le_64(val), q->db); 257 } 258 259 #endif /* _IONIC_DEV_H_ */ 260