1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018-2022 Advanced Micro Devices, Inc. 3 */ 4 5 #ifndef _IONIC_DEV_H_ 6 #define _IONIC_DEV_H_ 7 8 #include <stdbool.h> 9 10 #include "ionic_osdep.h" 11 #include "ionic_if.h" 12 #include "ionic_regs.h" 13 14 #define VLAN_TAG_SIZE 4 15 16 #define IONIC_MIN_MTU RTE_ETHER_MIN_MTU 17 #define IONIC_MAX_MTU 9378 18 #define IONIC_ETH_OVERHEAD (RTE_ETHER_HDR_LEN + VLAN_TAG_SIZE) 19 20 #define IONIC_MAX_RING_DESC 32768 21 #define IONIC_MIN_RING_DESC 16 22 #define IONIC_DEF_TXRX_DESC 4096 23 #define IONIC_DEF_TXRX_BURST 32 24 25 #define IONIC_DEVCMD_TIMEOUT 5 /* devcmd_timeout */ 26 #define IONIC_DEVCMD_CHECK_PERIOD_US 10 /* devcmd status chk period */ 27 28 #define IONIC_ALIGN 4096 29 30 struct ionic_adapter; 31 32 struct ionic_dev_bar { 33 void __iomem *vaddr; 34 rte_iova_t bus_addr; 35 unsigned long len; 36 }; 37 38 static inline void ionic_struct_size_checks(void) 39 { 40 RTE_BUILD_BUG_ON(sizeof(struct ionic_doorbell) != 8); 41 RTE_BUILD_BUG_ON(sizeof(struct ionic_intr) != 32); 42 RTE_BUILD_BUG_ON(sizeof(struct ionic_intr_status) != 8); 43 44 RTE_BUILD_BUG_ON(sizeof(union ionic_dev_regs) != 4096); 45 RTE_BUILD_BUG_ON(sizeof(union ionic_dev_info_regs) != 2048); 46 RTE_BUILD_BUG_ON(sizeof(union ionic_dev_cmd_regs) != 2048); 47 48 RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_stats) != 1024); 49 50 RTE_BUILD_BUG_ON(sizeof(struct ionic_admin_cmd) != 64); 51 RTE_BUILD_BUG_ON(sizeof(struct ionic_admin_comp) != 16); 52 RTE_BUILD_BUG_ON(sizeof(struct ionic_nop_cmd) != 64); 53 RTE_BUILD_BUG_ON(sizeof(struct ionic_nop_comp) != 16); 54 55 /* Device commands */ 56 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_identify_cmd) != 64); 57 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_identify_comp) != 16); 58 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_init_cmd) != 64); 59 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_init_comp) != 16); 60 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_reset_cmd) != 64); 61 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_reset_comp) != 16); 62 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_getattr_cmd) != 64); 63 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_getattr_comp) != 16); 64 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_setattr_cmd) != 64); 65 RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_setattr_comp) != 16); 66 67 /* Port commands */ 68 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_identify_cmd) != 64); 69 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_identify_comp) != 16); 70 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_init_cmd) != 64); 71 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_init_comp) != 16); 72 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_reset_cmd) != 64); 73 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_reset_comp) != 16); 74 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_getattr_cmd) != 64); 75 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_getattr_comp) != 16); 76 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_setattr_cmd) != 64); 77 RTE_BUILD_BUG_ON(sizeof(struct ionic_port_setattr_comp) != 16); 78 79 /* LIF commands */ 80 RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_init_cmd) != 64); 81 RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_init_comp) != 16); 82 RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_reset_cmd) != 64); 83 RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_getattr_cmd) != 64); 84 RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_getattr_comp) != 16); 85 RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_setattr_cmd) != 64); 86 RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_setattr_comp) != 16); 87 88 RTE_BUILD_BUG_ON(sizeof(struct ionic_q_init_cmd) != 64); 89 RTE_BUILD_BUG_ON(sizeof(struct ionic_q_init_comp) != 16); 90 RTE_BUILD_BUG_ON(sizeof(struct ionic_q_control_cmd) != 64); 91 92 RTE_BUILD_BUG_ON(sizeof(struct ionic_rx_mode_set_cmd) != 64); 93 RTE_BUILD_BUG_ON(sizeof(struct ionic_rx_filter_add_cmd) != 64); 94 RTE_BUILD_BUG_ON(sizeof(struct ionic_rx_filter_add_comp) != 16); 95 96 /* RDMA commands */ 97 RTE_BUILD_BUG_ON(sizeof(struct ionic_rdma_reset_cmd) != 64); 98 RTE_BUILD_BUG_ON(sizeof(struct ionic_rdma_queue_cmd) != 64); 99 100 /* Events */ 101 RTE_BUILD_BUG_ON(sizeof(struct ionic_notifyq_cmd) != 4); 102 RTE_BUILD_BUG_ON(sizeof(union ionic_notifyq_comp) != 64); 103 RTE_BUILD_BUG_ON(sizeof(struct ionic_notifyq_event) != 64); 104 RTE_BUILD_BUG_ON(sizeof(struct ionic_link_change_event) != 64); 105 RTE_BUILD_BUG_ON(sizeof(struct ionic_reset_event) != 64); 106 RTE_BUILD_BUG_ON(sizeof(struct ionic_heartbeat_event) != 64); 107 RTE_BUILD_BUG_ON(sizeof(struct ionic_log_event) != 64); 108 109 /* I/O */ 110 RTE_BUILD_BUG_ON(sizeof(struct ionic_txq_desc) != 16); 111 RTE_BUILD_BUG_ON(sizeof(struct ionic_txq_sg_desc_v1) != 256); 112 RTE_BUILD_BUG_ON(sizeof(struct ionic_txq_comp) != 16); 113 114 RTE_BUILD_BUG_ON(sizeof(struct ionic_rxq_desc) != 16); 115 RTE_BUILD_BUG_ON(sizeof(struct ionic_rxq_sg_desc) != 128); 116 RTE_BUILD_BUG_ON(sizeof(struct ionic_rxq_comp) != 16); 117 } 118 119 struct ionic_dev { 120 union ionic_dev_info_regs __iomem *dev_info; 121 union ionic_dev_cmd_regs __iomem *dev_cmd; 122 123 struct ionic_doorbell __iomem *db_pages; 124 struct ionic_intr __iomem *intr_ctrl; 125 struct ionic_intr_status __iomem *intr_status; 126 127 struct ionic_port_info *port_info; 128 const struct rte_memzone *port_info_z; 129 rte_iova_t port_info_pa; 130 uint32_t port_info_sz; 131 }; 132 133 #define Q_NEXT_TO_POST(_q, _n) (((_q)->head_idx + (_n)) & ((_q)->size_mask)) 134 #define Q_NEXT_TO_SRVC(_q, _n) (((_q)->tail_idx + (_n)) & ((_q)->size_mask)) 135 136 #define IONIC_INFO_IDX(_q, _i) ((_i) * (_q)->num_segs) 137 #define IONIC_INFO_PTR(_q, _i) (&(_q)->info[IONIC_INFO_IDX((_q), _i)]) 138 139 struct ionic_queue { 140 uint16_t num_descs; 141 uint16_t num_segs; 142 uint16_t head_idx; 143 uint16_t tail_idx; 144 uint16_t size_mask; 145 uint8_t type; 146 uint8_t hw_type; 147 void *base; 148 void *sg_base; 149 struct ionic_doorbell __iomem *db; 150 void **info; 151 152 uint32_t index; 153 uint32_t hw_index; 154 rte_iova_t base_pa; 155 rte_iova_t sg_base_pa; 156 }; 157 158 #define IONIC_INTR_NONE (-1) 159 160 struct ionic_intr_info { 161 int index; 162 uint32_t vector; 163 struct ionic_intr __iomem *ctrl; 164 }; 165 166 struct ionic_cq { 167 uint16_t tail_idx; 168 uint16_t num_descs; 169 uint16_t size_mask; 170 bool done_color; 171 void *base; 172 rte_iova_t base_pa; 173 }; 174 175 struct ionic_lif; 176 struct ionic_adapter; 177 struct ionic_qcq; 178 struct rte_mempool; 179 struct rte_eth_dev; 180 struct rte_devargs; 181 182 struct ionic_dev_intf { 183 int (*setup)(struct ionic_adapter *adapter); 184 int (*devargs)(struct ionic_adapter *adapter, 185 struct rte_devargs *devargs); 186 void (*copy_bus_info)(struct ionic_adapter *adapter, 187 struct rte_eth_dev *eth_dev); 188 int (*configure_intr)(struct ionic_adapter *adapter); 189 void (*unconfigure_intr)(struct ionic_adapter *adapter); 190 void (*unmap_bars)(struct ionic_adapter *adapter); 191 }; 192 193 void ionic_intr_init(struct ionic_dev *idev, struct ionic_intr_info *intr, 194 unsigned long index); 195 196 const char *ionic_opcode_to_str(enum ionic_cmd_opcode opcode); 197 198 void ionic_dev_cmd_go(struct ionic_dev *idev, union ionic_dev_cmd *cmd); 199 uint8_t ionic_dev_cmd_status(struct ionic_dev *idev); 200 bool ionic_dev_cmd_done(struct ionic_dev *idev); 201 void ionic_dev_cmd_comp(struct ionic_dev *idev, void *mem); 202 203 void ionic_dev_cmd_identify(struct ionic_dev *idev, uint8_t ver); 204 void ionic_dev_cmd_init(struct ionic_dev *idev); 205 void ionic_dev_cmd_reset(struct ionic_dev *idev); 206 207 void ionic_dev_cmd_port_identify(struct ionic_dev *idev); 208 void ionic_dev_cmd_port_init(struct ionic_dev *idev); 209 void ionic_dev_cmd_port_reset(struct ionic_dev *idev); 210 void ionic_dev_cmd_port_state(struct ionic_dev *idev, uint8_t state); 211 void ionic_dev_cmd_port_speed(struct ionic_dev *idev, uint32_t speed); 212 void ionic_dev_cmd_port_mtu(struct ionic_dev *idev, uint32_t mtu); 213 void ionic_dev_cmd_port_autoneg(struct ionic_dev *idev, uint8_t an_enable); 214 void ionic_dev_cmd_port_fec(struct ionic_dev *idev, uint8_t fec_type); 215 void ionic_dev_cmd_port_pause(struct ionic_dev *idev, uint8_t pause_type); 216 void ionic_dev_cmd_port_loopback(struct ionic_dev *idev, 217 uint8_t loopback_mode); 218 219 void ionic_dev_cmd_queue_identify(struct ionic_dev *idev, 220 uint16_t lif_type, uint8_t qtype, uint8_t qver); 221 222 void ionic_dev_cmd_lif_identify(struct ionic_dev *idev, uint8_t type, 223 uint8_t ver); 224 void ionic_dev_cmd_lif_init(struct ionic_dev *idev, rte_iova_t addr); 225 void ionic_dev_cmd_lif_reset(struct ionic_dev *idev); 226 227 void ionic_dev_cmd_adminq_init(struct ionic_dev *idev, struct ionic_qcq *qcq); 228 229 struct ionic_doorbell __iomem *ionic_db_map(struct ionic_lif *lif, 230 struct ionic_queue *q); 231 232 int ionic_cq_init(struct ionic_cq *cq, uint16_t num_descs); 233 void ionic_cq_reset(struct ionic_cq *cq); 234 void ionic_cq_map(struct ionic_cq *cq, void *base, rte_iova_t base_pa); 235 typedef bool (*ionic_cq_cb)(struct ionic_cq *cq, uint16_t cq_desc_index, 236 void *cb_arg); 237 uint32_t ionic_cq_service(struct ionic_cq *cq, uint32_t work_to_do, 238 ionic_cq_cb cb, void *cb_arg); 239 240 int ionic_q_init(struct ionic_queue *q, uint32_t index, uint16_t num_descs); 241 void ionic_q_reset(struct ionic_queue *q); 242 void ionic_q_map(struct ionic_queue *q, void *base, rte_iova_t base_pa); 243 void ionic_q_sg_map(struct ionic_queue *q, void *base, rte_iova_t base_pa); 244 245 static inline uint16_t 246 ionic_q_space_avail(struct ionic_queue *q) 247 { 248 uint16_t avail = q->tail_idx; 249 250 if (q->head_idx >= avail) 251 avail += q->num_descs - q->head_idx - 1; 252 else 253 avail -= q->head_idx + 1; 254 255 return avail; 256 } 257 258 static inline void 259 ionic_q_flush(struct ionic_queue *q) 260 { 261 uint64_t val = IONIC_DBELL_QID(q->hw_index) | q->head_idx; 262 263 rte_write64(rte_cpu_to_le_64(val), q->db); 264 } 265 266 #endif /* _IONIC_DEV_H_ */ 267