15ef51809SAlfredo Cardigliano /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) 25ef51809SAlfredo Cardigliano * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved. 35ef51809SAlfredo Cardigliano */ 45ef51809SAlfredo Cardigliano 55ef51809SAlfredo Cardigliano #ifndef _IONIC_DEV_H_ 65ef51809SAlfredo Cardigliano #define _IONIC_DEV_H_ 75ef51809SAlfredo Cardigliano 85ef51809SAlfredo Cardigliano #include "ionic_osdep.h" 95ef51809SAlfredo Cardigliano #include "ionic_if.h" 105ef51809SAlfredo Cardigliano #include "ionic_regs.h" 115ef51809SAlfredo Cardigliano 125ef51809SAlfredo Cardigliano #define IONIC_DEVCMD_TIMEOUT 30 /* devcmd_timeout */ 13*23bf4ddbSAlfredo Cardigliano #define IONIC_ALIGN 4096 145ef51809SAlfredo Cardigliano 155ef51809SAlfredo Cardigliano struct ionic_adapter; 165ef51809SAlfredo Cardigliano 175ef51809SAlfredo Cardigliano struct ionic_dev_bar { 185ef51809SAlfredo Cardigliano void __iomem *vaddr; 195ef51809SAlfredo Cardigliano rte_iova_t bus_addr; 205ef51809SAlfredo Cardigliano unsigned long len; 215ef51809SAlfredo Cardigliano }; 225ef51809SAlfredo Cardigliano 235ef51809SAlfredo Cardigliano static inline void ionic_struct_size_checks(void) 245ef51809SAlfredo Cardigliano { 255ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_doorbell) != 8); 265ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_intr) != 32); 275ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_intr_status) != 8); 285ef51809SAlfredo Cardigliano 295ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(union ionic_dev_regs) != 4096); 305ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(union ionic_dev_info_regs) != 2048); 315ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(union ionic_dev_cmd_regs) != 2048); 325ef51809SAlfredo Cardigliano 335ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_stats) != 1024); 345ef51809SAlfredo Cardigliano 355ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_admin_cmd) != 64); 365ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_admin_comp) != 16); 375ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_nop_cmd) != 64); 385ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_nop_comp) != 16); 395ef51809SAlfredo Cardigliano 405ef51809SAlfredo Cardigliano /* Device commands */ 415ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_identify_cmd) != 64); 425ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_identify_comp) != 16); 435ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_init_cmd) != 64); 445ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_init_comp) != 16); 455ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_reset_cmd) != 64); 465ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_reset_comp) != 16); 475ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_getattr_cmd) != 64); 485ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_getattr_comp) != 16); 495ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_setattr_cmd) != 64); 505ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_dev_setattr_comp) != 16); 515ef51809SAlfredo Cardigliano 525ef51809SAlfredo Cardigliano /* Port commands */ 535ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_port_identify_cmd) != 64); 545ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_port_identify_comp) != 16); 555ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_port_init_cmd) != 64); 565ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_port_init_comp) != 16); 575ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_port_reset_cmd) != 64); 585ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_port_reset_comp) != 16); 595ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_port_getattr_cmd) != 64); 605ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_port_getattr_comp) != 16); 615ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_port_setattr_cmd) != 64); 625ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_port_setattr_comp) != 16); 635ef51809SAlfredo Cardigliano 645ef51809SAlfredo Cardigliano /* LIF commands */ 655ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_init_cmd) != 64); 665ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_init_comp) != 16); 675ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_reset_cmd) != 64); 685ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_getattr_cmd) != 64); 695ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_getattr_comp) != 16); 705ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_setattr_cmd) != 64); 715ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_lif_setattr_comp) != 16); 725ef51809SAlfredo Cardigliano 735ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_q_init_cmd) != 64); 745ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_q_init_comp) != 16); 755ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_q_control_cmd) != 64); 765ef51809SAlfredo Cardigliano 775ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_rx_mode_set_cmd) != 64); 785ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_rx_filter_add_cmd) != 64); 795ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_rx_filter_add_comp) != 16); 805ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_rx_filter_del_cmd) != 64); 815ef51809SAlfredo Cardigliano 825ef51809SAlfredo Cardigliano /* RDMA commands */ 835ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_rdma_reset_cmd) != 64); 845ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_rdma_queue_cmd) != 64); 855ef51809SAlfredo Cardigliano 865ef51809SAlfredo Cardigliano /* Events */ 875ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_notifyq_cmd) != 4); 885ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(union ionic_notifyq_comp) != 64); 895ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_notifyq_event) != 64); 905ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_link_change_event) != 64); 915ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_reset_event) != 64); 925ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_heartbeat_event) != 64); 935ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_log_event) != 64); 945ef51809SAlfredo Cardigliano 955ef51809SAlfredo Cardigliano /* I/O */ 965ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_txq_desc) != 16); 975ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_txq_sg_desc) != 128); 985ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_txq_comp) != 16); 995ef51809SAlfredo Cardigliano 1005ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_rxq_desc) != 16); 1015ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_rxq_sg_desc) != 128); 1025ef51809SAlfredo Cardigliano RTE_BUILD_BUG_ON(sizeof(struct ionic_rxq_comp) != 16); 1035ef51809SAlfredo Cardigliano } 1045ef51809SAlfredo Cardigliano 1055ef51809SAlfredo Cardigliano struct ionic_dev { 1065ef51809SAlfredo Cardigliano union ionic_dev_info_regs __iomem *dev_info; 1075ef51809SAlfredo Cardigliano union ionic_dev_cmd_regs __iomem *dev_cmd; 1085ef51809SAlfredo Cardigliano 1095ef51809SAlfredo Cardigliano struct ionic_doorbell __iomem *db_pages; 1105ef51809SAlfredo Cardigliano rte_iova_t phy_db_pages; 1115ef51809SAlfredo Cardigliano 1125ef51809SAlfredo Cardigliano struct ionic_intr __iomem *intr_ctrl; 1135ef51809SAlfredo Cardigliano 1145ef51809SAlfredo Cardigliano struct ionic_intr_status __iomem *intr_status; 115*23bf4ddbSAlfredo Cardigliano 116*23bf4ddbSAlfredo Cardigliano struct ionic_port_info *port_info; 117*23bf4ddbSAlfredo Cardigliano const struct rte_memzone *port_info_z; 118*23bf4ddbSAlfredo Cardigliano rte_iova_t port_info_pa; 119*23bf4ddbSAlfredo Cardigliano uint32_t port_info_sz; 1205ef51809SAlfredo Cardigliano }; 1215ef51809SAlfredo Cardigliano 1225ef51809SAlfredo Cardigliano int ionic_dev_setup(struct ionic_adapter *adapter); 1235ef51809SAlfredo Cardigliano 1245ef51809SAlfredo Cardigliano void ionic_dev_cmd_go(struct ionic_dev *idev, union ionic_dev_cmd *cmd); 1255ef51809SAlfredo Cardigliano uint8_t ionic_dev_cmd_status(struct ionic_dev *idev); 1265ef51809SAlfredo Cardigliano bool ionic_dev_cmd_done(struct ionic_dev *idev); 1275ef51809SAlfredo Cardigliano void ionic_dev_cmd_comp(struct ionic_dev *idev, void *mem); 1285ef51809SAlfredo Cardigliano 1295ef51809SAlfredo Cardigliano void ionic_dev_cmd_identify(struct ionic_dev *idev, uint8_t ver); 1305ef51809SAlfredo Cardigliano void ionic_dev_cmd_init(struct ionic_dev *idev); 1315ef51809SAlfredo Cardigliano void ionic_dev_cmd_reset(struct ionic_dev *idev); 1325ef51809SAlfredo Cardigliano 133*23bf4ddbSAlfredo Cardigliano void ionic_dev_cmd_port_identify(struct ionic_dev *idev); 134*23bf4ddbSAlfredo Cardigliano void ionic_dev_cmd_port_init(struct ionic_dev *idev); 135*23bf4ddbSAlfredo Cardigliano void ionic_dev_cmd_port_reset(struct ionic_dev *idev); 136*23bf4ddbSAlfredo Cardigliano void ionic_dev_cmd_port_state(struct ionic_dev *idev, uint8_t state); 137*23bf4ddbSAlfredo Cardigliano void ionic_dev_cmd_port_speed(struct ionic_dev *idev, uint32_t speed); 138*23bf4ddbSAlfredo Cardigliano void ionic_dev_cmd_port_mtu(struct ionic_dev *idev, uint32_t mtu); 139*23bf4ddbSAlfredo Cardigliano void ionic_dev_cmd_port_autoneg(struct ionic_dev *idev, uint8_t an_enable); 140*23bf4ddbSAlfredo Cardigliano void ionic_dev_cmd_port_fec(struct ionic_dev *idev, uint8_t fec_type); 141*23bf4ddbSAlfredo Cardigliano void ionic_dev_cmd_port_pause(struct ionic_dev *idev, uint8_t pause_type); 142*23bf4ddbSAlfredo Cardigliano void ionic_dev_cmd_port_loopback(struct ionic_dev *idev, 143*23bf4ddbSAlfredo Cardigliano uint8_t loopback_mode); 144*23bf4ddbSAlfredo Cardigliano 1455ef51809SAlfredo Cardigliano #endif /* _IONIC_DEV_H_ */ 146