xref: /dpdk/drivers/net/ionic/ionic_dev.c (revision 6f04fa45211e3ca4fb9a7e9ceabc682fa47e88bf) 
1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
2  * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved.
3  */
4 
5 #include <stdbool.h>
6 
7 #include <rte_malloc.h>
8 
9 #include "ionic_dev.h"
10 #include "ionic_lif.h"
11 #include "ionic.h"
12 
13 int
14 ionic_dev_setup(struct ionic_adapter *adapter)
15 {
16 	struct ionic_dev_bar *bar = adapter->bars;
17 	unsigned int num_bars = adapter->num_bars;
18 	struct ionic_dev *idev = &adapter->idev;
19 	uint32_t sig;
20 	u_char *bar0_base;
21 	unsigned int i;
22 
23 	/* BAR0: dev_cmd and interrupts */
24 	if (num_bars < 1) {
25 		IONIC_PRINT(ERR, "No bars found, aborting");
26 		return -EFAULT;
27 	}
28 
29 	if (bar->len < IONIC_BAR0_SIZE) {
30 		IONIC_PRINT(ERR,
31 			"Resource bar size %lu too small, aborting",
32 			bar->len);
33 		return -EFAULT;
34 	}
35 
36 	bar0_base = bar->vaddr;
37 	idev->dev_info = (union ionic_dev_info_regs *)
38 		&bar0_base[IONIC_BAR0_DEV_INFO_REGS_OFFSET];
39 	idev->dev_cmd = (union ionic_dev_cmd_regs *)
40 		&bar0_base[IONIC_BAR0_DEV_CMD_REGS_OFFSET];
41 	idev->intr_status = (struct ionic_intr_status *)
42 		&bar0_base[IONIC_BAR0_INTR_STATUS_OFFSET];
43 	idev->intr_ctrl = (struct ionic_intr *)
44 		&bar0_base[IONIC_BAR0_INTR_CTRL_OFFSET];
45 
46 	sig = ioread32(&idev->dev_info->signature);
47 	if (sig != IONIC_DEV_INFO_SIGNATURE) {
48 		IONIC_PRINT(ERR, "Incompatible firmware signature %" PRIx32 "",
49 			sig);
50 		return -EFAULT;
51 	}
52 
53 	for (i = 0; i < IONIC_DEVINFO_FWVERS_BUFLEN; i++)
54 		adapter->fw_version[i] =
55 			ioread8(&idev->dev_info->fw_version[i]);
56 	adapter->fw_version[IONIC_DEVINFO_FWVERS_BUFLEN - 1] = '\0';
57 
58 	IONIC_PRINT(DEBUG, "Firmware version: %s", adapter->fw_version);
59 
60 	/* BAR1: doorbells */
61 	bar++;
62 	if (num_bars < 2) {
63 		IONIC_PRINT(ERR, "Doorbell bar missing, aborting");
64 		return -EFAULT;
65 	}
66 
67 	idev->db_pages = bar->vaddr;
68 
69 	return 0;
70 }
71 
72 /* Devcmd Interface */
73 
74 uint8_t
75 ionic_dev_cmd_status(struct ionic_dev *idev)
76 {
77 	return ioread8(&idev->dev_cmd->comp.comp.status);
78 }
79 
80 bool
81 ionic_dev_cmd_done(struct ionic_dev *idev)
82 {
83 	return ioread32(&idev->dev_cmd->done) & IONIC_DEV_CMD_DONE;
84 }
85 
86 void
87 ionic_dev_cmd_comp(struct ionic_dev *idev, void *mem)
88 {
89 	union ionic_dev_cmd_comp *comp = mem;
90 	uint32_t comp_size = RTE_DIM(comp->words);
91 	uint32_t i;
92 
93 	for (i = 0; i < comp_size; i++)
94 		comp->words[i] = ioread32(&idev->dev_cmd->comp.words[i]);
95 }
96 
97 void
98 ionic_dev_cmd_go(struct ionic_dev *idev, union ionic_dev_cmd *cmd)
99 {
100 	uint32_t cmd_size = RTE_DIM(cmd->words);
101 	uint32_t i;
102 
103 	IONIC_PRINT(DEBUG, "Sending %s (%d) via dev_cmd",
104 		    ionic_opcode_to_str(cmd->cmd.opcode), cmd->cmd.opcode);
105 
106 	for (i = 0; i < cmd_size; i++)
107 		iowrite32(cmd->words[i], &idev->dev_cmd->cmd.words[i]);
108 
109 	iowrite32(0, &idev->dev_cmd->done);
110 	iowrite32(1, &idev->dev_cmd->doorbell);
111 }
112 
113 /* Device commands */
114 
115 void
116 ionic_dev_cmd_identify(struct ionic_dev *idev, uint8_t ver)
117 {
118 	union ionic_dev_cmd cmd = {
119 		.identify.opcode = IONIC_CMD_IDENTIFY,
120 		.identify.ver = ver,
121 	};
122 
123 	ionic_dev_cmd_go(idev, &cmd);
124 }
125 
126 void
127 ionic_dev_cmd_init(struct ionic_dev *idev)
128 {
129 	union ionic_dev_cmd cmd = {
130 		.init.opcode = IONIC_CMD_INIT,
131 		.init.type = 0,
132 	};
133 
134 	ionic_dev_cmd_go(idev, &cmd);
135 }
136 
137 void
138 ionic_dev_cmd_reset(struct ionic_dev *idev)
139 {
140 	union ionic_dev_cmd cmd = {
141 		.reset.opcode = IONIC_CMD_RESET,
142 	};
143 
144 	ionic_dev_cmd_go(idev, &cmd);
145 }
146 
147 /* Port commands */
148 
149 void
150 ionic_dev_cmd_port_identify(struct ionic_dev *idev)
151 {
152 	union ionic_dev_cmd cmd = {
153 		.port_init.opcode = IONIC_CMD_PORT_IDENTIFY,
154 		.port_init.index = 0,
155 	};
156 
157 	ionic_dev_cmd_go(idev, &cmd);
158 }
159 
160 void
161 ionic_dev_cmd_port_init(struct ionic_dev *idev)
162 {
163 	union ionic_dev_cmd cmd = {
164 		.port_init.opcode = IONIC_CMD_PORT_INIT,
165 		.port_init.index = 0,
166 		.port_init.info_pa = rte_cpu_to_le_64(idev->port_info_pa),
167 	};
168 
169 	ionic_dev_cmd_go(idev, &cmd);
170 }
171 
172 void
173 ionic_dev_cmd_port_reset(struct ionic_dev *idev)
174 {
175 	union ionic_dev_cmd cmd = {
176 		.port_reset.opcode = IONIC_CMD_PORT_RESET,
177 		.port_reset.index = 0,
178 	};
179 
180 	ionic_dev_cmd_go(idev, &cmd);
181 }
182 
183 void
184 ionic_dev_cmd_port_state(struct ionic_dev *idev, uint8_t state)
185 {
186 	union ionic_dev_cmd cmd = {
187 		.port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
188 		.port_setattr.index = 0,
189 		.port_setattr.attr = IONIC_PORT_ATTR_STATE,
190 		.port_setattr.state = state,
191 	};
192 
193 	ionic_dev_cmd_go(idev, &cmd);
194 }
195 
196 void
197 ionic_dev_cmd_port_speed(struct ionic_dev *idev, uint32_t speed)
198 {
199 	union ionic_dev_cmd cmd = {
200 		.port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
201 		.port_setattr.index = 0,
202 		.port_setattr.attr = IONIC_PORT_ATTR_SPEED,
203 		.port_setattr.speed = rte_cpu_to_le_32(speed),
204 	};
205 
206 	ionic_dev_cmd_go(idev, &cmd);
207 }
208 
209 void
210 ionic_dev_cmd_port_mtu(struct ionic_dev *idev, uint32_t mtu)
211 {
212 	union ionic_dev_cmd cmd = {
213 		.port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
214 		.port_setattr.index = 0,
215 		.port_setattr.attr = IONIC_PORT_ATTR_MTU,
216 		.port_setattr.mtu = rte_cpu_to_le_32(mtu),
217 	};
218 
219 	ionic_dev_cmd_go(idev, &cmd);
220 }
221 
222 void
223 ionic_dev_cmd_port_autoneg(struct ionic_dev *idev, uint8_t an_enable)
224 {
225 	union ionic_dev_cmd cmd = {
226 		.port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
227 		.port_setattr.index = 0,
228 		.port_setattr.attr = IONIC_PORT_ATTR_AUTONEG,
229 		.port_setattr.an_enable = an_enable,
230 	};
231 
232 	ionic_dev_cmd_go(idev, &cmd);
233 }
234 
235 void
236 ionic_dev_cmd_port_fec(struct ionic_dev *idev, uint8_t fec_type)
237 {
238 	union ionic_dev_cmd cmd = {
239 		.port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
240 		.port_setattr.index = 0,
241 		.port_setattr.attr = IONIC_PORT_ATTR_FEC,
242 		.port_setattr.fec_type = fec_type,
243 	};
244 
245 	ionic_dev_cmd_go(idev, &cmd);
246 }
247 
248 void
249 ionic_dev_cmd_port_pause(struct ionic_dev *idev, uint8_t pause_type)
250 {
251 	union ionic_dev_cmd cmd = {
252 		.port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
253 		.port_setattr.index = 0,
254 		.port_setattr.attr = IONIC_PORT_ATTR_PAUSE,
255 		.port_setattr.pause_type = pause_type,
256 	};
257 
258 	ionic_dev_cmd_go(idev, &cmd);
259 }
260 
261 void
262 ionic_dev_cmd_port_loopback(struct ionic_dev *idev, uint8_t loopback_mode)
263 {
264 	union ionic_dev_cmd cmd = {
265 		.port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
266 		.port_setattr.index = 0,
267 		.port_setattr.attr = IONIC_PORT_ATTR_LOOPBACK,
268 		.port_setattr.loopback_mode = loopback_mode,
269 	};
270 
271 	ionic_dev_cmd_go(idev, &cmd);
272 }
273 
274 /* LIF commands */
275 
276 void
277 ionic_dev_cmd_queue_identify(struct ionic_dev *idev,
278 		uint16_t lif_type, uint8_t qtype, uint8_t qver)
279 {
280 	union ionic_dev_cmd cmd = {
281 		.q_identify.opcode = IONIC_CMD_Q_IDENTIFY,
282 		.q_identify.lif_type = rte_cpu_to_le_16(lif_type),
283 		.q_identify.type = qtype,
284 		.q_identify.ver = qver,
285 	};
286 
287 	ionic_dev_cmd_go(idev, &cmd);
288 }
289 
290 void
291 ionic_dev_cmd_lif_identify(struct ionic_dev *idev, uint8_t type, uint8_t ver)
292 {
293 	union ionic_dev_cmd cmd = {
294 		.lif_identify.opcode = IONIC_CMD_LIF_IDENTIFY,
295 		.lif_identify.type = type,
296 		.lif_identify.ver = ver,
297 	};
298 
299 	ionic_dev_cmd_go(idev, &cmd);
300 }
301 
302 void
303 ionic_dev_cmd_lif_init(struct ionic_dev *idev, rte_iova_t info_pa)
304 {
305 	union ionic_dev_cmd cmd = {
306 		.lif_init.opcode = IONIC_CMD_LIF_INIT,
307 		.lif_init.info_pa = rte_cpu_to_le_64(info_pa),
308 	};
309 
310 	ionic_dev_cmd_go(idev, &cmd);
311 }
312 
313 void
314 ionic_dev_cmd_lif_reset(struct ionic_dev *idev)
315 {
316 	union ionic_dev_cmd cmd = {
317 		.lif_init.opcode = IONIC_CMD_LIF_RESET,
318 	};
319 
320 	ionic_dev_cmd_go(idev, &cmd);
321 }
322 
323 struct ionic_doorbell *
324 ionic_db_map(struct ionic_lif *lif, struct ionic_queue *q)
325 {
326 	return lif->kern_dbpage + q->hw_type;
327 }
328 
329 void
330 ionic_intr_init(struct ionic_dev *idev, struct ionic_intr_info *intr,
331 		unsigned long index)
332 {
333 	ionic_intr_clean(idev->intr_ctrl, index);
334 	intr->index = index;
335 }
336 
337 void
338 ionic_dev_cmd_adminq_init(struct ionic_dev *idev, struct ionic_qcq *qcq)
339 {
340 	struct ionic_queue *q = &qcq->q;
341 	struct ionic_cq *cq = &qcq->cq;
342 
343 	union ionic_dev_cmd cmd = {
344 		.q_init.opcode = IONIC_CMD_Q_INIT,
345 		.q_init.type = q->type,
346 		.q_init.ver = qcq->lif->qtype_info[q->type].version,
347 		.q_init.index = rte_cpu_to_le_32(q->index),
348 		.q_init.flags = rte_cpu_to_le_16(IONIC_QINIT_F_ENA),
349 		.q_init.intr_index = rte_cpu_to_le_16(IONIC_INTR_NONE),
350 		.q_init.ring_size = rte_log2_u32(q->num_descs),
351 		.q_init.ring_base = rte_cpu_to_le_64(q->base_pa),
352 		.q_init.cq_ring_base = rte_cpu_to_le_64(cq->base_pa),
353 	};
354 
355 	IONIC_PRINT(DEBUG, "adminq.q_init.ver %u", cmd.q_init.ver);
356 
357 	ionic_dev_cmd_go(idev, &cmd);
358 }
359 
360 int
361 ionic_cq_init(struct ionic_lif *lif, struct ionic_cq *cq,
362 		uint32_t num_descs, size_t desc_size)
363 {
364 	if (desc_size == 0) {
365 		IONIC_PRINT(ERR, "Descriptor size is %zu", desc_size);
366 		return -EINVAL;
367 	}
368 
369 	if (!rte_is_power_of_2(num_descs) ||
370 	    num_descs < IONIC_MIN_RING_DESC ||
371 	    num_descs > IONIC_MAX_RING_DESC) {
372 		IONIC_PRINT(ERR, "%u descriptors (min: %u max: %u)",
373 			num_descs, IONIC_MIN_RING_DESC, IONIC_MAX_RING_DESC);
374 		return -EINVAL;
375 	}
376 
377 	cq->lif = lif;
378 	cq->num_descs = num_descs;
379 	cq->desc_size = desc_size;
380 	cq->tail_idx = 0;
381 	cq->done_color = 1;
382 
383 	return 0;
384 }
385 
386 void
387 ionic_cq_map(struct ionic_cq *cq, void *base, rte_iova_t base_pa)
388 {
389 	cq->base = base;
390 	cq->base_pa = base_pa;
391 }
392 
393 void
394 ionic_cq_bind(struct ionic_cq *cq, struct ionic_queue *q)
395 {
396 	cq->bound_q = q;
397 	q->bound_cq = cq;
398 }
399 
400 uint32_t
401 ionic_cq_service(struct ionic_cq *cq, uint32_t work_to_do,
402 		 ionic_cq_cb cb, void *cb_arg)
403 {
404 	uint32_t work_done = 0;
405 
406 	if (work_to_do == 0)
407 		return 0;
408 
409 	while (cb(cq, cq->tail_idx, cb_arg)) {
410 		cq->tail_idx = (cq->tail_idx + 1) & (cq->num_descs - 1);
411 		if (cq->tail_idx == 0)
412 			cq->done_color = !cq->done_color;
413 
414 		if (++work_done == work_to_do)
415 			break;
416 	}
417 
418 	return work_done;
419 }
420 
421 int
422 ionic_q_init(struct ionic_lif *lif, struct ionic_dev *idev,
423 	     struct ionic_queue *q, uint32_t index, uint32_t num_descs,
424 	     size_t desc_size, size_t sg_desc_size)
425 {
426 	uint32_t ring_size;
427 
428 	if (desc_size == 0 || !rte_is_power_of_2(num_descs))
429 		return -EINVAL;
430 
431 	ring_size = rte_log2_u32(num_descs);
432 
433 	if (ring_size < 2 || ring_size > 16)
434 		return -EINVAL;
435 
436 	q->lif = lif;
437 	q->idev = idev;
438 	q->index = index;
439 	q->num_descs = num_descs;
440 	q->desc_size = desc_size;
441 	q->sg_desc_size = sg_desc_size;
442 	q->head_idx = 0;
443 	q->tail_idx = 0;
444 
445 	return 0;
446 }
447 
448 void
449 ionic_q_map(struct ionic_queue *q, void *base, rte_iova_t base_pa)
450 {
451 	q->base = base;
452 	q->base_pa = base_pa;
453 }
454 
455 void
456 ionic_q_sg_map(struct ionic_queue *q, void *base, rte_iova_t base_pa)
457 {
458 	q->sg_base = base;
459 	q->sg_base_pa = base_pa;
460 }
461 
462 void
463 ionic_q_post(struct ionic_queue *q, bool ring_doorbell, desc_cb cb,
464 	     void *cb_arg)
465 {
466 	struct ionic_desc_info *head = &q->info[q->head_idx];
467 
468 	head->cb = cb;
469 	head->cb_arg = cb_arg;
470 
471 	q->head_idx = (q->head_idx + 1) & (q->num_descs - 1);
472 
473 	if (ring_doorbell)
474 		ionic_q_flush(q);
475 }
476 
477 void
478 ionic_q_service(struct ionic_queue *q, uint32_t cq_desc_index,
479 		uint32_t stop_index, void *service_cb_arg)
480 {
481 	struct ionic_desc_info *desc_info;
482 	uint32_t curr_q_tail_idx;
483 
484 	do {
485 		desc_info = &q->info[q->tail_idx];
486 
487 		if (desc_info->cb)
488 			desc_info->cb(q, q->tail_idx, cq_desc_index,
489 				desc_info->cb_arg, service_cb_arg);
490 
491 		desc_info->cb = NULL;
492 		desc_info->cb_arg = NULL;
493 
494 		curr_q_tail_idx = q->tail_idx;
495 		q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1);
496 
497 	} while (curr_q_tail_idx != stop_index);
498 }
499 
500 static void
501 ionic_adminq_cb(struct ionic_queue *q,
502 		uint32_t q_desc_index, uint32_t cq_desc_index,
503 		void *cb_arg, void *service_cb_arg __rte_unused)
504 {
505 	struct ionic_admin_ctx *ctx = cb_arg;
506 	struct ionic_admin_comp *cq_desc_base = q->bound_cq->base;
507 	struct ionic_admin_comp *cq_desc = &cq_desc_base[cq_desc_index];
508 	uint16_t comp_index;
509 
510 	if (!ctx)
511 		return;
512 
513 	comp_index = rte_le_to_cpu_16(cq_desc->comp_index);
514 	if (unlikely(comp_index != q_desc_index)) {
515 		IONIC_WARN_ON(comp_index != q_desc_index);
516 		return;
517 	}
518 
519 	memcpy(&ctx->comp, cq_desc, sizeof(*cq_desc));
520 
521 	ctx->pending_work = false; /* done */
522 }
523 
524 /** ionic_adminq_post - Post an admin command.
525  * @lif:		Handle to lif.
526  * @cmd_ctx:		Api admin command context.
527  *
528  * Post the command to an admin queue in the ethernet driver.  If this command
529  * succeeds, then the command has been posted, but that does not indicate a
530  * completion.  If this command returns success, then the completion callback
531  * will eventually be called.
532  *
533  * Return: zero or negative error status.
534  */
535 int
536 ionic_adminq_post(struct ionic_lif *lif, struct ionic_admin_ctx *ctx)
537 {
538 	struct ionic_queue *adminq = &lif->adminqcq->q;
539 	struct ionic_admin_cmd *q_desc_base = adminq->base;
540 	struct ionic_admin_cmd *q_desc;
541 	int err = 0;
542 
543 	rte_spinlock_lock(&lif->adminq_lock);
544 
545 	if (ionic_q_space_avail(adminq) < 1) {
546 		err = -ENOSPC;
547 		goto err_out;
548 	}
549 
550 	q_desc = &q_desc_base[adminq->head_idx];
551 
552 	memcpy(q_desc, &ctx->cmd, sizeof(ctx->cmd));
553 
554 	ionic_q_post(adminq, true, ionic_adminq_cb, ctx);
555 
556 err_out:
557 	rte_spinlock_unlock(&lif->adminq_lock);
558 
559 	return err;
560 }
561