xref: /dpdk/drivers/net/ionic/ionic_dev.c (revision 6c02043e9967a9d8f6e8c058256e257efe1d6d1a) 
1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
2  * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved.
3  */
4 
5 #include <stdbool.h>
6 
7 #include <rte_malloc.h>
8 
9 #include "ionic_dev.h"
10 #include "ionic_lif.h"
11 #include "ionic.h"
12 
13 int
14 ionic_dev_setup(struct ionic_adapter *adapter)
15 {
16 	struct ionic_dev_bar *bar = adapter->bars;
17 	unsigned int num_bars = adapter->num_bars;
18 	struct ionic_dev *idev = &adapter->idev;
19 	uint32_t sig;
20 	u_char *bar0_base;
21 	unsigned int i;
22 
23 	/* BAR0: dev_cmd and interrupts */
24 	if (num_bars < 1) {
25 		IONIC_PRINT(ERR, "No bars found, aborting");
26 		return -EFAULT;
27 	}
28 
29 	if (bar->len < IONIC_BAR0_SIZE) {
30 		IONIC_PRINT(ERR,
31 			"Resource bar size %lu too small, aborting",
32 			bar->len);
33 		return -EFAULT;
34 	}
35 
36 	bar0_base = bar->vaddr;
37 	idev->dev_info = (union ionic_dev_info_regs *)
38 		&bar0_base[IONIC_BAR0_DEV_INFO_REGS_OFFSET];
39 	idev->dev_cmd = (union ionic_dev_cmd_regs *)
40 		&bar0_base[IONIC_BAR0_DEV_CMD_REGS_OFFSET];
41 	idev->intr_status = (struct ionic_intr_status *)
42 		&bar0_base[IONIC_BAR0_INTR_STATUS_OFFSET];
43 	idev->intr_ctrl = (struct ionic_intr *)
44 		&bar0_base[IONIC_BAR0_INTR_CTRL_OFFSET];
45 
46 	sig = ioread32(&idev->dev_info->signature);
47 	if (sig != IONIC_DEV_INFO_SIGNATURE) {
48 		IONIC_PRINT(ERR, "Incompatible firmware signature %" PRIx32 "",
49 			sig);
50 		return -EFAULT;
51 	}
52 
53 	for (i = 0; i < IONIC_DEVINFO_FWVERS_BUFLEN; i++)
54 		adapter->fw_version[i] =
55 			ioread8(&idev->dev_info->fw_version[i]);
56 	adapter->fw_version[IONIC_DEVINFO_FWVERS_BUFLEN - 1] = '\0';
57 
58 	IONIC_PRINT(DEBUG, "Firmware version: %s", adapter->fw_version);
59 
60 	/* BAR1: doorbells */
61 	bar++;
62 	if (num_bars < 2) {
63 		IONIC_PRINT(ERR, "Doorbell bar missing, aborting");
64 		return -EFAULT;
65 	}
66 
67 	idev->db_pages = bar->vaddr;
68 
69 	return 0;
70 }
71 
72 /* Devcmd Interface */
73 
74 uint8_t
75 ionic_dev_cmd_status(struct ionic_dev *idev)
76 {
77 	return ioread8(&idev->dev_cmd->comp.comp.status);
78 }
79 
80 bool
81 ionic_dev_cmd_done(struct ionic_dev *idev)
82 {
83 	return ioread32(&idev->dev_cmd->done) & IONIC_DEV_CMD_DONE;
84 }
85 
86 void
87 ionic_dev_cmd_comp(struct ionic_dev *idev, void *mem)
88 {
89 	union ionic_dev_cmd_comp *comp = mem;
90 	unsigned int i;
91 	uint32_t comp_size = sizeof(comp->words) /
92 		sizeof(comp->words[0]);
93 
94 	for (i = 0; i < comp_size; i++)
95 		comp->words[i] = ioread32(&idev->dev_cmd->comp.words[i]);
96 }
97 
98 void
99 ionic_dev_cmd_go(struct ionic_dev *idev, union ionic_dev_cmd *cmd)
100 {
101 	unsigned int i;
102 	uint32_t cmd_size = sizeof(cmd->words) /
103 		sizeof(cmd->words[0]);
104 
105 	IONIC_PRINT(DEBUG, "Sending %s (%d) via dev_cmd",
106 		    ionic_opcode_to_str(cmd->cmd.opcode), cmd->cmd.opcode);
107 
108 	for (i = 0; i < cmd_size; i++)
109 		iowrite32(cmd->words[i], &idev->dev_cmd->cmd.words[i]);
110 
111 	iowrite32(0, &idev->dev_cmd->done);
112 	iowrite32(1, &idev->dev_cmd->doorbell);
113 }
114 
115 /* Device commands */
116 
117 void
118 ionic_dev_cmd_identify(struct ionic_dev *idev, uint8_t ver)
119 {
120 	union ionic_dev_cmd cmd = {
121 		.identify.opcode = IONIC_CMD_IDENTIFY,
122 		.identify.ver = ver,
123 	};
124 
125 	ionic_dev_cmd_go(idev, &cmd);
126 }
127 
128 void
129 ionic_dev_cmd_init(struct ionic_dev *idev)
130 {
131 	union ionic_dev_cmd cmd = {
132 		.init.opcode = IONIC_CMD_INIT,
133 		.init.type = 0,
134 	};
135 
136 	ionic_dev_cmd_go(idev, &cmd);
137 }
138 
139 void
140 ionic_dev_cmd_reset(struct ionic_dev *idev)
141 {
142 	union ionic_dev_cmd cmd = {
143 		.reset.opcode = IONIC_CMD_RESET,
144 	};
145 
146 	ionic_dev_cmd_go(idev, &cmd);
147 }
148 
149 /* Port commands */
150 
151 void
152 ionic_dev_cmd_port_identify(struct ionic_dev *idev)
153 {
154 	union ionic_dev_cmd cmd = {
155 		.port_init.opcode = IONIC_CMD_PORT_IDENTIFY,
156 		.port_init.index = 0,
157 	};
158 
159 	ionic_dev_cmd_go(idev, &cmd);
160 }
161 
162 void
163 ionic_dev_cmd_port_init(struct ionic_dev *idev)
164 {
165 	union ionic_dev_cmd cmd = {
166 		.port_init.opcode = IONIC_CMD_PORT_INIT,
167 		.port_init.index = 0,
168 		.port_init.info_pa = rte_cpu_to_le_64(idev->port_info_pa),
169 	};
170 
171 	ionic_dev_cmd_go(idev, &cmd);
172 }
173 
174 void
175 ionic_dev_cmd_port_reset(struct ionic_dev *idev)
176 {
177 	union ionic_dev_cmd cmd = {
178 		.port_reset.opcode = IONIC_CMD_PORT_RESET,
179 		.port_reset.index = 0,
180 	};
181 
182 	ionic_dev_cmd_go(idev, &cmd);
183 }
184 
185 void
186 ionic_dev_cmd_port_state(struct ionic_dev *idev, uint8_t state)
187 {
188 	union ionic_dev_cmd cmd = {
189 		.port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
190 		.port_setattr.index = 0,
191 		.port_setattr.attr = IONIC_PORT_ATTR_STATE,
192 		.port_setattr.state = state,
193 	};
194 
195 	ionic_dev_cmd_go(idev, &cmd);
196 }
197 
198 void
199 ionic_dev_cmd_port_speed(struct ionic_dev *idev, uint32_t speed)
200 {
201 	union ionic_dev_cmd cmd = {
202 		.port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
203 		.port_setattr.index = 0,
204 		.port_setattr.attr = IONIC_PORT_ATTR_SPEED,
205 		.port_setattr.speed = rte_cpu_to_le_32(speed),
206 	};
207 
208 	ionic_dev_cmd_go(idev, &cmd);
209 }
210 
211 void
212 ionic_dev_cmd_port_mtu(struct ionic_dev *idev, uint32_t mtu)
213 {
214 	union ionic_dev_cmd cmd = {
215 		.port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
216 		.port_setattr.index = 0,
217 		.port_setattr.attr = IONIC_PORT_ATTR_MTU,
218 		.port_setattr.mtu = rte_cpu_to_le_32(mtu),
219 	};
220 
221 	ionic_dev_cmd_go(idev, &cmd);
222 }
223 
224 void
225 ionic_dev_cmd_port_autoneg(struct ionic_dev *idev, uint8_t an_enable)
226 {
227 	union ionic_dev_cmd cmd = {
228 		.port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
229 		.port_setattr.index = 0,
230 		.port_setattr.attr = IONIC_PORT_ATTR_AUTONEG,
231 		.port_setattr.an_enable = an_enable,
232 	};
233 
234 	ionic_dev_cmd_go(idev, &cmd);
235 }
236 
237 void
238 ionic_dev_cmd_port_fec(struct ionic_dev *idev, uint8_t fec_type)
239 {
240 	union ionic_dev_cmd cmd = {
241 		.port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
242 		.port_setattr.index = 0,
243 		.port_setattr.attr = IONIC_PORT_ATTR_FEC,
244 		.port_setattr.fec_type = fec_type,
245 	};
246 
247 	ionic_dev_cmd_go(idev, &cmd);
248 }
249 
250 void
251 ionic_dev_cmd_port_pause(struct ionic_dev *idev, uint8_t pause_type)
252 {
253 	union ionic_dev_cmd cmd = {
254 		.port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
255 		.port_setattr.index = 0,
256 		.port_setattr.attr = IONIC_PORT_ATTR_PAUSE,
257 		.port_setattr.pause_type = pause_type,
258 	};
259 
260 	ionic_dev_cmd_go(idev, &cmd);
261 }
262 
263 void
264 ionic_dev_cmd_port_loopback(struct ionic_dev *idev, uint8_t loopback_mode)
265 {
266 	union ionic_dev_cmd cmd = {
267 		.port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
268 		.port_setattr.index = 0,
269 		.port_setattr.attr = IONIC_PORT_ATTR_LOOPBACK,
270 		.port_setattr.loopback_mode = loopback_mode,
271 	};
272 
273 	ionic_dev_cmd_go(idev, &cmd);
274 }
275 
276 /* LIF commands */
277 
278 void
279 ionic_dev_cmd_queue_identify(struct ionic_dev *idev,
280 		uint16_t lif_type, uint8_t qtype, uint8_t qver)
281 {
282 	union ionic_dev_cmd cmd = {
283 		.q_identify.opcode = IONIC_CMD_Q_IDENTIFY,
284 		.q_identify.lif_type = rte_cpu_to_le_16(lif_type),
285 		.q_identify.type = qtype,
286 		.q_identify.ver = qver,
287 	};
288 
289 	ionic_dev_cmd_go(idev, &cmd);
290 }
291 
292 void
293 ionic_dev_cmd_lif_identify(struct ionic_dev *idev, uint8_t type, uint8_t ver)
294 {
295 	union ionic_dev_cmd cmd = {
296 		.lif_identify.opcode = IONIC_CMD_LIF_IDENTIFY,
297 		.lif_identify.type = type,
298 		.lif_identify.ver = ver,
299 	};
300 
301 	ionic_dev_cmd_go(idev, &cmd);
302 }
303 
304 void
305 ionic_dev_cmd_lif_init(struct ionic_dev *idev, rte_iova_t info_pa)
306 {
307 	union ionic_dev_cmd cmd = {
308 		.lif_init.opcode = IONIC_CMD_LIF_INIT,
309 		.lif_init.info_pa = rte_cpu_to_le_64(info_pa),
310 	};
311 
312 	ionic_dev_cmd_go(idev, &cmd);
313 }
314 
315 void
316 ionic_dev_cmd_lif_reset(struct ionic_dev *idev)
317 {
318 	union ionic_dev_cmd cmd = {
319 		.lif_init.opcode = IONIC_CMD_LIF_RESET,
320 	};
321 
322 	ionic_dev_cmd_go(idev, &cmd);
323 }
324 
325 struct ionic_doorbell *
326 ionic_db_map(struct ionic_lif *lif, struct ionic_queue *q)
327 {
328 	return lif->kern_dbpage + q->hw_type;
329 }
330 
331 void
332 ionic_intr_init(struct ionic_dev *idev, struct ionic_intr_info *intr,
333 		unsigned long index)
334 {
335 	ionic_intr_clean(idev->intr_ctrl, index);
336 	intr->index = index;
337 }
338 
339 void
340 ionic_dev_cmd_adminq_init(struct ionic_dev *idev, struct ionic_qcq *qcq)
341 {
342 	struct ionic_queue *q = &qcq->q;
343 	struct ionic_cq *cq = &qcq->cq;
344 
345 	union ionic_dev_cmd cmd = {
346 		.q_init.opcode = IONIC_CMD_Q_INIT,
347 		.q_init.type = q->type,
348 		.q_init.ver = qcq->lif->qtype_info[q->type].version,
349 		.q_init.index = rte_cpu_to_le_32(q->index),
350 		.q_init.flags = rte_cpu_to_le_16(IONIC_QINIT_F_ENA),
351 		.q_init.intr_index = rte_cpu_to_le_16(IONIC_INTR_NONE),
352 		.q_init.ring_size = rte_log2_u32(q->num_descs),
353 		.q_init.ring_base = rte_cpu_to_le_64(q->base_pa),
354 		.q_init.cq_ring_base = rte_cpu_to_le_64(cq->base_pa),
355 	};
356 
357 	IONIC_PRINT(DEBUG, "adminq.q_init.ver %u", cmd.q_init.ver);
358 
359 	ionic_dev_cmd_go(idev, &cmd);
360 }
361 
362 int
363 ionic_cq_init(struct ionic_lif *lif, struct ionic_cq *cq,
364 		uint32_t num_descs, size_t desc_size)
365 {
366 	if (desc_size == 0) {
367 		IONIC_PRINT(ERR, "Descriptor size is %zu", desc_size);
368 		return -EINVAL;
369 	}
370 
371 	if (!rte_is_power_of_2(num_descs) ||
372 	    num_descs < IONIC_MIN_RING_DESC ||
373 	    num_descs > IONIC_MAX_RING_DESC) {
374 		IONIC_PRINT(ERR, "%u descriptors (min: %u max: %u)",
375 			num_descs, IONIC_MIN_RING_DESC, IONIC_MAX_RING_DESC);
376 		return -EINVAL;
377 	}
378 
379 	cq->lif = lif;
380 	cq->num_descs = num_descs;
381 	cq->desc_size = desc_size;
382 	cq->tail_idx = 0;
383 	cq->done_color = 1;
384 
385 	return 0;
386 }
387 
388 void
389 ionic_cq_map(struct ionic_cq *cq, void *base, rte_iova_t base_pa)
390 {
391 	cq->base = base;
392 	cq->base_pa = base_pa;
393 }
394 
395 void
396 ionic_cq_bind(struct ionic_cq *cq, struct ionic_queue *q)
397 {
398 	cq->bound_q = q;
399 	q->bound_cq = cq;
400 }
401 
402 uint32_t
403 ionic_cq_service(struct ionic_cq *cq, uint32_t work_to_do,
404 		 ionic_cq_cb cb, void *cb_arg)
405 {
406 	uint32_t work_done = 0;
407 
408 	if (work_to_do == 0)
409 		return 0;
410 
411 	while (cb(cq, cq->tail_idx, cb_arg)) {
412 		cq->tail_idx = (cq->tail_idx + 1) & (cq->num_descs - 1);
413 		if (cq->tail_idx == 0)
414 			cq->done_color = !cq->done_color;
415 
416 		if (++work_done == work_to_do)
417 			break;
418 	}
419 
420 	return work_done;
421 }
422 
423 int
424 ionic_q_init(struct ionic_lif *lif, struct ionic_dev *idev,
425 	     struct ionic_queue *q, uint32_t index, uint32_t num_descs,
426 	     size_t desc_size, size_t sg_desc_size)
427 {
428 	uint32_t ring_size;
429 
430 	if (desc_size == 0 || !rte_is_power_of_2(num_descs))
431 		return -EINVAL;
432 
433 	ring_size = rte_log2_u32(num_descs);
434 
435 	if (ring_size < 2 || ring_size > 16)
436 		return -EINVAL;
437 
438 	q->lif = lif;
439 	q->idev = idev;
440 	q->index = index;
441 	q->num_descs = num_descs;
442 	q->desc_size = desc_size;
443 	q->sg_desc_size = sg_desc_size;
444 	q->head_idx = 0;
445 	q->tail_idx = 0;
446 
447 	return 0;
448 }
449 
450 void
451 ionic_q_map(struct ionic_queue *q, void *base, rte_iova_t base_pa)
452 {
453 	q->base = base;
454 	q->base_pa = base_pa;
455 }
456 
457 void
458 ionic_q_sg_map(struct ionic_queue *q, void *base, rte_iova_t base_pa)
459 {
460 	q->sg_base = base;
461 	q->sg_base_pa = base_pa;
462 }
463 
464 void
465 ionic_q_post(struct ionic_queue *q, bool ring_doorbell, desc_cb cb,
466 	     void *cb_arg)
467 {
468 	struct ionic_desc_info *head = &q->info[q->head_idx];
469 
470 	head->cb = cb;
471 	head->cb_arg = cb_arg;
472 
473 	q->head_idx = (q->head_idx + 1) & (q->num_descs - 1);
474 
475 	if (ring_doorbell)
476 		ionic_q_flush(q);
477 }
478 
479 void
480 ionic_q_service(struct ionic_queue *q, uint32_t cq_desc_index,
481 		uint32_t stop_index, void *service_cb_arg)
482 {
483 	struct ionic_desc_info *desc_info;
484 	uint32_t curr_q_tail_idx;
485 
486 	do {
487 		desc_info = &q->info[q->tail_idx];
488 
489 		if (desc_info->cb)
490 			desc_info->cb(q, q->tail_idx, cq_desc_index,
491 				desc_info->cb_arg, service_cb_arg);
492 
493 		desc_info->cb = NULL;
494 		desc_info->cb_arg = NULL;
495 
496 		curr_q_tail_idx = q->tail_idx;
497 		q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1);
498 
499 	} while (curr_q_tail_idx != stop_index);
500 }
501 
502 static void
503 ionic_adminq_cb(struct ionic_queue *q,
504 		uint32_t q_desc_index, uint32_t cq_desc_index,
505 		void *cb_arg, void *service_cb_arg __rte_unused)
506 {
507 	struct ionic_admin_ctx *ctx = cb_arg;
508 	struct ionic_admin_comp *cq_desc_base = q->bound_cq->base;
509 	struct ionic_admin_comp *cq_desc = &cq_desc_base[cq_desc_index];
510 	uint16_t comp_index;
511 
512 	if (!ctx)
513 		return;
514 
515 	comp_index = rte_le_to_cpu_16(cq_desc->comp_index);
516 	if (unlikely(comp_index != q_desc_index)) {
517 		IONIC_WARN_ON(comp_index != q_desc_index);
518 		return;
519 	}
520 
521 	memcpy(&ctx->comp, cq_desc, sizeof(*cq_desc));
522 
523 	ctx->pending_work = false; /* done */
524 }
525 
526 /** ionic_adminq_post - Post an admin command.
527  * @lif:		Handle to lif.
528  * @cmd_ctx:		Api admin command context.
529  *
530  * Post the command to an admin queue in the ethernet driver.  If this command
531  * succeeds, then the command has been posted, but that does not indicate a
532  * completion.  If this command returns success, then the completion callback
533  * will eventually be called.
534  *
535  * Return: zero or negative error status.
536  */
537 int
538 ionic_adminq_post(struct ionic_lif *lif, struct ionic_admin_ctx *ctx)
539 {
540 	struct ionic_queue *adminq = &lif->adminqcq->q;
541 	struct ionic_admin_cmd *q_desc_base = adminq->base;
542 	struct ionic_admin_cmd *q_desc;
543 	int err = 0;
544 
545 	rte_spinlock_lock(&lif->adminq_lock);
546 
547 	if (ionic_q_space_avail(adminq) < 1) {
548 		err = -ENOSPC;
549 		goto err_out;
550 	}
551 
552 	q_desc = &q_desc_base[adminq->head_idx];
553 
554 	memcpy(q_desc, &ctx->cmd, sizeof(ctx->cmd));
555 
556 	ionic_q_post(adminq, true, ionic_adminq_cb, ctx);
557 
558 err_out:
559 	rte_spinlock_unlock(&lif->adminq_lock);
560 
561 	return err;
562 }
563