1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018-2019 Hisilicon Limited. 3 */ 4 5 #ifndef _HNS3_MBX_H_ 6 #define _HNS3_MBX_H_ 7 8 #define HNS3_MBX_VF_MSG_DATA_NUM 16 9 10 enum HNS3_MBX_OPCODE { 11 HNS3_MBX_RESET = 0x01, /* (VF -> PF) assert reset */ 12 HNS3_MBX_ASSERTING_RESET, /* (PF -> VF) PF is asserting reset */ 13 HNS3_MBX_SET_UNICAST, /* (VF -> PF) set UC addr */ 14 HNS3_MBX_SET_MULTICAST, /* (VF -> PF) set MC addr */ 15 HNS3_MBX_SET_VLAN, /* (VF -> PF) set VLAN */ 16 HNS3_MBX_MAP_RING_TO_VECTOR, /* (VF -> PF) map ring-to-vector */ 17 HNS3_MBX_UNMAP_RING_TO_VECTOR, /* (VF -> PF) unamp ring-to-vector */ 18 HNS3_MBX_SET_PROMISC_MODE, /* (VF -> PF) set promiscuous mode */ 19 HNS3_MBX_SET_MACVLAN, /* (VF -> PF) set unicast filter */ 20 HNS3_MBX_API_NEGOTIATE, /* (VF -> PF) negotiate API version */ 21 HNS3_MBX_GET_QINFO, /* (VF -> PF) get queue config */ 22 HNS3_MBX_GET_QDEPTH, /* (VF -> PF) get queue depth */ 23 HNS3_MBX_GET_TCINFO, /* (VF -> PF) get TC config */ 24 HNS3_MBX_GET_RETA, /* (VF -> PF) get RETA */ 25 HNS3_MBX_GET_RSS_KEY, /* (VF -> PF) get RSS key */ 26 HNS3_MBX_GET_MAC_ADDR, /* (VF -> PF) get MAC addr */ 27 HNS3_MBX_PF_VF_RESP, /* (PF -> VF) generate respone to VF */ 28 HNS3_MBX_GET_BDNUM, /* (VF -> PF) get BD num */ 29 HNS3_MBX_GET_BUFSIZE, /* (VF -> PF) get buffer size */ 30 HNS3_MBX_GET_STREAMID, /* (VF -> PF) get stream id */ 31 HNS3_MBX_SET_AESTART, /* (VF -> PF) start ae */ 32 HNS3_MBX_SET_TSOSTATS, /* (VF -> PF) get tso stats */ 33 HNS3_MBX_LINK_STAT_CHANGE, /* (PF -> VF) link status has changed */ 34 HNS3_MBX_GET_BASE_CONFIG, /* (VF -> PF) get config */ 35 HNS3_MBX_BIND_FUNC_QUEUE, /* (VF -> PF) bind function and queue */ 36 HNS3_MBX_GET_LINK_STATUS, /* (VF -> PF) get link status */ 37 HNS3_MBX_QUEUE_RESET, /* (VF -> PF) reset queue */ 38 HNS3_MBX_KEEP_ALIVE, /* (VF -> PF) send keep alive cmd */ 39 HNS3_MBX_SET_ALIVE, /* (VF -> PF) set alive state */ 40 HNS3_MBX_SET_MTU, /* (VF -> PF) set mtu */ 41 HNS3_MBX_GET_QID_IN_PF, /* (VF -> PF) get queue id in pf */ 42 43 HNS3_MBX_PUSH_VLAN_INFO = 34, /* (PF -> VF) push port base vlan */ 44 45 HNS3_MBX_PUSH_PROMISC_INFO = 36, /* (PF -> VF) push vf promisc info */ 46 47 HNS3_MBX_HANDLE_VF_TBL = 38, /* (VF -> PF) store/clear hw cfg tbl */ 48 HNS3_MBX_GET_RING_VECTOR_MAP, /* (VF -> PF) get ring-to-vector map */ 49 HNS3_MBX_PUSH_LINK_STATUS = 201, /* (IMP -> PF) get port link status */ 50 }; 51 52 /* below are per-VF mac-vlan subcodes */ 53 enum hns3_mbx_mac_vlan_subcode { 54 HNS3_MBX_MAC_VLAN_UC_MODIFY = 0, /* modify UC mac addr */ 55 HNS3_MBX_MAC_VLAN_UC_ADD, /* add a new UC mac addr */ 56 HNS3_MBX_MAC_VLAN_UC_REMOVE, /* remove a new UC mac addr */ 57 HNS3_MBX_MAC_VLAN_MC_MODIFY, /* modify MC mac addr */ 58 HNS3_MBX_MAC_VLAN_MC_ADD, /* add new MC mac addr */ 59 HNS3_MBX_MAC_VLAN_MC_REMOVE, /* remove MC mac addr */ 60 }; 61 62 /* below are per-VF vlan cfg subcodes */ 63 enum hns3_mbx_vlan_cfg_subcode { 64 HNS3_MBX_VLAN_FILTER = 0, /* set vlan filter */ 65 HNS3_MBX_VLAN_TX_OFF_CFG, /* set tx side vlan offload */ 66 HNS3_MBX_VLAN_RX_OFF_CFG, /* set rx side vlan offload */ 67 HNS3_MBX_GET_PORT_BASE_VLAN_STATE = 4, /* get port based vlan state */ 68 }; 69 70 enum hns3_mbx_tbl_cfg_subcode { 71 HNS3_MBX_VPORT_LIST_CLEAR = 0, 72 }; 73 74 enum hns3_mbx_link_fail_subcode { 75 HNS3_MBX_LF_NORMAL = 0, 76 HNS3_MBX_LF_REF_CLOCK_LOST, 77 HNS3_MBX_LF_XSFP_TX_DISABLE, 78 HNS3_MBX_LF_XSFP_ABSENT, 79 }; 80 81 #define HNS3_MBX_MAX_MSG_SIZE 16 82 #define HNS3_MBX_MAX_RESP_DATA_SIZE 8 83 #define HNS3_MBX_RING_MAP_BASIC_MSG_NUM 3 84 #define HNS3_MBX_RING_NODE_VARIABLE_NUM 3 85 86 struct hns3_mbx_resp_status { 87 rte_spinlock_t lock; /* protects against contending sync cmd resp */ 88 uint32_t req_msg_data; 89 uint32_t head; 90 uint32_t tail; 91 uint32_t lost; 92 int resp_status; 93 uint8_t additional_info[HNS3_MBX_MAX_RESP_DATA_SIZE]; 94 }; 95 96 struct errno_respcode_map { 97 uint16_t resp_code; 98 int err_no; 99 }; 100 101 #define HNS3_MBX_NEED_RESP_BIT BIT(0) 102 103 struct hns3_mbx_vf_to_pf_cmd { 104 uint8_t rsv; 105 uint8_t mbx_src_vfid; /* Auto filled by IMP */ 106 uint8_t mbx_need_resp; 107 uint8_t rsv1; 108 uint8_t msg_len; 109 uint8_t rsv2[3]; 110 uint8_t msg[HNS3_MBX_MAX_MSG_SIZE]; 111 }; 112 113 struct hns3_mbx_pf_to_vf_cmd { 114 uint8_t dest_vfid; 115 uint8_t rsv[3]; 116 uint8_t msg_len; 117 uint8_t rsv1[3]; 118 uint16_t msg[8]; 119 }; 120 121 struct hns3_ring_chain_param { 122 uint8_t ring_type; 123 uint8_t tqp_index; 124 uint8_t int_gl_index; 125 }; 126 127 #define HNS3_MBX_MAX_RING_CHAIN_PARAM_NUM 4 128 struct hns3_vf_bind_vector_msg { 129 uint8_t vector_id; 130 uint8_t ring_num; 131 struct hns3_ring_chain_param param[HNS3_MBX_MAX_RING_CHAIN_PARAM_NUM]; 132 }; 133 134 struct hns3_vf_rst_cmd { 135 uint8_t dest_vfid; 136 uint8_t vf_rst; 137 uint8_t rsv[22]; 138 }; 139 140 struct hns3_pf_rst_done_cmd { 141 uint8_t pf_rst_done; 142 uint8_t rsv[23]; 143 }; 144 145 #define HNS3_PF_RESET_DONE_BIT BIT(0) 146 147 /* used by VF to store the received Async responses from PF */ 148 struct hns3_mbx_arq_ring { 149 #define HNS3_MBX_MAX_ARQ_MSG_SIZE 8 150 #define HNS3_MBX_MAX_ARQ_MSG_NUM 1024 151 uint32_t head; 152 uint32_t tail; 153 uint32_t count; 154 uint16_t msg_q[HNS3_MBX_MAX_ARQ_MSG_NUM][HNS3_MBX_MAX_ARQ_MSG_SIZE]; 155 }; 156 157 #define hns3_mbx_ring_ptr_move_crq(crq) \ 158 ((crq)->next_to_use = ((crq)->next_to_use + 1) % (crq)->desc_num) 159 #define hns3_mbx_tail_ptr_move_arq(arq) \ 160 ((arq).tail = ((arq).tail + 1) % HNS3_MBX_MAX_ARQ_MSG_SIZE) 161 #define hns3_mbx_head_ptr_move_arq(arq) \ 162 ((arq).head = ((arq).head + 1) % HNS3_MBX_MAX_ARQ_MSG_SIZE) 163 164 struct hns3_hw; 165 void hns3_dev_handle_mbx_msg(struct hns3_hw *hw); 166 int hns3_send_mbx_msg(struct hns3_hw *hw, uint16_t code, uint16_t subcode, 167 const uint8_t *msg_data, uint8_t msg_len, bool need_resp, 168 uint8_t *resp_data, uint16_t resp_len); 169 #endif /* _HNS3_MBX_H_ */ 170