1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018-2019 Hisilicon Limited. 3 */ 4 5 #include <stdbool.h> 6 #include <rte_atomic.h> 7 #include <rte_alarm.h> 8 #include <rte_cycles.h> 9 #include <rte_ethdev.h> 10 #include <rte_io.h> 11 #include <rte_malloc.h> 12 #include <rte_pci.h> 13 #include <rte_bus_pci.h> 14 15 #include "hns3_ethdev.h" 16 #include "hns3_logs.h" 17 #include "hns3_intr.h" 18 #include "hns3_regs.h" 19 #include "hns3_rxtx.h" 20 21 #define SWITCH_CONTEXT_US 10 22 23 #define HNS3_CHECK_MERGE_CNT(val) \ 24 do { \ 25 if (val) \ 26 hw->reset.stats.merge_cnt++; \ 27 } while (0) 28 29 static const char *reset_string[HNS3_MAX_RESET] = { 30 "none", "vf_func", "vf_pf_func", "vf_full", "flr", 31 "vf_global", "pf_func", "global", "IMP", 32 }; 33 34 static const struct hns3_hw_error mac_afifo_tnl_int[] = { 35 { .int_msk = BIT(0), .msg = "egu_cge_afifo_ecc_1bit_err", 36 .reset_level = HNS3_NONE_RESET }, 37 { .int_msk = BIT(1), .msg = "egu_cge_afifo_ecc_mbit_err", 38 .reset_level = HNS3_GLOBAL_RESET }, 39 { .int_msk = BIT(2), .msg = "egu_lge_afifo_ecc_1bit_err", 40 .reset_level = HNS3_NONE_RESET }, 41 { .int_msk = BIT(3), .msg = "egu_lge_afifo_ecc_mbit_err", 42 .reset_level = HNS3_GLOBAL_RESET }, 43 { .int_msk = BIT(4), .msg = "cge_igu_afifo_ecc_1bit_err", 44 .reset_level = HNS3_NONE_RESET }, 45 { .int_msk = BIT(5), .msg = "cge_igu_afifo_ecc_mbit_err", 46 .reset_level = HNS3_GLOBAL_RESET }, 47 { .int_msk = BIT(6), .msg = "lge_igu_afifo_ecc_1bit_err", 48 .reset_level = HNS3_NONE_RESET }, 49 { .int_msk = BIT(7), .msg = "lge_igu_afifo_ecc_mbit_err", 50 .reset_level = HNS3_GLOBAL_RESET }, 51 { .int_msk = BIT(8), .msg = "cge_igu_afifo_overflow_err", 52 .reset_level = HNS3_GLOBAL_RESET }, 53 { .int_msk = BIT(9), .msg = "lge_igu_afifo_overflow_err", 54 .reset_level = HNS3_GLOBAL_RESET }, 55 { .int_msk = BIT(10), .msg = "egu_cge_afifo_underrun_err", 56 .reset_level = HNS3_GLOBAL_RESET }, 57 { .int_msk = BIT(11), .msg = "egu_lge_afifo_underrun_err", 58 .reset_level = HNS3_GLOBAL_RESET }, 59 { .int_msk = BIT(12), .msg = "egu_ge_afifo_underrun_err", 60 .reset_level = HNS3_GLOBAL_RESET }, 61 { .int_msk = BIT(13), .msg = "ge_igu_afifo_overflow_err", 62 .reset_level = HNS3_GLOBAL_RESET }, 63 { .int_msk = 0, .msg = NULL, 64 .reset_level = HNS3_NONE_RESET} 65 }; 66 67 static const struct hns3_hw_error ppu_mpf_abnormal_int_st1[] = { 68 { .int_msk = 0xFFFFFFFF, .msg = "rpu_rx_pkt_ecc_mbit_err", 69 .reset_level = HNS3_GLOBAL_RESET }, 70 { .int_msk = 0, .msg = NULL, 71 .reset_level = HNS3_NONE_RESET} 72 }; 73 74 static const struct hns3_hw_error ppu_mpf_abnormal_int_st2_ras[] = { 75 { .int_msk = BIT(13), .msg = "rpu_rx_pkt_bit32_ecc_mbit_err", 76 .reset_level = HNS3_GLOBAL_RESET }, 77 { .int_msk = BIT(14), .msg = "rpu_rx_pkt_bit33_ecc_mbit_err", 78 .reset_level = HNS3_GLOBAL_RESET }, 79 { .int_msk = BIT(15), .msg = "rpu_rx_pkt_bit34_ecc_mbit_err", 80 .reset_level = HNS3_GLOBAL_RESET }, 81 { .int_msk = BIT(16), .msg = "rpu_rx_pkt_bit35_ecc_mbit_err", 82 .reset_level = HNS3_GLOBAL_RESET }, 83 { .int_msk = BIT(17), .msg = "rcb_tx_ring_ecc_mbit_err", 84 .reset_level = HNS3_GLOBAL_RESET }, 85 { .int_msk = BIT(18), .msg = "rcb_rx_ring_ecc_mbit_err", 86 .reset_level = HNS3_GLOBAL_RESET }, 87 { .int_msk = BIT(19), .msg = "rcb_tx_fbd_ecc_mbit_err", 88 .reset_level = HNS3_GLOBAL_RESET }, 89 { .int_msk = BIT(20), .msg = "rcb_rx_ebd_ecc_mbit_err", 90 .reset_level = HNS3_GLOBAL_RESET }, 91 { .int_msk = BIT(21), .msg = "rcb_tso_info_ecc_mbit_err", 92 .reset_level = HNS3_GLOBAL_RESET }, 93 { .int_msk = BIT(22), .msg = "rcb_tx_int_info_ecc_mbit_err", 94 .reset_level = HNS3_GLOBAL_RESET }, 95 { .int_msk = BIT(23), .msg = "rcb_rx_int_info_ecc_mbit_err", 96 .reset_level = HNS3_GLOBAL_RESET }, 97 { .int_msk = BIT(24), .msg = "tpu_tx_pkt_0_ecc_mbit_err", 98 .reset_level = HNS3_GLOBAL_RESET }, 99 { .int_msk = BIT(25), .msg = "tpu_tx_pkt_1_ecc_mbit_err", 100 .reset_level = HNS3_GLOBAL_RESET }, 101 { .int_msk = BIT(26), .msg = "rd_bus_err", 102 .reset_level = HNS3_GLOBAL_RESET }, 103 { .int_msk = BIT(27), .msg = "wr_bus_err", 104 .reset_level = HNS3_GLOBAL_RESET }, 105 { .int_msk = BIT(30), .msg = "ooo_ecc_err_detect", 106 .reset_level = HNS3_NONE_RESET }, 107 { .int_msk = BIT(31), .msg = "ooo_ecc_err_multpl", 108 .reset_level = HNS3_GLOBAL_RESET }, 109 { .int_msk = 0, .msg = NULL, 110 .reset_level = HNS3_NONE_RESET} 111 }; 112 113 static const struct hns3_hw_error ppu_mpf_abnormal_int_st2_msix[] = { 114 { .int_msk = BIT(29), .msg = "rx_q_search_miss", 115 .reset_level = HNS3_NONE_RESET }, 116 { .int_msk = 0, .msg = NULL, 117 .reset_level = HNS3_NONE_RESET} 118 }; 119 120 static const struct hns3_hw_error ssu_port_based_pf_int[] = { 121 { .int_msk = BIT(0), .msg = "roc_pkt_without_key_port", 122 .reset_level = HNS3_GLOBAL_RESET }, 123 { .int_msk = BIT(9), .msg = "low_water_line_err_port", 124 .reset_level = HNS3_NONE_RESET }, 125 { .int_msk = 0, .msg = NULL, 126 .reset_level = HNS3_NONE_RESET} 127 }; 128 129 static const struct hns3_hw_error ppp_pf_abnormal_int[] = { 130 { .int_msk = BIT(0), .msg = "tx_vlan_tag_err", 131 .reset_level = HNS3_NONE_RESET }, 132 { .int_msk = BIT(1), .msg = "rss_list_tc_unassigned_queue_err", 133 .reset_level = HNS3_NONE_RESET }, 134 { .int_msk = 0, .msg = NULL, 135 .reset_level = HNS3_NONE_RESET} 136 }; 137 138 static const struct hns3_hw_error ppu_pf_abnormal_int_ras[] = { 139 { .int_msk = BIT(3), .msg = "tx_rd_fbd_poison", 140 .reset_level = HNS3_FUNC_RESET }, 141 { .int_msk = BIT(4), .msg = "rx_rd_ebd_poison", 142 .reset_level = HNS3_FUNC_RESET }, 143 { .int_msk = 0, .msg = NULL, 144 .reset_level = HNS3_NONE_RESET} 145 }; 146 147 static const struct hns3_hw_error ppu_pf_abnormal_int_msix[] = { 148 { .int_msk = BIT(0), .msg = "over_8bd_no_fe", 149 .reset_level = HNS3_FUNC_RESET }, 150 { .int_msk = BIT(1), .msg = "tso_mss_cmp_min_err", 151 .reset_level = HNS3_NONE_RESET }, 152 { .int_msk = BIT(2), .msg = "tso_mss_cmp_max_err", 153 .reset_level = HNS3_NONE_RESET }, 154 { .int_msk = BIT(5), .msg = "buf_wait_timeout", 155 .reset_level = HNS3_NONE_RESET }, 156 { .int_msk = 0, .msg = NULL, 157 .reset_level = HNS3_NONE_RESET} 158 }; 159 160 static const struct hns3_hw_error imp_tcm_ecc_int[] = { 161 { .int_msk = BIT(1), .msg = "imp_itcm0_ecc_mbit_err", 162 .reset_level = HNS3_NONE_RESET }, 163 { .int_msk = BIT(3), .msg = "imp_itcm1_ecc_mbit_err", 164 .reset_level = HNS3_NONE_RESET }, 165 { .int_msk = BIT(5), .msg = "imp_itcm2_ecc_mbit_err", 166 .reset_level = HNS3_NONE_RESET }, 167 { .int_msk = BIT(7), .msg = "imp_itcm3_ecc_mbit_err", 168 .reset_level = HNS3_NONE_RESET }, 169 { .int_msk = BIT(9), .msg = "imp_dtcm0_mem0_ecc_mbit_err", 170 .reset_level = HNS3_NONE_RESET }, 171 { .int_msk = BIT(11), .msg = "imp_dtcm0_mem1_ecc_mbit_err", 172 .reset_level = HNS3_NONE_RESET }, 173 { .int_msk = BIT(13), .msg = "imp_dtcm1_mem0_ecc_mbit_err", 174 .reset_level = HNS3_NONE_RESET }, 175 { .int_msk = BIT(15), .msg = "imp_dtcm1_mem1_ecc_mbit_err", 176 .reset_level = HNS3_NONE_RESET }, 177 { .int_msk = BIT(17), .msg = "imp_itcm4_ecc_mbit_err", 178 .reset_level = HNS3_NONE_RESET }, 179 { .int_msk = 0, .msg = NULL, 180 .reset_level = HNS3_NONE_RESET} 181 }; 182 183 static const struct hns3_hw_error cmdq_mem_ecc_int[] = { 184 { .int_msk = BIT(1), .msg = "cmdq_nic_rx_depth_ecc_mbit_err", 185 .reset_level = HNS3_NONE_RESET }, 186 { .int_msk = BIT(3), .msg = "cmdq_nic_tx_depth_ecc_mbit_err", 187 .reset_level = HNS3_NONE_RESET }, 188 { .int_msk = BIT(5), .msg = "cmdq_nic_rx_tail_ecc_mbit_err", 189 .reset_level = HNS3_NONE_RESET }, 190 { .int_msk = BIT(7), .msg = "cmdq_nic_tx_tail_ecc_mbit_err", 191 .reset_level = HNS3_NONE_RESET }, 192 { .int_msk = BIT(9), .msg = "cmdq_nic_rx_head_ecc_mbit_err", 193 .reset_level = HNS3_NONE_RESET }, 194 { .int_msk = BIT(11), .msg = "cmdq_nic_tx_head_ecc_mbit_err", 195 .reset_level = HNS3_NONE_RESET }, 196 { .int_msk = BIT(13), .msg = "cmdq_nic_rx_addr_ecc_mbit_err", 197 .reset_level = HNS3_NONE_RESET }, 198 { .int_msk = BIT(15), .msg = "cmdq_nic_tx_addr_ecc_mbit_err", 199 .reset_level = HNS3_NONE_RESET }, 200 { .int_msk = 0, .msg = NULL, 201 .reset_level = HNS3_NONE_RESET} 202 }; 203 204 static const struct hns3_hw_error tqp_int_ecc_int[] = { 205 { .int_msk = BIT(6), .msg = "tqp_int_cfg_even_ecc_mbit_err", 206 .reset_level = HNS3_NONE_RESET }, 207 { .int_msk = BIT(7), .msg = "tqp_int_cfg_odd_ecc_mbit_err", 208 .reset_level = HNS3_NONE_RESET }, 209 { .int_msk = BIT(8), .msg = "tqp_int_ctrl_even_ecc_mbit_err", 210 .reset_level = HNS3_NONE_RESET }, 211 { .int_msk = BIT(9), .msg = "tqp_int_ctrl_odd_ecc_mbit_err", 212 .reset_level = HNS3_NONE_RESET }, 213 { .int_msk = BIT(10), .msg = "tx_que_scan_int_ecc_mbit_err", 214 .reset_level = HNS3_NONE_RESET }, 215 { .int_msk = BIT(11), .msg = "rx_que_scan_int_ecc_mbit_err", 216 .reset_level = HNS3_NONE_RESET }, 217 { .int_msk = 0, .msg = NULL, 218 .reset_level = HNS3_NONE_RESET} 219 }; 220 221 static const struct hns3_hw_error imp_rd_poison_int[] = { 222 { .int_msk = BIT(0), .msg = "imp_rd_poison_int", 223 .reset_level = HNS3_NONE_RESET }, 224 { .int_msk = 0, .msg = NULL, 225 .reset_level = HNS3_NONE_RESET} 226 }; 227 228 #define HNS3_SSU_MEM_ECC_ERR(x) \ 229 { .int_msk = BIT(x), .msg = "ssu_mem" #x "_ecc_mbit_err", \ 230 .reset_level = HNS3_GLOBAL_RESET } 231 232 static const struct hns3_hw_error ssu_ecc_multi_bit_int_0[] = { 233 HNS3_SSU_MEM_ECC_ERR(0), 234 HNS3_SSU_MEM_ECC_ERR(1), 235 HNS3_SSU_MEM_ECC_ERR(2), 236 HNS3_SSU_MEM_ECC_ERR(3), 237 HNS3_SSU_MEM_ECC_ERR(4), 238 HNS3_SSU_MEM_ECC_ERR(5), 239 HNS3_SSU_MEM_ECC_ERR(6), 240 HNS3_SSU_MEM_ECC_ERR(7), 241 HNS3_SSU_MEM_ECC_ERR(8), 242 HNS3_SSU_MEM_ECC_ERR(9), 243 HNS3_SSU_MEM_ECC_ERR(10), 244 HNS3_SSU_MEM_ECC_ERR(11), 245 HNS3_SSU_MEM_ECC_ERR(12), 246 HNS3_SSU_MEM_ECC_ERR(13), 247 HNS3_SSU_MEM_ECC_ERR(14), 248 HNS3_SSU_MEM_ECC_ERR(15), 249 HNS3_SSU_MEM_ECC_ERR(16), 250 HNS3_SSU_MEM_ECC_ERR(17), 251 HNS3_SSU_MEM_ECC_ERR(18), 252 HNS3_SSU_MEM_ECC_ERR(19), 253 HNS3_SSU_MEM_ECC_ERR(20), 254 HNS3_SSU_MEM_ECC_ERR(21), 255 HNS3_SSU_MEM_ECC_ERR(22), 256 HNS3_SSU_MEM_ECC_ERR(23), 257 HNS3_SSU_MEM_ECC_ERR(24), 258 HNS3_SSU_MEM_ECC_ERR(25), 259 HNS3_SSU_MEM_ECC_ERR(26), 260 HNS3_SSU_MEM_ECC_ERR(27), 261 HNS3_SSU_MEM_ECC_ERR(28), 262 HNS3_SSU_MEM_ECC_ERR(29), 263 HNS3_SSU_MEM_ECC_ERR(30), 264 HNS3_SSU_MEM_ECC_ERR(31), 265 { .int_msk = 0, .msg = NULL, 266 .reset_level = HNS3_NONE_RESET} 267 }; 268 269 static const struct hns3_hw_error ssu_ecc_multi_bit_int_1[] = { 270 { .int_msk = BIT(0), .msg = "ssu_mem32_ecc_mbit_err", 271 .reset_level = HNS3_GLOBAL_RESET }, 272 { .int_msk = 0, .msg = NULL, 273 .reset_level = HNS3_NONE_RESET} 274 }; 275 276 static const struct hns3_hw_error ssu_common_ecc_int[] = { 277 { .int_msk = BIT(0), .msg = "buf_sum_err", 278 .reset_level = HNS3_NONE_RESET }, 279 { .int_msk = BIT(1), .msg = "ppp_mb_num_err", 280 .reset_level = HNS3_NONE_RESET }, 281 { .int_msk = BIT(2), .msg = "ppp_mbid_err", 282 .reset_level = HNS3_GLOBAL_RESET }, 283 { .int_msk = BIT(3), .msg = "ppp_rlt_mac_err", 284 .reset_level = HNS3_GLOBAL_RESET }, 285 { .int_msk = BIT(4), .msg = "ppp_rlt_host_err", 286 .reset_level = HNS3_GLOBAL_RESET }, 287 { .int_msk = BIT(5), .msg = "cks_edit_position_err", 288 .reset_level = HNS3_GLOBAL_RESET }, 289 { .int_msk = BIT(6), .msg = "cks_edit_condition_err", 290 .reset_level = HNS3_GLOBAL_RESET }, 291 { .int_msk = BIT(7), .msg = "vlan_edit_condition_err", 292 .reset_level = HNS3_GLOBAL_RESET }, 293 { .int_msk = BIT(8), .msg = "vlan_num_ot_err", 294 .reset_level = HNS3_GLOBAL_RESET }, 295 { .int_msk = BIT(9), .msg = "vlan_num_in_err", 296 .reset_level = HNS3_GLOBAL_RESET }, 297 { .int_msk = 0, .msg = NULL, 298 .reset_level = HNS3_NONE_RESET} 299 }; 300 301 static const struct hns3_hw_error igu_int[] = { 302 { .int_msk = BIT(0), .msg = "igu_rx_buf0_ecc_mbit_err", 303 .reset_level = HNS3_GLOBAL_RESET }, 304 { .int_msk = BIT(2), .msg = "igu_rx_buf1_ecc_mbit_err", 305 .reset_level = HNS3_GLOBAL_RESET }, 306 { .int_msk = 0, .msg = NULL, 307 .reset_level = HNS3_NONE_RESET} 308 }; 309 310 static const struct hns3_hw_error msix_ecc_int[] = { 311 { .int_msk = BIT(1), .msg = "msix_nic_ecc_mbit_err", 312 .reset_level = HNS3_NONE_RESET }, 313 { .int_msk = 0, .msg = NULL, 314 .reset_level = HNS3_NONE_RESET} 315 }; 316 317 static const struct hns3_hw_error ppp_mpf_abnormal_int_st1[] = { 318 { .int_msk = BIT(0), .msg = "vf_vlan_ad_mem_ecc_mbit_err", 319 .reset_level = HNS3_GLOBAL_RESET }, 320 { .int_msk = BIT(1), .msg = "umv_mcast_group_mem_ecc_mbit_err", 321 .reset_level = HNS3_GLOBAL_RESET }, 322 { .int_msk = BIT(2), .msg = "umv_key_mem0_ecc_mbit_err", 323 .reset_level = HNS3_GLOBAL_RESET }, 324 { .int_msk = BIT(3), .msg = "umv_key_mem1_ecc_mbit_err", 325 .reset_level = HNS3_GLOBAL_RESET }, 326 { .int_msk = BIT(4), .msg = "umv_key_mem2_ecc_mbit_err", 327 .reset_level = HNS3_GLOBAL_RESET }, 328 { .int_msk = BIT(5), .msg = "umv_key_mem3_ecc_mbit_err", 329 .reset_level = HNS3_GLOBAL_RESET }, 330 { .int_msk = BIT(6), .msg = "umv_ad_mem_ecc_mbit_err", 331 .reset_level = HNS3_GLOBAL_RESET }, 332 { .int_msk = BIT(7), .msg = "rss_tc_mode_mem_ecc_mbit_err", 333 .reset_level = HNS3_GLOBAL_RESET }, 334 { .int_msk = BIT(8), .msg = "rss_idt_mem0_ecc_mbit_err", 335 .reset_level = HNS3_GLOBAL_RESET }, 336 { .int_msk = BIT(9), .msg = "rss_idt_mem1_ecc_mbit_err", 337 .reset_level = HNS3_GLOBAL_RESET }, 338 { .int_msk = BIT(10), .msg = "rss_idt_mem2_ecc_mbit_err", 339 .reset_level = HNS3_GLOBAL_RESET }, 340 { .int_msk = BIT(11), .msg = "rss_idt_mem3_ecc_mbit_err", 341 .reset_level = HNS3_GLOBAL_RESET }, 342 { .int_msk = BIT(12), .msg = "rss_idt_mem4_ecc_mbit_err", 343 .reset_level = HNS3_GLOBAL_RESET }, 344 { .int_msk = BIT(13), .msg = "rss_idt_mem5_ecc_mbit_err", 345 .reset_level = HNS3_GLOBAL_RESET }, 346 { .int_msk = BIT(14), .msg = "rss_idt_mem6_ecc_mbit_err", 347 .reset_level = HNS3_GLOBAL_RESET }, 348 { .int_msk = BIT(15), .msg = "rss_idt_mem7_ecc_mbit_err", 349 .reset_level = HNS3_GLOBAL_RESET }, 350 { .int_msk = BIT(16), .msg = "rss_idt_mem8_ecc_mbit_err", 351 .reset_level = HNS3_GLOBAL_RESET }, 352 { .int_msk = BIT(17), .msg = "rss_idt_mem9_ecc_mbit_err", 353 .reset_level = HNS3_GLOBAL_RESET }, 354 { .int_msk = BIT(18), .msg = "rss_idt_mem10_ecc_m1bit_err", 355 .reset_level = HNS3_GLOBAL_RESET }, 356 { .int_msk = BIT(19), .msg = "rss_idt_mem11_ecc_mbit_err", 357 .reset_level = HNS3_GLOBAL_RESET }, 358 { .int_msk = BIT(20), .msg = "rss_idt_mem12_ecc_mbit_err", 359 .reset_level = HNS3_GLOBAL_RESET }, 360 { .int_msk = BIT(21), .msg = "rss_idt_mem13_ecc_mbit_err", 361 .reset_level = HNS3_GLOBAL_RESET }, 362 { .int_msk = BIT(22), .msg = "rss_idt_mem14_ecc_mbit_err", 363 .reset_level = HNS3_GLOBAL_RESET }, 364 { .int_msk = BIT(23), .msg = "rss_idt_mem15_ecc_mbit_err", 365 .reset_level = HNS3_GLOBAL_RESET }, 366 { .int_msk = BIT(24), .msg = "port_vlan_mem_ecc_mbit_err", 367 .reset_level = HNS3_GLOBAL_RESET }, 368 { .int_msk = BIT(25), .msg = "mcast_linear_table_mem_ecc_mbit_err", 369 .reset_level = HNS3_GLOBAL_RESET }, 370 { .int_msk = BIT(26), .msg = "mcast_result_mem_ecc_mbit_err", 371 .reset_level = HNS3_GLOBAL_RESET }, 372 { .int_msk = BIT(27), .msg = "flow_director_ad_mem0_ecc_mbit_err", 373 .reset_level = HNS3_GLOBAL_RESET }, 374 { .int_msk = BIT(28), .msg = "flow_director_ad_mem1_ecc_mbit_err", 375 .reset_level = HNS3_GLOBAL_RESET }, 376 { .int_msk = BIT(29), .msg = "rx_vlan_tag_memory_ecc_mbit_err", 377 .reset_level = HNS3_GLOBAL_RESET }, 378 { .int_msk = BIT(30), .msg = "Tx_UP_mapping_config_mem_ecc_mbit_err", 379 .reset_level = HNS3_GLOBAL_RESET }, 380 { .int_msk = 0, .msg = NULL, 381 .reset_level = HNS3_NONE_RESET} 382 }; 383 384 static const struct hns3_hw_error ppp_mpf_abnormal_int_st3[] = { 385 { .int_msk = BIT(0), .msg = "hfs_fifo_mem_ecc_mbit_err", 386 .reset_level = HNS3_GLOBAL_RESET }, 387 { .int_msk = BIT(1), .msg = "rslt_descr_fifo_mem_ecc_mbit_err", 388 .reset_level = HNS3_GLOBAL_RESET }, 389 { .int_msk = BIT(2), .msg = "tx_vlan_tag_mem_ecc_mbit_err", 390 .reset_level = HNS3_GLOBAL_RESET }, 391 { .int_msk = BIT(3), .msg = "FD_CN0_memory_ecc_mbit_err", 392 .reset_level = HNS3_GLOBAL_RESET }, 393 { .int_msk = BIT(4), .msg = "FD_CN1_memory_ecc_mbit_err", 394 .reset_level = HNS3_GLOBAL_RESET }, 395 { .int_msk = BIT(5), .msg = "GRO_AD_memory_ecc_mbit_err", 396 .reset_level = HNS3_GLOBAL_RESET }, 397 { .int_msk = 0, .msg = NULL, 398 .reset_level = HNS3_NONE_RESET} 399 }; 400 401 static const struct hns3_hw_error ppu_mpf_abnormal_int_st3[] = { 402 { .int_msk = BIT(4), .msg = "gro_bd_ecc_mbit_err", 403 .reset_level = HNS3_GLOBAL_RESET }, 404 { .int_msk = BIT(5), .msg = "gro_context_ecc_mbit_err", 405 .reset_level = HNS3_GLOBAL_RESET }, 406 { .int_msk = BIT(6), .msg = "rx_stash_cfg_ecc_mbit_err", 407 .reset_level = HNS3_GLOBAL_RESET }, 408 { .int_msk = BIT(7), .msg = "axi_rd_fbd_ecc_mbit_err", 409 .reset_level = HNS3_GLOBAL_RESET }, 410 { .int_msk = 0, .msg = NULL, 411 .reset_level = HNS3_NONE_RESET} 412 }; 413 414 static const struct hns3_hw_error tm_sch_int[] = { 415 { .int_msk = BIT(1), .msg = "tm_sch_ecc_mbit_err", 416 .reset_level = HNS3_GLOBAL_RESET }, 417 { .int_msk = BIT(2), .msg = "tm_sch_port_shap_sub_fifo_wr_err", 418 .reset_level = HNS3_GLOBAL_RESET }, 419 { .int_msk = BIT(3), .msg = "tm_sch_port_shap_sub_fifo_rd_err", 420 .reset_level = HNS3_GLOBAL_RESET }, 421 { .int_msk = BIT(4), .msg = "tm_sch_pg_pshap_sub_fifo_wr_err", 422 .reset_level = HNS3_GLOBAL_RESET }, 423 { .int_msk = BIT(5), .msg = "tm_sch_pg_pshap_sub_fifo_rd_err", 424 .reset_level = HNS3_GLOBAL_RESET }, 425 { .int_msk = BIT(6), .msg = "tm_sch_pg_cshap_sub_fifo_wr_err", 426 .reset_level = HNS3_GLOBAL_RESET }, 427 { .int_msk = BIT(7), .msg = "tm_sch_pg_cshap_sub_fifo_rd_err", 428 .reset_level = HNS3_GLOBAL_RESET }, 429 { .int_msk = BIT(8), .msg = "tm_sch_pri_pshap_sub_fifo_wr_err", 430 .reset_level = HNS3_GLOBAL_RESET }, 431 { .int_msk = BIT(9), .msg = "tm_sch_pri_pshap_sub_fifo_rd_err", 432 .reset_level = HNS3_GLOBAL_RESET }, 433 { .int_msk = BIT(10), .msg = "tm_sch_pri_cshap_sub_fifo_wr_err", 434 .reset_level = HNS3_GLOBAL_RESET }, 435 { .int_msk = BIT(11), .msg = "tm_sch_pri_cshap_sub_fifo_rd_err", 436 .reset_level = HNS3_GLOBAL_RESET }, 437 { .int_msk = BIT(12), .msg = "tm_sch_port_shap_offset_fifo_wr_err", 438 .reset_level = HNS3_GLOBAL_RESET }, 439 { .int_msk = BIT(13), .msg = "tm_sch_port_shap_offset_fifo_rd_err", 440 .reset_level = HNS3_GLOBAL_RESET }, 441 { .int_msk = BIT(14), .msg = "tm_sch_pg_pshap_offset_fifo_wr_err", 442 .reset_level = HNS3_GLOBAL_RESET }, 443 { .int_msk = BIT(15), .msg = "tm_sch_pg_pshap_offset_fifo_rd_err", 444 .reset_level = HNS3_GLOBAL_RESET }, 445 { .int_msk = BIT(16), .msg = "tm_sch_pg_cshap_offset_fifo_wr_err", 446 .reset_level = HNS3_GLOBAL_RESET }, 447 { .int_msk = BIT(17), .msg = "tm_sch_pg_cshap_offset_fifo_rd_err", 448 .reset_level = HNS3_GLOBAL_RESET }, 449 { .int_msk = BIT(18), .msg = "tm_sch_pri_pshap_offset_fifo_wr_err", 450 .reset_level = HNS3_GLOBAL_RESET }, 451 { .int_msk = BIT(19), .msg = "tm_sch_pri_pshap_offset_fifo_rd_err", 452 .reset_level = HNS3_GLOBAL_RESET }, 453 { .int_msk = BIT(20), .msg = "tm_sch_pri_cshap_offset_fifo_wr_err", 454 .reset_level = HNS3_GLOBAL_RESET }, 455 { .int_msk = BIT(21), .msg = "tm_sch_pri_cshap_offset_fifo_rd_err", 456 .reset_level = HNS3_GLOBAL_RESET }, 457 { .int_msk = BIT(22), .msg = "tm_sch_rq_fifo_wr_err", 458 .reset_level = HNS3_GLOBAL_RESET }, 459 { .int_msk = BIT(23), .msg = "tm_sch_rq_fifo_rd_err", 460 .reset_level = HNS3_GLOBAL_RESET }, 461 { .int_msk = BIT(24), .msg = "tm_sch_nq_fifo_wr_err", 462 .reset_level = HNS3_GLOBAL_RESET }, 463 { .int_msk = BIT(25), .msg = "tm_sch_nq_fifo_rd_err", 464 .reset_level = HNS3_GLOBAL_RESET }, 465 { .int_msk = BIT(26), .msg = "tm_sch_roce_up_fifo_wr_err", 466 .reset_level = HNS3_GLOBAL_RESET }, 467 { .int_msk = BIT(27), .msg = "tm_sch_roce_up_fifo_rd_err", 468 .reset_level = HNS3_GLOBAL_RESET }, 469 { .int_msk = BIT(28), .msg = "tm_sch_rcb_byte_fifo_wr_err", 470 .reset_level = HNS3_GLOBAL_RESET }, 471 { .int_msk = BIT(29), .msg = "tm_sch_rcb_byte_fifo_rd_err", 472 .reset_level = HNS3_GLOBAL_RESET }, 473 { .int_msk = BIT(30), .msg = "tm_sch_ssu_byte_fifo_wr_err", 474 .reset_level = HNS3_GLOBAL_RESET }, 475 { .int_msk = BIT(31), .msg = "tm_sch_ssu_byte_fifo_rd_err", 476 .reset_level = HNS3_GLOBAL_RESET }, 477 { .int_msk = 0, .msg = NULL, 478 .reset_level = HNS3_NONE_RESET} 479 }; 480 481 static const struct hns3_hw_error qcn_fifo_int[] = { 482 { .int_msk = BIT(0), .msg = "qcn_shap_gp0_sch_fifo_rd_err", 483 .reset_level = HNS3_GLOBAL_RESET }, 484 { .int_msk = BIT(1), .msg = "qcn_shap_gp0_sch_fifo_wr_err", 485 .reset_level = HNS3_GLOBAL_RESET }, 486 { .int_msk = BIT(2), .msg = "qcn_shap_gp1_sch_fifo_rd_err", 487 .reset_level = HNS3_GLOBAL_RESET }, 488 { .int_msk = BIT(3), .msg = "qcn_shap_gp1_sch_fifo_wr_err", 489 .reset_level = HNS3_GLOBAL_RESET }, 490 { .int_msk = BIT(4), .msg = "qcn_shap_gp2_sch_fifo_rd_err", 491 .reset_level = HNS3_GLOBAL_RESET }, 492 { .int_msk = BIT(5), .msg = "qcn_shap_gp2_sch_fifo_wr_err", 493 .reset_level = HNS3_GLOBAL_RESET }, 494 { .int_msk = BIT(6), .msg = "qcn_shap_gp3_sch_fifo_rd_err", 495 .reset_level = HNS3_GLOBAL_RESET }, 496 { .int_msk = BIT(7), .msg = "qcn_shap_gp3_sch_fifo_wr_err", 497 .reset_level = HNS3_GLOBAL_RESET }, 498 { .int_msk = BIT(8), .msg = "qcn_shap_gp0_offset_fifo_rd_err", 499 .reset_level = HNS3_GLOBAL_RESET }, 500 { .int_msk = BIT(9), .msg = "qcn_shap_gp0_offset_fifo_wr_err", 501 .reset_level = HNS3_GLOBAL_RESET }, 502 { .int_msk = BIT(10), .msg = "qcn_shap_gp1_offset_fifo_rd_err", 503 .reset_level = HNS3_GLOBAL_RESET }, 504 { .int_msk = BIT(11), .msg = "qcn_shap_gp1_offset_fifo_wr_err", 505 .reset_level = HNS3_GLOBAL_RESET }, 506 { .int_msk = BIT(12), .msg = "qcn_shap_gp2_offset_fifo_rd_err", 507 .reset_level = HNS3_GLOBAL_RESET }, 508 { .int_msk = BIT(13), .msg = "qcn_shap_gp2_offset_fifo_wr_err", 509 .reset_level = HNS3_GLOBAL_RESET }, 510 { .int_msk = BIT(14), .msg = "qcn_shap_gp3_offset_fifo_rd_err", 511 .reset_level = HNS3_GLOBAL_RESET }, 512 { .int_msk = BIT(15), .msg = "qcn_shap_gp3_offset_fifo_wr_err", 513 .reset_level = HNS3_GLOBAL_RESET }, 514 { .int_msk = BIT(16), .msg = "qcn_byte_info_fifo_rd_err", 515 .reset_level = HNS3_GLOBAL_RESET }, 516 { .int_msk = BIT(17), .msg = "qcn_byte_info_fifo_wr_err", 517 .reset_level = HNS3_GLOBAL_RESET }, 518 { .int_msk = 0, .msg = NULL, 519 .reset_level = HNS3_NONE_RESET} 520 }; 521 522 static const struct hns3_hw_error qcn_ecc_int[] = { 523 { .int_msk = BIT(1), .msg = "qcn_byte_mem_ecc_mbit_err", 524 .reset_level = HNS3_GLOBAL_RESET }, 525 { .int_msk = BIT(3), .msg = "qcn_time_mem_ecc_mbit_err", 526 .reset_level = HNS3_GLOBAL_RESET }, 527 { .int_msk = BIT(5), .msg = "qcn_fb_mem_ecc_mbit_err", 528 .reset_level = HNS3_GLOBAL_RESET }, 529 { .int_msk = BIT(7), .msg = "qcn_link_mem_ecc_mbit_err", 530 .reset_level = HNS3_GLOBAL_RESET }, 531 { .int_msk = BIT(9), .msg = "qcn_rate_mem_ecc_mbit_err", 532 .reset_level = HNS3_GLOBAL_RESET }, 533 { .int_msk = BIT(11), .msg = "qcn_tmplt_mem_ecc_mbit_err", 534 .reset_level = HNS3_GLOBAL_RESET }, 535 { .int_msk = BIT(13), .msg = "qcn_shap_cfg_mem_ecc_mbit_err", 536 .reset_level = HNS3_GLOBAL_RESET }, 537 { .int_msk = BIT(15), .msg = "qcn_gp0_barrel_mem_ecc_mbit_err", 538 .reset_level = HNS3_GLOBAL_RESET }, 539 { .int_msk = BIT(17), .msg = "qcn_gp1_barrel_mem_ecc_mbit_err", 540 .reset_level = HNS3_GLOBAL_RESET }, 541 { .int_msk = BIT(19), .msg = "qcn_gp2_barrel_mem_ecc_mbit_err", 542 .reset_level = HNS3_GLOBAL_RESET }, 543 { .int_msk = BIT(21), .msg = "qcn_gp3_barral_mem_ecc_mbit_err", 544 .reset_level = HNS3_GLOBAL_RESET }, 545 { .int_msk = 0, .msg = NULL, 546 .reset_level = HNS3_NONE_RESET} 547 }; 548 549 static const struct hns3_hw_error ncsi_ecc_int[] = { 550 { .int_msk = BIT(1), .msg = "ncsi_tx_ecc_mbit_err", 551 .reset_level = HNS3_NONE_RESET }, 552 { .int_msk = 0, .msg = NULL, 553 .reset_level = HNS3_NONE_RESET} 554 }; 555 556 static const struct hns3_hw_error ssu_fifo_overflow_int[] = { 557 { .int_msk = BIT(0), .msg = "ig_mac_inf_int", 558 .reset_level = HNS3_GLOBAL_RESET }, 559 { .int_msk = BIT(1), .msg = "ig_host_inf_int", 560 .reset_level = HNS3_GLOBAL_RESET }, 561 { .int_msk = BIT(2), .msg = "ig_roc_buf_int", 562 .reset_level = HNS3_GLOBAL_RESET }, 563 { .int_msk = BIT(3), .msg = "ig_host_data_fifo_int", 564 .reset_level = HNS3_GLOBAL_RESET }, 565 { .int_msk = BIT(4), .msg = "ig_host_key_fifo_int", 566 .reset_level = HNS3_GLOBAL_RESET }, 567 { .int_msk = BIT(5), .msg = "tx_qcn_fifo_int", 568 .reset_level = HNS3_GLOBAL_RESET }, 569 { .int_msk = BIT(6), .msg = "rx_qcn_fifo_int", 570 .reset_level = HNS3_GLOBAL_RESET }, 571 { .int_msk = BIT(7), .msg = "tx_pf_rd_fifo_int", 572 .reset_level = HNS3_GLOBAL_RESET }, 573 { .int_msk = BIT(8), .msg = "rx_pf_rd_fifo_int", 574 .reset_level = HNS3_GLOBAL_RESET }, 575 { .int_msk = BIT(9), .msg = "qm_eof_fifo_int", 576 .reset_level = HNS3_GLOBAL_RESET }, 577 { .int_msk = BIT(10), .msg = "mb_rlt_fifo_int", 578 .reset_level = HNS3_GLOBAL_RESET }, 579 { .int_msk = BIT(11), .msg = "dup_uncopy_fifo_int", 580 .reset_level = HNS3_GLOBAL_RESET }, 581 { .int_msk = BIT(12), .msg = "dup_cnt_rd_fifo_int", 582 .reset_level = HNS3_GLOBAL_RESET }, 583 { .int_msk = BIT(13), .msg = "dup_cnt_drop_fifo_int", 584 .reset_level = HNS3_GLOBAL_RESET }, 585 { .int_msk = BIT(14), .msg = "dup_cnt_wrb_fifo_int", 586 .reset_level = HNS3_GLOBAL_RESET }, 587 { .int_msk = BIT(15), .msg = "host_cmd_fifo_int", 588 .reset_level = HNS3_GLOBAL_RESET }, 589 { .int_msk = BIT(16), .msg = "mac_cmd_fifo_int", 590 .reset_level = HNS3_GLOBAL_RESET }, 591 { .int_msk = BIT(17), .msg = "host_cmd_bitmap_empty_int", 592 .reset_level = HNS3_GLOBAL_RESET }, 593 { .int_msk = BIT(18), .msg = "mac_cmd_bitmap_empty_int", 594 .reset_level = HNS3_GLOBAL_RESET }, 595 { .int_msk = BIT(19), .msg = "dup_bitmap_empty_int", 596 .reset_level = HNS3_GLOBAL_RESET }, 597 { .int_msk = BIT(20), .msg = "out_queue_bitmap_empty_int", 598 .reset_level = HNS3_GLOBAL_RESET }, 599 { .int_msk = BIT(21), .msg = "bank2_bitmap_empty_int", 600 .reset_level = HNS3_GLOBAL_RESET }, 601 { .int_msk = BIT(22), .msg = "bank1_bitmap_empty_int", 602 .reset_level = HNS3_GLOBAL_RESET }, 603 { .int_msk = BIT(23), .msg = "bank0_bitmap_empty_int", 604 .reset_level = HNS3_GLOBAL_RESET }, 605 { .int_msk = 0, .msg = NULL, 606 .reset_level = HNS3_NONE_RESET} 607 }; 608 609 static const struct hns3_hw_error ssu_ets_tcg_int[] = { 610 { .int_msk = BIT(0), .msg = "ets_rd_int_rx_tcg", 611 .reset_level = HNS3_GLOBAL_RESET }, 612 { .int_msk = BIT(1), .msg = "ets_wr_int_rx_tcg", 613 .reset_level = HNS3_GLOBAL_RESET }, 614 { .int_msk = BIT(2), .msg = "ets_rd_int_tx_tcg", 615 .reset_level = HNS3_GLOBAL_RESET }, 616 { .int_msk = BIT(3), .msg = "ets_wr_int_tx_tcg", 617 .reset_level = HNS3_GLOBAL_RESET }, 618 { .int_msk = 0, .msg = NULL, 619 .reset_level = HNS3_NONE_RESET} 620 }; 621 622 static const struct hns3_hw_error igu_egu_tnl_int[] = { 623 { .int_msk = BIT(0), .msg = "rx_buf_overflow", 624 .reset_level = HNS3_GLOBAL_RESET }, 625 { .int_msk = BIT(1), .msg = "rx_stp_fifo_overflow", 626 .reset_level = HNS3_GLOBAL_RESET }, 627 { .int_msk = BIT(2), .msg = "rx_stp_fifo_underflow", 628 .reset_level = HNS3_GLOBAL_RESET }, 629 { .int_msk = BIT(3), .msg = "tx_buf_overflow", 630 .reset_level = HNS3_GLOBAL_RESET }, 631 { .int_msk = BIT(4), .msg = "tx_buf_underrun", 632 .reset_level = HNS3_GLOBAL_RESET }, 633 { .int_msk = BIT(5), .msg = "rx_stp_buf_overflow", 634 .reset_level = HNS3_GLOBAL_RESET }, 635 { .int_msk = 0, .msg = NULL, 636 .reset_level = HNS3_NONE_RESET} 637 }; 638 639 static const struct hns3_hw_error ssu_port_based_err_int[] = { 640 { .int_msk = BIT(0), .msg = "roc_pkt_without_key_port", 641 .reset_level = HNS3_FUNC_RESET }, 642 { .int_msk = BIT(1), .msg = "tpu_pkt_without_key_port", 643 .reset_level = HNS3_GLOBAL_RESET }, 644 { .int_msk = BIT(2), .msg = "igu_pkt_without_key_port", 645 .reset_level = HNS3_GLOBAL_RESET }, 646 { .int_msk = BIT(3), .msg = "roc_eof_mis_match_port", 647 .reset_level = HNS3_GLOBAL_RESET }, 648 { .int_msk = BIT(4), .msg = "tpu_eof_mis_match_port", 649 .reset_level = HNS3_GLOBAL_RESET }, 650 { .int_msk = BIT(5), .msg = "igu_eof_mis_match_port", 651 .reset_level = HNS3_GLOBAL_RESET }, 652 { .int_msk = BIT(6), .msg = "roc_sof_mis_match_port", 653 .reset_level = HNS3_GLOBAL_RESET }, 654 { .int_msk = BIT(7), .msg = "tpu_sof_mis_match_port", 655 .reset_level = HNS3_GLOBAL_RESET }, 656 { .int_msk = BIT(8), .msg = "igu_sof_mis_match_port", 657 .reset_level = HNS3_GLOBAL_RESET }, 658 { .int_msk = BIT(11), .msg = "ets_rd_int_rx_port", 659 .reset_level = HNS3_GLOBAL_RESET }, 660 { .int_msk = BIT(12), .msg = "ets_wr_int_rx_port", 661 .reset_level = HNS3_GLOBAL_RESET }, 662 { .int_msk = BIT(13), .msg = "ets_rd_int_tx_port", 663 .reset_level = HNS3_GLOBAL_RESET }, 664 { .int_msk = BIT(14), .msg = "ets_wr_int_tx_port", 665 .reset_level = HNS3_GLOBAL_RESET }, 666 { .int_msk = 0, .msg = NULL, 667 .reset_level = HNS3_NONE_RESET} 668 }; 669 670 static const struct hns3_hw_error_desc mpf_ras_err_tbl[] = { 671 { .desc_offset = 0, .data_offset = 0, 672 .msg = "IMP_TCM_ECC_INT_STS", 673 .hw_err = imp_tcm_ecc_int }, 674 { .desc_offset = 0, .data_offset = 1, 675 .msg = "CMDQ_MEM_ECC_INT_STS", 676 .hw_err = cmdq_mem_ecc_int }, 677 { .desc_offset = 0, .data_offset = 2, 678 .msg = "IMP_RD_POISON_INT_STS", 679 .hw_err = imp_rd_poison_int }, 680 { .desc_offset = 0, .data_offset = 3, 681 .msg = "TQP_INT_ECC_INT_STS", 682 .hw_err = tqp_int_ecc_int }, 683 { .desc_offset = 0, .data_offset = 4, 684 .msg = "MSIX_ECC_INT_STS", 685 .hw_err = msix_ecc_int }, 686 { .desc_offset = 2, .data_offset = 2, 687 .msg = "SSU_ECC_MULTI_BIT_INT_0", 688 .hw_err = ssu_ecc_multi_bit_int_0 }, 689 { .desc_offset = 2, .data_offset = 3, 690 .msg = "SSU_ECC_MULTI_BIT_INT_1", 691 .hw_err = ssu_ecc_multi_bit_int_1 }, 692 { .desc_offset = 2, .data_offset = 4, 693 .msg = "SSU_COMMON_ERR_INT", 694 .hw_err = ssu_common_ecc_int }, 695 { .desc_offset = 3, .data_offset = 0, 696 .msg = "IGU_INT_STS", 697 .hw_err = igu_int }, 698 { .desc_offset = 4, .data_offset = 1, 699 .msg = "PPP_MPF_ABNORMAL_INT_ST1", 700 .hw_err = ppp_mpf_abnormal_int_st1 }, 701 { .desc_offset = 4, .data_offset = 3, 702 .msg = "PPP_MPF_ABNORMAL_INT_ST3", 703 .hw_err = ppp_mpf_abnormal_int_st3 }, 704 { .desc_offset = 5, .data_offset = 1, 705 .msg = "PPU_MPF_ABNORMAL_INT_ST1", 706 .hw_err = ppu_mpf_abnormal_int_st1 }, 707 { .desc_offset = 5, .data_offset = 2, 708 .msg = "PPU_MPF_ABNORMAL_INT_ST2_RAS", 709 .hw_err = ppu_mpf_abnormal_int_st2_ras }, 710 { .desc_offset = 5, .data_offset = 3, 711 .msg = "PPU_MPF_ABNORMAL_INT_ST3", 712 .hw_err = ppu_mpf_abnormal_int_st3 }, 713 { .desc_offset = 6, .data_offset = 0, 714 .msg = "TM_SCH_RINT", 715 .hw_err = tm_sch_int }, 716 { .desc_offset = 7, .data_offset = 0, 717 .msg = "QCN_FIFO_RINT", 718 .hw_err = qcn_fifo_int }, 719 { .desc_offset = 7, .data_offset = 1, 720 .msg = "QCN_ECC_RINT", 721 .hw_err = qcn_ecc_int }, 722 { .desc_offset = 9, .data_offset = 0, 723 .msg = "NCSI_ECC_INT_RPT", 724 .hw_err = ncsi_ecc_int }, 725 { .desc_offset = 0, .data_offset = 0, 726 .msg = NULL, 727 .hw_err = NULL } 728 }; 729 730 static const struct hns3_hw_error_desc pf_ras_err_tbl[] = { 731 { .desc_offset = 0, .data_offset = 0, 732 .msg = "SSU_PORT_BASED_ERR_INT_RAS", 733 .hw_err = ssu_port_based_err_int }, 734 { .desc_offset = 0, .data_offset = 1, 735 .msg = "SSU_FIFO_OVERFLOW_INT", 736 .hw_err = ssu_fifo_overflow_int }, 737 { .desc_offset = 0, .data_offset = 2, 738 .msg = "SSU_ETS_TCG_INT", 739 .hw_err = ssu_ets_tcg_int }, 740 { .desc_offset = 1, .data_offset = 0, 741 .msg = "IGU_EGU_TNL_INT_STS", 742 .hw_err = igu_egu_tnl_int }, 743 { .desc_offset = 3, .data_offset = 0, 744 .msg = "PPU_PF_ABNORMAL_INT_ST_RAS", 745 .hw_err = ppu_pf_abnormal_int_ras }, 746 { .desc_offset = 0, .data_offset = 0, 747 .msg = NULL, 748 .hw_err = NULL } 749 }; 750 751 static const struct hns3_hw_error_desc mpf_msix_err_tbl[] = { 752 { .desc_offset = 1, .data_offset = 0, 753 .msg = "MAC_AFIFO_TNL_INT_R", 754 .hw_err = mac_afifo_tnl_int }, 755 { .desc_offset = 5, .data_offset = 2, 756 .msg = "PPU_MPF_ABNORMAL_INT_ST2_MSIX", 757 .hw_err = ppu_mpf_abnormal_int_st2_msix }, 758 { .desc_offset = 0, .data_offset = 0, 759 .msg = NULL, 760 .hw_err = NULL } 761 }; 762 763 static const struct hns3_hw_error_desc pf_msix_err_tbl[] = { 764 { .desc_offset = 0, .data_offset = 0, 765 .msg = "SSU_PORT_BASED_ERR_INT_MSIX", 766 .hw_err = ssu_port_based_pf_int }, 767 { .desc_offset = 2, .data_offset = 0, 768 .msg = "PPP_PF_ABNORMAL_INT_ST0", 769 .hw_err = ppp_pf_abnormal_int }, 770 { .desc_offset = 3, .data_offset = 0, 771 .msg = "PPU_PF_ABNORMAL_INT_ST_MSIX", 772 .hw_err = ppu_pf_abnormal_int_msix }, 773 { .desc_offset = 0, .data_offset = 0, 774 .msg = NULL, 775 .hw_err = NULL } 776 }; 777 778 enum hns3_hw_err_type { 779 MPF_MSIX_ERR, 780 PF_MSIX_ERR, 781 MPF_RAS_ERR, 782 PF_RAS_ERR, 783 }; 784 785 static int 786 hns3_config_ncsi_hw_err_int(struct hns3_adapter *hns, bool en) 787 { 788 struct hns3_hw *hw = &hns->hw; 789 struct hns3_cmd_desc desc; 790 int ret; 791 792 /* configure NCSI error interrupts */ 793 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_NCSI_INT_EN, false); 794 if (en) 795 desc.data[0] = rte_cpu_to_le_32(HNS3_NCSI_ERR_INT_EN); 796 797 ret = hns3_cmd_send(hw, &desc, 1); 798 if (ret) 799 hns3_err(hw, "fail to %s NCSI error interrupts, ret = %d", 800 en ? "enable" : "disable", ret); 801 802 return ret; 803 } 804 805 static int 806 enable_igu_egu_err_intr(struct hns3_adapter *hns, bool en) 807 { 808 struct hns3_hw *hw = &hns->hw; 809 struct hns3_cmd_desc desc; 810 int ret; 811 812 /* configure IGU,EGU error interrupts */ 813 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_IGU_COMMON_INT_EN, false); 814 if (en) 815 desc.data[0] = rte_cpu_to_le_32(HNS3_IGU_ERR_INT_ENABLE); 816 else 817 desc.data[0] = rte_cpu_to_le_32(HNS3_IGU_ERR_INT_DISABLE); 818 819 desc.data[1] = rte_cpu_to_le_32(HNS3_IGU_ERR_INT_EN_MASK); 820 821 ret = hns3_cmd_send(hw, &desc, 1); 822 if (ret) { 823 hns3_err(hw, "fail to %s IGU common interrupts, ret = %d", 824 en ? "enable" : "disable", ret); 825 return ret; 826 } 827 828 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_IGU_EGU_TNL_INT_EN, false); 829 if (en) 830 desc.data[0] = rte_cpu_to_le_32(HNS3_IGU_TNL_ERR_INT_EN); 831 832 desc.data[1] = rte_cpu_to_le_32(HNS3_IGU_TNL_ERR_INT_EN_MASK); 833 834 ret = hns3_cmd_send(hw, &desc, 1); 835 if (ret) { 836 hns3_err(hw, "fail to %s IGU-EGU TNL interrupts, ret = %d", 837 en ? "enable" : "disable", ret); 838 return ret; 839 } 840 841 return hns3_config_ncsi_hw_err_int(hns, en); 842 } 843 844 static int 845 config_ppp_err_intr(struct hns3_adapter *hns, uint32_t cmd, bool en) 846 { 847 struct hns3_hw *hw = &hns->hw; 848 struct hns3_cmd_desc desc[2]; 849 int ret; 850 851 /* configure PPP error interrupts */ 852 hns3_cmd_setup_basic_desc(&desc[0], cmd, false); 853 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 854 hns3_cmd_setup_basic_desc(&desc[1], cmd, false); 855 856 if (cmd == HNS3_OPC_PPP_CMD0_INT_CMD) { 857 if (en) { 858 desc[0].data[0] = 859 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT0_EN); 860 desc[0].data[1] = 861 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT1_EN); 862 desc[0].data[4] = 863 rte_cpu_to_le_32(HNS3_PPP_PF_ERR_INT_EN); 864 } 865 866 desc[1].data[0] = 867 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT0_EN_MASK); 868 desc[1].data[1] = 869 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT1_EN_MASK); 870 desc[1].data[2] = 871 rte_cpu_to_le_32(HNS3_PPP_PF_ERR_INT_EN_MASK); 872 } else if (cmd == HNS3_OPC_PPP_CMD1_INT_CMD) { 873 if (en) { 874 desc[0].data[0] = 875 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT2_EN); 876 desc[0].data[1] = 877 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT3_EN); 878 } 879 880 desc[1].data[0] = 881 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT2_EN_MASK); 882 desc[1].data[1] = 883 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT3_EN_MASK); 884 } 885 886 ret = hns3_cmd_send(hw, &desc[0], 2); 887 if (ret) 888 hns3_err(hw, "fail to %s PPP error int, ret = %d", 889 en ? "enable" : "disable", ret); 890 891 return ret; 892 } 893 894 static int 895 enable_ppp_err_intr(struct hns3_adapter *hns, bool en) 896 { 897 int ret; 898 899 ret = config_ppp_err_intr(hns, HNS3_OPC_PPP_CMD0_INT_CMD, en); 900 if (ret) 901 return ret; 902 903 return config_ppp_err_intr(hns, HNS3_OPC_PPP_CMD1_INT_CMD, en); 904 } 905 906 static int 907 enable_ssu_err_intr(struct hns3_adapter *hns, bool en) 908 { 909 struct hns3_hw *hw = &hns->hw; 910 struct hns3_cmd_desc desc[2]; 911 int ret; 912 913 /* configure SSU ecc error interrupts */ 914 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_SSU_ECC_INT_CMD, false); 915 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 916 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_SSU_ECC_INT_CMD, false); 917 if (en) { 918 desc[0].data[0] = 919 rte_cpu_to_le_32(HNS3_SSU_1BIT_ECC_ERR_INT_EN); 920 desc[0].data[1] = 921 rte_cpu_to_le_32(HNS3_SSU_MULTI_BIT_ECC_ERR_INT_EN); 922 desc[0].data[4] = 923 rte_cpu_to_le_32(HNS3_SSU_BIT32_ECC_ERR_INT_EN); 924 } 925 926 desc[1].data[0] = rte_cpu_to_le_32(HNS3_SSU_1BIT_ECC_ERR_INT_EN_MASK); 927 desc[1].data[1] = 928 rte_cpu_to_le_32(HNS3_SSU_MULTI_BIT_ECC_ERR_INT_EN_MASK); 929 desc[1].data[2] = rte_cpu_to_le_32(HNS3_SSU_BIT32_ECC_ERR_INT_EN_MASK); 930 931 ret = hns3_cmd_send(hw, &desc[0], 2); 932 if (ret) { 933 hns3_err(hw, "fail to %s SSU ECC error interrupt, ret = %d", 934 en ? "enable" : "disable", ret); 935 return ret; 936 } 937 938 /* configure SSU common error interrupts */ 939 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_SSU_COMMON_INT_CMD, false); 940 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 941 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_SSU_COMMON_INT_CMD, false); 942 943 if (en) { 944 desc[0].data[0] = rte_cpu_to_le_32(HNS3_SSU_COMMON_INT_EN); 945 desc[0].data[1] = 946 rte_cpu_to_le_32(HNS3_SSU_PORT_BASED_ERR_INT_EN); 947 desc[0].data[2] = 948 rte_cpu_to_le_32(HNS3_SSU_FIFO_OVERFLOW_ERR_INT_EN); 949 } 950 951 desc[1].data[0] = rte_cpu_to_le_32(HNS3_SSU_COMMON_INT_EN_MASK | 952 HNS3_SSU_PORT_BASED_ERR_INT_EN_MASK); 953 desc[1].data[1] = 954 rte_cpu_to_le_32(HNS3_SSU_FIFO_OVERFLOW_ERR_INT_EN_MASK); 955 956 ret = hns3_cmd_send(hw, &desc[0], 2); 957 if (ret) 958 hns3_err(hw, "fail to %s SSU COMMON error intr, ret = %d", 959 en ? "enable" : "disable", ret); 960 961 return ret; 962 } 963 964 static int 965 config_ppu_err_intrs(struct hns3_adapter *hns, uint32_t cmd, bool en) 966 { 967 struct hns3_hw *hw = &hns->hw; 968 struct hns3_cmd_desc desc[2]; 969 int num = 1; 970 971 /* configure PPU error interrupts */ 972 switch (cmd) { 973 case HNS3_OPC_PPU_MPF_ECC_INT_CMD: 974 hns3_cmd_setup_basic_desc(&desc[0], cmd, false); 975 desc[0].flag |= HNS3_CMD_FLAG_NEXT; 976 hns3_cmd_setup_basic_desc(&desc[1], cmd, false); 977 if (en) { 978 desc[0].data[0] = HNS3_PPU_MPF_ABNORMAL_INT0_EN; 979 desc[0].data[1] = HNS3_PPU_MPF_ABNORMAL_INT1_EN; 980 desc[1].data[3] = HNS3_PPU_MPF_ABNORMAL_INT3_EN; 981 desc[1].data[4] = HNS3_PPU_MPF_ABNORMAL_INT2_EN; 982 } 983 984 desc[1].data[0] = HNS3_PPU_MPF_ABNORMAL_INT0_EN_MASK; 985 desc[1].data[1] = HNS3_PPU_MPF_ABNORMAL_INT1_EN_MASK; 986 desc[1].data[2] = HNS3_PPU_MPF_ABNORMAL_INT2_EN_MASK; 987 desc[1].data[3] |= HNS3_PPU_MPF_ABNORMAL_INT3_EN_MASK; 988 num = 2; 989 break; 990 case HNS3_OPC_PPU_MPF_OTHER_INT_CMD: 991 hns3_cmd_setup_basic_desc(&desc[0], cmd, false); 992 if (en) 993 desc[0].data[0] = HNS3_PPU_MPF_ABNORMAL_INT2_EN2; 994 995 desc[0].data[2] = HNS3_PPU_MPF_ABNORMAL_INT2_EN2_MASK; 996 break; 997 case HNS3_OPC_PPU_PF_OTHER_INT_CMD: 998 hns3_cmd_setup_basic_desc(&desc[0], cmd, false); 999 if (en) 1000 desc[0].data[0] = HNS3_PPU_PF_ABNORMAL_INT_EN; 1001 1002 desc[0].data[2] = HNS3_PPU_PF_ABNORMAL_INT_EN_MASK; 1003 break; 1004 default: 1005 hns3_err(hw, 1006 "Invalid cmd(%u) to configure PPU error interrupts.", 1007 cmd); 1008 return -EINVAL; 1009 } 1010 1011 return hns3_cmd_send(hw, &desc[0], num); 1012 } 1013 1014 static int 1015 enable_ppu_err_intr(struct hns3_adapter *hns, bool en) 1016 { 1017 struct hns3_hw *hw = &hns->hw; 1018 int ret; 1019 1020 ret = config_ppu_err_intrs(hns, HNS3_OPC_PPU_MPF_ECC_INT_CMD, en); 1021 if (ret) { 1022 hns3_err(hw, "fail to %s PPU MPF ECC error intr, ret = %d", 1023 en ? "enable" : "disable", ret); 1024 return ret; 1025 } 1026 1027 ret = config_ppu_err_intrs(hns, HNS3_OPC_PPU_MPF_OTHER_INT_CMD, en); 1028 if (ret) { 1029 hns3_err(hw, "fail to %s PPU MPF other intr, ret = %d", 1030 en ? "enable" : "disable", ret); 1031 return ret; 1032 } 1033 1034 ret = config_ppu_err_intrs(hns, HNS3_OPC_PPU_PF_OTHER_INT_CMD, en); 1035 if (ret) 1036 hns3_err(hw, "fail to %s PPU PF error interrupts, ret = %d", 1037 en ? "enable" : "disable", ret); 1038 return ret; 1039 } 1040 1041 static int 1042 enable_tm_err_intr(struct hns3_adapter *hns, bool en) 1043 { 1044 struct hns3_hw *hw = &hns->hw; 1045 struct hns3_cmd_desc desc; 1046 int ret; 1047 1048 /* configure TM SCH error interrupts */ 1049 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_SCH_ECC_INT_EN, false); 1050 if (en) 1051 desc.data[0] = rte_cpu_to_le_32(HNS3_TM_SCH_ECC_ERR_INT_EN); 1052 1053 ret = hns3_cmd_send(hw, &desc, 1); 1054 if (ret) { 1055 hns3_err(hw, "fail to %s TM SCH interrupts, ret = %d", 1056 en ? "enable" : "disable", ret); 1057 return ret; 1058 } 1059 1060 /* configure TM QCN hw errors */ 1061 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_QCN_MEM_INT_CFG, true); 1062 ret = hns3_cmd_send(hw, &desc, 1); 1063 if (ret) { 1064 hns3_err(hw, "fail to read TM QCN CFG status, ret = %d\n", ret); 1065 return ret; 1066 } 1067 1068 hns3_cmd_reuse_desc(&desc, false); 1069 if (en) 1070 desc.data[1] = rte_cpu_to_le_32(HNS3_TM_QCN_MEM_ERR_INT_EN); 1071 1072 ret = hns3_cmd_send(hw, &desc, 1); 1073 if (ret) 1074 hns3_err(hw, "fail to %s TM QCN mem errors, ret = %d\n", 1075 en ? "enable" : "disable", ret); 1076 1077 return ret; 1078 } 1079 1080 static int 1081 enable_common_err_intr(struct hns3_adapter *hns, bool en) 1082 { 1083 struct hns3_hw *hw = &hns->hw; 1084 struct hns3_cmd_desc desc[2]; 1085 int ret; 1086 1087 /* configure common error interrupts */ 1088 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_COMMON_ECC_INT_CFG, false); 1089 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1090 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_COMMON_ECC_INT_CFG, false); 1091 1092 if (en) { 1093 desc[0].data[0] = 1094 rte_cpu_to_le_32(HNS3_IMP_TCM_ECC_ERR_INT_EN); 1095 desc[0].data[2] = 1096 rte_cpu_to_le_32(HNS3_CMDQ_NIC_ECC_ERR_INT_EN); 1097 desc[0].data[3] = 1098 rte_cpu_to_le_32(HNS3_IMP_RD_POISON_ERR_INT_EN); 1099 desc[0].data[4] = 1100 rte_cpu_to_le_32(HNS3_TQP_ECC_ERR_INT_EN | 1101 HNS3_MSIX_SRAM_ECC_ERR_INT_EN); 1102 desc[0].data[5] = 1103 rte_cpu_to_le_32(HNS3_IMP_ITCM4_ECC_ERR_INT_EN); 1104 } 1105 1106 desc[1].data[0] = rte_cpu_to_le_32(HNS3_IMP_TCM_ECC_ERR_INT_EN_MASK); 1107 desc[1].data[2] = rte_cpu_to_le_32(HNS3_CMDQ_NIC_ECC_ERR_INT_EN_MASK); 1108 desc[1].data[3] = rte_cpu_to_le_32(HNS3_IMP_RD_POISON_ERR_INT_EN_MASK); 1109 desc[1].data[4] = rte_cpu_to_le_32(HNS3_TQP_ECC_ERR_INT_EN_MASK | 1110 HNS3_MSIX_SRAM_ECC_ERR_INT_EN_MASK); 1111 desc[1].data[5] = rte_cpu_to_le_32(HNS3_IMP_ITCM4_ECC_ERR_INT_EN_MASK); 1112 1113 ret = hns3_cmd_send(hw, &desc[0], RTE_DIM(desc)); 1114 if (ret) 1115 hns3_err(hw, "fail to %s common err interrupts, ret = %d\n", 1116 en ? "enable" : "disable", ret); 1117 1118 return ret; 1119 } 1120 1121 static int 1122 enable_mac_err_intr(struct hns3_adapter *hns, bool en) 1123 { 1124 struct hns3_hw *hw = &hns->hw; 1125 struct hns3_cmd_desc desc; 1126 int ret; 1127 1128 /* configure MAC common error interrupts */ 1129 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_COMMON_INT_EN, false); 1130 if (en) 1131 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_COMMON_ERR_INT_EN); 1132 1133 desc.data[1] = rte_cpu_to_le_32(HNS3_MAC_COMMON_ERR_INT_EN_MASK); 1134 1135 ret = hns3_cmd_send(hw, &desc, 1); 1136 if (ret) 1137 hns3_err(hw, "fail to %s MAC COMMON error intr: %d", 1138 en ? "enable" : "disable", ret); 1139 1140 return ret; 1141 } 1142 1143 static const struct hns3_hw_blk hw_blk[] = { 1144 { 1145 .name = "IGU_EGU", 1146 .enable_err_intr = enable_igu_egu_err_intr, 1147 }, 1148 { 1149 .name = "PPP", 1150 .enable_err_intr = enable_ppp_err_intr, 1151 }, 1152 { 1153 .name = "SSU", 1154 .enable_err_intr = enable_ssu_err_intr, 1155 }, 1156 { 1157 .name = "PPU", 1158 .enable_err_intr = enable_ppu_err_intr, 1159 }, 1160 { 1161 .name = "TM", 1162 .enable_err_intr = enable_tm_err_intr, 1163 }, 1164 { 1165 .name = "COMMON", 1166 .enable_err_intr = enable_common_err_intr, 1167 }, 1168 { 1169 .name = "MAC", 1170 .enable_err_intr = enable_mac_err_intr, 1171 }, 1172 { 1173 .name = NULL, 1174 .enable_err_intr = NULL, 1175 } 1176 }; 1177 1178 int 1179 hns3_enable_hw_error_intr(struct hns3_adapter *hns, bool en) 1180 { 1181 const struct hns3_hw_blk *module = hw_blk; 1182 int ret = 0; 1183 1184 while (module->enable_err_intr) { 1185 ret = module->enable_err_intr(hns, en); 1186 if (ret) 1187 return ret; 1188 1189 module++; 1190 } 1191 1192 return ret; 1193 } 1194 1195 static enum hns3_reset_level 1196 hns3_find_highest_level(struct hns3_adapter *hns, const char *reg, 1197 const struct hns3_hw_error *err, uint32_t err_sts) 1198 { 1199 enum hns3_reset_level reset_level = HNS3_FUNC_RESET; 1200 struct hns3_hw *hw = &hns->hw; 1201 bool need_reset = false; 1202 1203 while (err->msg) { 1204 if (err->int_msk & err_sts) { 1205 hns3_warn(hw, "%s %s found [error status=0x%x]", 1206 reg, err->msg, err_sts); 1207 if (err->reset_level != HNS3_NONE_RESET && 1208 err->reset_level >= reset_level) { 1209 reset_level = err->reset_level; 1210 need_reset = true; 1211 } 1212 hns3_error_int_stats_add(hns, reg); 1213 } 1214 err++; 1215 } 1216 if (need_reset) 1217 return reset_level; 1218 else 1219 return HNS3_NONE_RESET; 1220 } 1221 1222 static int 1223 query_num_bds(struct hns3_hw *hw, bool is_ras, uint32_t *mpf_bd_num, 1224 uint32_t *pf_bd_num) 1225 { 1226 uint32_t mpf_min_bd_num, pf_min_bd_num; 1227 uint32_t mpf_bd_num_val, pf_bd_num_val; 1228 enum hns3_opcode_type opcode; 1229 struct hns3_cmd_desc desc; 1230 int ret; 1231 1232 if (is_ras) { 1233 opcode = HNS3_OPC_QUERY_RAS_INT_STS_BD_NUM; 1234 mpf_min_bd_num = HNS3_MPF_RAS_INT_MIN_BD_NUM; 1235 pf_min_bd_num = HNS3_PF_RAS_INT_MIN_BD_NUM; 1236 } else { 1237 opcode = HNS3_OPC_QUERY_MSIX_INT_STS_BD_NUM; 1238 mpf_min_bd_num = HNS3_MPF_MSIX_INT_MIN_BD_NUM; 1239 pf_min_bd_num = HNS3_PF_MSIX_INT_MIN_BD_NUM; 1240 } 1241 1242 hns3_cmd_setup_basic_desc(&desc, opcode, true); 1243 ret = hns3_cmd_send(hw, &desc, 1); 1244 if (ret) { 1245 hns3_err(hw, "query num bds in msix failed, ret = %d", ret); 1246 return ret; 1247 } 1248 1249 mpf_bd_num_val = rte_le_to_cpu_32(desc.data[0]); 1250 pf_bd_num_val = rte_le_to_cpu_32(desc.data[1]); 1251 if (mpf_bd_num_val < mpf_min_bd_num || pf_bd_num_val < pf_min_bd_num) { 1252 hns3_err(hw, "error bd num: mpf(%u), min_mpf(%u), " 1253 "pf(%u), min_pf(%u)\n", mpf_bd_num_val, mpf_min_bd_num, 1254 pf_bd_num_val, pf_min_bd_num); 1255 return -EINVAL; 1256 } 1257 1258 *mpf_bd_num = mpf_bd_num_val; 1259 *pf_bd_num = pf_bd_num_val; 1260 1261 return 0; 1262 } 1263 1264 void 1265 hns3_intr_unregister(const struct rte_intr_handle *hdl, 1266 rte_intr_callback_fn cb_fn, void *cb_arg) 1267 { 1268 int retry_cnt = 0; 1269 int ret; 1270 1271 do { 1272 ret = rte_intr_callback_unregister(hdl, cb_fn, cb_arg); 1273 if (ret >= 0) { 1274 break; 1275 } else if (ret != -EAGAIN) { 1276 PMD_INIT_LOG(ERR, "Failed to unregister intr: %d", ret); 1277 break; 1278 } 1279 rte_delay_ms(HNS3_INTR_UNREG_FAIL_DELAY_MS); 1280 } while (retry_cnt++ < HNS3_INTR_UNREG_FAIL_RETRY_CNT); 1281 } 1282 1283 static uint32_t 1284 hns3_get_hw_error_status(struct hns3_cmd_desc *desc, uint8_t desc_offset, 1285 uint8_t data_offset) 1286 { 1287 uint32_t status; 1288 uint32_t *desc_data; 1289 1290 if (desc_offset == 0) 1291 status = rte_le_to_cpu_32(desc[desc_offset].data[data_offset]); 1292 else { 1293 desc_data = (uint32_t *)&desc[desc_offset]; 1294 status = rte_le_to_cpu_32(*(desc_data + data_offset)); 1295 } 1296 1297 return status; 1298 } 1299 1300 static int 1301 hns3_handle_hw_error(struct hns3_adapter *hns, struct hns3_cmd_desc *desc, 1302 int num, uint64_t *levels, enum hns3_hw_err_type err_type) 1303 { 1304 const struct hns3_hw_error_desc *err = pf_ras_err_tbl; 1305 enum hns3_opcode_type opcode; 1306 enum hns3_reset_level req_level; 1307 struct hns3_hw *hw = &hns->hw; 1308 uint32_t status; 1309 int ret; 1310 1311 switch (err_type) { 1312 case MPF_MSIX_ERR: 1313 err = mpf_msix_err_tbl; 1314 opcode = HNS3_OPC_QUERY_CLEAR_ALL_MPF_MSIX_INT; 1315 break; 1316 case PF_MSIX_ERR: 1317 err = pf_msix_err_tbl; 1318 opcode = HNS3_OPC_QUERY_CLEAR_ALL_PF_MSIX_INT; 1319 break; 1320 case MPF_RAS_ERR: 1321 err = mpf_ras_err_tbl; 1322 opcode = HNS3_OPC_QUERY_CLEAR_MPF_RAS_INT; 1323 break; 1324 case PF_RAS_ERR: 1325 err = pf_ras_err_tbl; 1326 opcode = HNS3_OPC_QUERY_CLEAR_PF_RAS_INT; 1327 break; 1328 default: 1329 hns3_err(hw, "error hardware err_type = %d\n", err_type); 1330 return -EINVAL; 1331 } 1332 1333 /* query all hardware errors */ 1334 hns3_cmd_setup_basic_desc(&desc[0], opcode, true); 1335 ret = hns3_cmd_send(hw, &desc[0], num); 1336 if (ret) { 1337 hns3_err(hw, "query hw err int 0x%x cmd failed, ret = %d\n", 1338 opcode, ret); 1339 return ret; 1340 } 1341 1342 /* traverses the error table and process based on the error type */ 1343 while (err->msg) { 1344 status = hns3_get_hw_error_status(desc, err->desc_offset, 1345 err->data_offset); 1346 if (status) { 1347 /* 1348 * set the reset_level or non_reset flag based on 1349 * the error type and add error statistics. here just 1350 * set the flag, the actual reset action is in 1351 * hns3_msix_process. 1352 */ 1353 req_level = hns3_find_highest_level(hns, err->msg, 1354 err->hw_err, 1355 status); 1356 hns3_atomic_set_bit(req_level, levels); 1357 } 1358 err++; 1359 } 1360 1361 /* clear all hardware errors */ 1362 hns3_cmd_reuse_desc(&desc[0], false); 1363 ret = hns3_cmd_send(hw, &desc[0], num); 1364 if (ret) 1365 hns3_err(hw, "clear all hw err int cmd failed, ret = %d\n", 1366 ret); 1367 1368 return ret; 1369 } 1370 1371 void 1372 hns3_handle_msix_error(struct hns3_adapter *hns, uint64_t *levels) 1373 { 1374 uint32_t mpf_bd_num, pf_bd_num, bd_num; 1375 struct hns3_hw *hw = &hns->hw; 1376 struct hns3_cmd_desc *desc; 1377 int ret; 1378 1379 /* query the number of bds for the MSIx int status */ 1380 ret = query_num_bds(hw, false, &mpf_bd_num, &pf_bd_num); 1381 if (ret) { 1382 hns3_err(hw, "fail to query msix int status bd num: ret = %d", 1383 ret); 1384 return; 1385 } 1386 1387 bd_num = RTE_MAX(mpf_bd_num, pf_bd_num); 1388 desc = rte_zmalloc(NULL, bd_num * sizeof(struct hns3_cmd_desc), 0); 1389 if (desc == NULL) { 1390 hns3_err(hw, 1391 "fail to zmalloc desc for handling msix error, size = %zu", 1392 bd_num * sizeof(struct hns3_cmd_desc)); 1393 return; 1394 } 1395 1396 /* handle all main PF MSIx errors */ 1397 ret = hns3_handle_hw_error(hns, desc, mpf_bd_num, levels, MPF_MSIX_ERR); 1398 if (ret) { 1399 hns3_err(hw, "fail to handle all main pf msix errors, ret = %d", 1400 ret); 1401 goto out; 1402 } 1403 1404 memset(desc, 0, bd_num * sizeof(struct hns3_cmd_desc)); 1405 1406 /* handle all PF MSIx errors */ 1407 ret = hns3_handle_hw_error(hns, desc, pf_bd_num, levels, PF_MSIX_ERR); 1408 if (ret) { 1409 hns3_err(hw, "fail to handle all pf msix errors, ret = %d", 1410 ret); 1411 goto out; 1412 } 1413 1414 out: 1415 rte_free(desc); 1416 } 1417 1418 void 1419 hns3_handle_ras_error(struct hns3_adapter *hns, uint64_t *levels) 1420 { 1421 uint32_t mpf_bd_num, pf_bd_num, bd_num; 1422 struct hns3_hw *hw = &hns->hw; 1423 struct hns3_cmd_desc *desc; 1424 uint32_t status; 1425 int ret; 1426 1427 status = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG); 1428 if ((status & HNS3_RAS_REG_NFE_MASK) == 0) 1429 return; 1430 1431 /* query the number of bds for the RAS int status */ 1432 ret = query_num_bds(hw, true, &mpf_bd_num, &pf_bd_num); 1433 if (ret) { 1434 hns3_err(hw, "fail to query ras int status bd num: ret = %d", 1435 ret); 1436 return; 1437 } 1438 1439 bd_num = RTE_MAX(mpf_bd_num, pf_bd_num); 1440 desc = rte_zmalloc(NULL, bd_num * sizeof(struct hns3_cmd_desc), 0); 1441 if (desc == NULL) { 1442 hns3_err(hw, 1443 "fail to zmalloc desc for handing ras error, size = %zu", 1444 bd_num * sizeof(struct hns3_cmd_desc)); 1445 return; 1446 } 1447 1448 /* handle all main PF RAS errors */ 1449 ret = hns3_handle_hw_error(hns, desc, mpf_bd_num, levels, MPF_RAS_ERR); 1450 if (ret) { 1451 hns3_err(hw, "fail to handle all main pf ras errors, ret = %d", 1452 ret); 1453 goto out; 1454 } 1455 1456 memset(desc, 0, bd_num * sizeof(struct hns3_cmd_desc)); 1457 1458 /* handle all PF RAS errors */ 1459 ret = hns3_handle_hw_error(hns, desc, pf_bd_num, levels, PF_RAS_ERR); 1460 if (ret) { 1461 hns3_err(hw, "fail to handle all pf ras errors, ret = %d", ret); 1462 goto out; 1463 } 1464 1465 out: 1466 rte_free(desc); 1467 } 1468 1469 int 1470 hns3_reset_init(struct hns3_hw *hw) 1471 { 1472 rte_spinlock_init(&hw->lock); 1473 hw->reset.level = HNS3_NONE_RESET; 1474 hw->reset.stage = RESET_STAGE_NONE; 1475 hw->reset.request = 0; 1476 hw->reset.pending = 0; 1477 rte_atomic16_init(&hw->reset.resetting); 1478 rte_atomic16_init(&hw->reset.disable_cmd); 1479 hw->reset.wait_data = rte_zmalloc("wait_data", 1480 sizeof(struct hns3_wait_data), 0); 1481 if (!hw->reset.wait_data) { 1482 PMD_INIT_LOG(ERR, "Failed to allocate memory for wait_data"); 1483 return -ENOMEM; 1484 } 1485 return 0; 1486 } 1487 1488 void 1489 hns3_schedule_reset(struct hns3_adapter *hns) 1490 { 1491 struct hns3_hw *hw = &hns->hw; 1492 1493 /* Reschedule the reset process after successful initialization */ 1494 if (hw->adapter_state == HNS3_NIC_UNINITIALIZED) { 1495 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_PENDING); 1496 return; 1497 } 1498 1499 if (hw->adapter_state >= HNS3_NIC_CLOSED) 1500 return; 1501 1502 /* Schedule restart alarm if it is not scheduled yet */ 1503 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_REQUESTED) 1504 return; 1505 if (rte_atomic16_read(&hns->hw.reset.schedule) == SCHEDULE_DEFERRED) 1506 rte_eal_alarm_cancel(hw->reset.ops->reset_service, hns); 1507 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_REQUESTED); 1508 1509 rte_eal_alarm_set(SWITCH_CONTEXT_US, hw->reset.ops->reset_service, hns); 1510 } 1511 1512 void 1513 hns3_schedule_delayed_reset(struct hns3_adapter *hns) 1514 { 1515 #define DEFERRED_SCHED_US (3 * MSEC_PER_SEC * USEC_PER_MSEC) 1516 struct hns3_hw *hw = &hns->hw; 1517 1518 /* Do nothing if it is uninited or closed */ 1519 if (hw->adapter_state == HNS3_NIC_UNINITIALIZED || 1520 hw->adapter_state >= HNS3_NIC_CLOSED) { 1521 return; 1522 } 1523 1524 if (rte_atomic16_read(&hns->hw.reset.schedule) != SCHEDULE_NONE) 1525 return; 1526 rte_atomic16_set(&hns->hw.reset.schedule, SCHEDULE_DEFERRED); 1527 rte_eal_alarm_set(DEFERRED_SCHED_US, hw->reset.ops->reset_service, hns); 1528 } 1529 1530 void 1531 hns3_wait_callback(void *param) 1532 { 1533 struct hns3_wait_data *data = (struct hns3_wait_data *)param; 1534 struct hns3_adapter *hns = data->hns; 1535 struct hns3_hw *hw = &hns->hw; 1536 uint64_t msec; 1537 bool done; 1538 1539 data->count--; 1540 if (data->check_completion) { 1541 /* 1542 * Check if the current time exceeds the deadline 1543 * or a pending reset coming, or reset during close. 1544 */ 1545 msec = get_timeofday_ms(); 1546 if (msec > data->end_ms || is_reset_pending(hns) || 1547 hw->adapter_state == HNS3_NIC_CLOSING) { 1548 done = false; 1549 data->count = 0; 1550 } else 1551 done = data->check_completion(hw); 1552 } else 1553 done = true; 1554 1555 if (!done && data->count > 0) { 1556 rte_eal_alarm_set(data->interval, hns3_wait_callback, data); 1557 return; 1558 } 1559 if (done) 1560 data->result = HNS3_WAIT_SUCCESS; 1561 else { 1562 hns3_err(hw, "%s wait timeout at stage %d", 1563 reset_string[hw->reset.level], hw->reset.stage); 1564 data->result = HNS3_WAIT_TIMEOUT; 1565 } 1566 hns3_schedule_reset(hns); 1567 } 1568 1569 void 1570 hns3_notify_reset_ready(struct hns3_hw *hw, bool enable) 1571 { 1572 uint32_t reg_val; 1573 1574 reg_val = hns3_read_dev(hw, HNS3_CMDQ_TX_DEPTH_REG); 1575 if (enable) 1576 reg_val |= HNS3_NIC_SW_RST_RDY; 1577 else 1578 reg_val &= ~HNS3_NIC_SW_RST_RDY; 1579 1580 hns3_write_dev(hw, HNS3_CMDQ_TX_DEPTH_REG, reg_val); 1581 } 1582 1583 int 1584 hns3_reset_req_hw_reset(struct hns3_adapter *hns) 1585 { 1586 struct hns3_hw *hw = &hns->hw; 1587 1588 if (hw->reset.wait_data->result == HNS3_WAIT_UNKNOWN) { 1589 hw->reset.wait_data->hns = hns; 1590 hw->reset.wait_data->check_completion = NULL; 1591 hw->reset.wait_data->interval = HNS3_RESET_SYNC_US; 1592 hw->reset.wait_data->count = 1; 1593 hw->reset.wait_data->result = HNS3_WAIT_REQUEST; 1594 rte_eal_alarm_set(hw->reset.wait_data->interval, 1595 hns3_wait_callback, hw->reset.wait_data); 1596 return -EAGAIN; 1597 } else if (hw->reset.wait_data->result == HNS3_WAIT_REQUEST) 1598 return -EAGAIN; 1599 1600 /* inform hardware that preparatory work is done */ 1601 hns3_notify_reset_ready(hw, true); 1602 return 0; 1603 } 1604 1605 static void 1606 hns3_clear_reset_level(struct hns3_hw *hw, uint64_t *levels) 1607 { 1608 uint64_t merge_cnt = hw->reset.stats.merge_cnt; 1609 int64_t tmp; 1610 1611 switch (hw->reset.level) { 1612 case HNS3_IMP_RESET: 1613 hns3_atomic_clear_bit(HNS3_IMP_RESET, levels); 1614 tmp = hns3_test_and_clear_bit(HNS3_GLOBAL_RESET, levels); 1615 HNS3_CHECK_MERGE_CNT(tmp); 1616 tmp = hns3_test_and_clear_bit(HNS3_FUNC_RESET, levels); 1617 HNS3_CHECK_MERGE_CNT(tmp); 1618 break; 1619 case HNS3_GLOBAL_RESET: 1620 hns3_atomic_clear_bit(HNS3_GLOBAL_RESET, levels); 1621 tmp = hns3_test_and_clear_bit(HNS3_FUNC_RESET, levels); 1622 HNS3_CHECK_MERGE_CNT(tmp); 1623 break; 1624 case HNS3_FUNC_RESET: 1625 hns3_atomic_clear_bit(HNS3_FUNC_RESET, levels); 1626 break; 1627 case HNS3_VF_RESET: 1628 hns3_atomic_clear_bit(HNS3_VF_RESET, levels); 1629 tmp = hns3_test_and_clear_bit(HNS3_VF_PF_FUNC_RESET, levels); 1630 HNS3_CHECK_MERGE_CNT(tmp); 1631 tmp = hns3_test_and_clear_bit(HNS3_VF_FUNC_RESET, levels); 1632 HNS3_CHECK_MERGE_CNT(tmp); 1633 break; 1634 case HNS3_VF_FULL_RESET: 1635 hns3_atomic_clear_bit(HNS3_VF_FULL_RESET, levels); 1636 tmp = hns3_test_and_clear_bit(HNS3_VF_FUNC_RESET, levels); 1637 HNS3_CHECK_MERGE_CNT(tmp); 1638 break; 1639 case HNS3_VF_PF_FUNC_RESET: 1640 hns3_atomic_clear_bit(HNS3_VF_PF_FUNC_RESET, levels); 1641 tmp = hns3_test_and_clear_bit(HNS3_VF_FUNC_RESET, levels); 1642 HNS3_CHECK_MERGE_CNT(tmp); 1643 break; 1644 case HNS3_VF_FUNC_RESET: 1645 hns3_atomic_clear_bit(HNS3_VF_FUNC_RESET, levels); 1646 break; 1647 case HNS3_FLR_RESET: 1648 hns3_atomic_clear_bit(HNS3_FLR_RESET, levels); 1649 break; 1650 case HNS3_NONE_RESET: 1651 default: 1652 return; 1653 }; 1654 if (merge_cnt != hw->reset.stats.merge_cnt) 1655 hns3_warn(hw, 1656 "No need to do low-level reset after %s reset. " 1657 "merge cnt: %" PRIx64 " total merge cnt: %" PRIx64, 1658 reset_string[hw->reset.level], 1659 hw->reset.stats.merge_cnt - merge_cnt, 1660 hw->reset.stats.merge_cnt); 1661 } 1662 1663 static bool 1664 hns3_reset_err_handle(struct hns3_adapter *hns) 1665 { 1666 #define MAX_RESET_FAIL_CNT 5 1667 1668 struct hns3_hw *hw = &hns->hw; 1669 1670 if (hw->adapter_state == HNS3_NIC_CLOSING) 1671 goto reset_fail; 1672 1673 if (is_reset_pending(hns)) { 1674 hw->reset.attempts = 0; 1675 hw->reset.stats.fail_cnt++; 1676 hns3_warn(hw, "%s reset fail because new Reset is pending " 1677 "attempts:%" PRIx64, 1678 reset_string[hw->reset.level], 1679 hw->reset.stats.fail_cnt); 1680 hw->reset.level = HNS3_NONE_RESET; 1681 return true; 1682 } 1683 1684 hw->reset.attempts++; 1685 if (hw->reset.attempts < MAX_RESET_FAIL_CNT) { 1686 hns3_atomic_set_bit(hw->reset.level, &hw->reset.pending); 1687 hns3_warn(hw, "%s retry to reset attempts: %d", 1688 reset_string[hw->reset.level], 1689 hw->reset.attempts); 1690 return true; 1691 } 1692 1693 /* 1694 * Failure to reset does not mean that the network port is 1695 * completely unavailable, so cmd still needs to be initialized. 1696 * Regardless of whether the execution is successful or not, the 1697 * flow after execution must be continued. 1698 */ 1699 if (rte_atomic16_read(&hw->reset.disable_cmd)) 1700 (void)hns3_cmd_init(hw); 1701 reset_fail: 1702 hw->reset.attempts = 0; 1703 hw->reset.stats.fail_cnt++; 1704 hns3_warn(hw, "%s reset fail fail_cnt:%" PRIx64 " success_cnt:%" PRIx64 1705 " global_cnt:%" PRIx64 " imp_cnt:%" PRIx64 1706 " request_cnt:%" PRIx64 " exec_cnt:%" PRIx64 1707 " merge_cnt:%" PRIx64 "adapter_state:%d", 1708 reset_string[hw->reset.level], hw->reset.stats.fail_cnt, 1709 hw->reset.stats.success_cnt, hw->reset.stats.global_cnt, 1710 hw->reset.stats.imp_cnt, hw->reset.stats.request_cnt, 1711 hw->reset.stats.exec_cnt, hw->reset.stats.merge_cnt, 1712 hw->adapter_state); 1713 1714 /* IMP no longer waiting the ready flag */ 1715 hns3_notify_reset_ready(hw, true); 1716 return false; 1717 } 1718 1719 static int 1720 hns3_reset_pre(struct hns3_adapter *hns) 1721 { 1722 struct hns3_hw *hw = &hns->hw; 1723 struct timeval tv; 1724 int ret; 1725 1726 if (hw->reset.stage == RESET_STAGE_NONE) { 1727 rte_atomic16_set(&hns->hw.reset.resetting, 1); 1728 hw->reset.stage = RESET_STAGE_DOWN; 1729 ret = hw->reset.ops->stop_service(hns); 1730 gettimeofday(&tv, NULL); 1731 if (ret) { 1732 hns3_warn(hw, "Reset step1 down fail=%d time=%ld.%.6ld", 1733 ret, tv.tv_sec, tv.tv_usec); 1734 return ret; 1735 } 1736 hns3_warn(hw, "Reset step1 down success time=%ld.%.6ld", 1737 tv.tv_sec, tv.tv_usec); 1738 hw->reset.stage = RESET_STAGE_PREWAIT; 1739 } 1740 if (hw->reset.stage == RESET_STAGE_PREWAIT) { 1741 ret = hw->reset.ops->prepare_reset(hns); 1742 gettimeofday(&tv, NULL); 1743 if (ret) { 1744 hns3_warn(hw, 1745 "Reset step2 prepare wait fail=%d time=%ld.%.6ld", 1746 ret, tv.tv_sec, tv.tv_usec); 1747 return ret; 1748 } 1749 hns3_warn(hw, "Reset step2 prepare wait success time=%ld.%.6ld", 1750 tv.tv_sec, tv.tv_usec); 1751 hw->reset.stage = RESET_STAGE_REQ_HW_RESET; 1752 hw->reset.wait_data->result = HNS3_WAIT_UNKNOWN; 1753 } 1754 return 0; 1755 } 1756 1757 static int 1758 hns3_reset_post(struct hns3_adapter *hns) 1759 { 1760 #define TIMEOUT_RETRIES_CNT 5 1761 struct hns3_hw *hw = &hns->hw; 1762 struct timeval tv_delta; 1763 struct timeval tv; 1764 int ret = 0; 1765 1766 if (hw->adapter_state == HNS3_NIC_CLOSING) { 1767 hns3_warn(hw, "Don't do reset_post during closing, just uninit cmd"); 1768 hns3_cmd_uninit(hw); 1769 return -EPERM; 1770 } 1771 1772 if (hw->reset.stage == RESET_STAGE_DEV_INIT) { 1773 rte_spinlock_lock(&hw->lock); 1774 if (hw->reset.mbuf_deferred_free) { 1775 hns3_dev_release_mbufs(hns); 1776 hw->reset.mbuf_deferred_free = false; 1777 } 1778 ret = hw->reset.ops->reinit_dev(hns); 1779 rte_spinlock_unlock(&hw->lock); 1780 gettimeofday(&tv, NULL); 1781 if (ret) { 1782 hns3_warn(hw, "Reset step5 devinit fail=%d retries=%d", 1783 ret, hw->reset.retries); 1784 goto err; 1785 } 1786 hns3_warn(hw, "Reset step5 devinit success time=%ld.%.6ld", 1787 tv.tv_sec, tv.tv_usec); 1788 hw->reset.retries = 0; 1789 hw->reset.stage = RESET_STAGE_RESTORE; 1790 rte_eal_alarm_set(SWITCH_CONTEXT_US, 1791 hw->reset.ops->reset_service, hns); 1792 return -EAGAIN; 1793 } 1794 if (hw->reset.stage == RESET_STAGE_RESTORE) { 1795 rte_spinlock_lock(&hw->lock); 1796 ret = hw->reset.ops->restore_conf(hns); 1797 rte_spinlock_unlock(&hw->lock); 1798 gettimeofday(&tv, NULL); 1799 if (ret) { 1800 hns3_warn(hw, 1801 "Reset step6 restore fail=%d retries=%d", 1802 ret, hw->reset.retries); 1803 goto err; 1804 } 1805 hns3_warn(hw, "Reset step6 restore success time=%ld.%.6ld", 1806 tv.tv_sec, tv.tv_usec); 1807 hw->reset.retries = 0; 1808 hw->reset.stage = RESET_STAGE_DONE; 1809 } 1810 if (hw->reset.stage == RESET_STAGE_DONE) { 1811 /* IMP will wait ready flag before reset */ 1812 hns3_notify_reset_ready(hw, false); 1813 hns3_clear_reset_level(hw, &hw->reset.pending); 1814 rte_atomic16_clear(&hns->hw.reset.resetting); 1815 hw->reset.attempts = 0; 1816 hw->reset.stats.success_cnt++; 1817 hw->reset.stage = RESET_STAGE_NONE; 1818 rte_spinlock_lock(&hw->lock); 1819 hw->reset.ops->start_service(hns); 1820 rte_spinlock_unlock(&hw->lock); 1821 gettimeofday(&tv, NULL); 1822 timersub(&tv, &hw->reset.start_time, &tv_delta); 1823 hns3_warn(hw, "%s reset done fail_cnt:%" PRIx64 1824 " success_cnt:%" PRIx64 " global_cnt:%" PRIx64 1825 " imp_cnt:%" PRIx64 " request_cnt:%" PRIx64 1826 " exec_cnt:%" PRIx64 " merge_cnt:%" PRIx64, 1827 reset_string[hw->reset.level], 1828 hw->reset.stats.fail_cnt, hw->reset.stats.success_cnt, 1829 hw->reset.stats.global_cnt, hw->reset.stats.imp_cnt, 1830 hw->reset.stats.request_cnt, hw->reset.stats.exec_cnt, 1831 hw->reset.stats.merge_cnt); 1832 hns3_warn(hw, 1833 "%s reset done delta %ld ms time=%ld.%.6ld", 1834 reset_string[hw->reset.level], 1835 tv_delta.tv_sec * MSEC_PER_SEC + 1836 tv_delta.tv_usec / USEC_PER_MSEC, 1837 tv.tv_sec, tv.tv_usec); 1838 hw->reset.level = HNS3_NONE_RESET; 1839 } 1840 return 0; 1841 1842 err: 1843 if (ret == -ETIME) { 1844 hw->reset.retries++; 1845 if (hw->reset.retries < TIMEOUT_RETRIES_CNT) { 1846 rte_eal_alarm_set(HNS3_RESET_SYNC_US, 1847 hw->reset.ops->reset_service, hns); 1848 return -EAGAIN; 1849 } 1850 } 1851 hw->reset.retries = 0; 1852 return -EIO; 1853 } 1854 1855 /* 1856 * There are three scenarios as follows: 1857 * When the reset is not in progress, the reset process starts. 1858 * During the reset process, if the reset level has not changed, 1859 * the reset process continues; otherwise, the reset process is aborted. 1860 * hw->reset.level new_level action 1861 * HNS3_NONE_RESET HNS3_XXXX_RESET start reset 1862 * HNS3_XXXX_RESET HNS3_XXXX_RESET continue reset 1863 * HNS3_LOW_RESET HNS3_HIGH_RESET abort 1864 */ 1865 int 1866 hns3_reset_process(struct hns3_adapter *hns, enum hns3_reset_level new_level) 1867 { 1868 struct hns3_hw *hw = &hns->hw; 1869 struct timeval tv_delta; 1870 struct timeval tv; 1871 int ret; 1872 1873 if (hw->reset.level == HNS3_NONE_RESET) { 1874 hw->reset.level = new_level; 1875 hw->reset.stats.exec_cnt++; 1876 gettimeofday(&hw->reset.start_time, NULL); 1877 hns3_warn(hw, "Start %s reset time=%ld.%.6ld", 1878 reset_string[hw->reset.level], 1879 hw->reset.start_time.tv_sec, 1880 hw->reset.start_time.tv_usec); 1881 } 1882 1883 if (is_reset_pending(hns)) { 1884 gettimeofday(&tv, NULL); 1885 hns3_warn(hw, 1886 "%s reset is aborted by high level time=%ld.%.6ld", 1887 reset_string[hw->reset.level], tv.tv_sec, tv.tv_usec); 1888 if (hw->reset.wait_data->result == HNS3_WAIT_REQUEST) 1889 rte_eal_alarm_cancel(hns3_wait_callback, 1890 hw->reset.wait_data); 1891 ret = -EBUSY; 1892 goto err; 1893 } 1894 1895 ret = hns3_reset_pre(hns); 1896 if (ret) 1897 goto err; 1898 1899 if (hw->reset.stage == RESET_STAGE_REQ_HW_RESET) { 1900 ret = hns3_reset_req_hw_reset(hns); 1901 if (ret == -EAGAIN) 1902 return ret; 1903 gettimeofday(&tv, NULL); 1904 hns3_warn(hw, 1905 "Reset step3 request IMP reset success time=%ld.%.6ld", 1906 tv.tv_sec, tv.tv_usec); 1907 hw->reset.stage = RESET_STAGE_WAIT; 1908 hw->reset.wait_data->result = HNS3_WAIT_UNKNOWN; 1909 } 1910 if (hw->reset.stage == RESET_STAGE_WAIT) { 1911 ret = hw->reset.ops->wait_hardware_ready(hns); 1912 if (ret) 1913 goto retry; 1914 gettimeofday(&tv, NULL); 1915 hns3_warn(hw, "Reset step4 reset wait success time=%ld.%.6ld", 1916 tv.tv_sec, tv.tv_usec); 1917 hw->reset.stage = RESET_STAGE_DEV_INIT; 1918 } 1919 1920 ret = hns3_reset_post(hns); 1921 if (ret) 1922 goto retry; 1923 1924 return 0; 1925 retry: 1926 if (ret == -EAGAIN) 1927 return ret; 1928 err: 1929 hns3_clear_reset_level(hw, &hw->reset.pending); 1930 if (hns3_reset_err_handle(hns)) { 1931 hw->reset.stage = RESET_STAGE_PREWAIT; 1932 hns3_schedule_reset(hns); 1933 } else { 1934 rte_spinlock_lock(&hw->lock); 1935 if (hw->reset.mbuf_deferred_free) { 1936 hns3_dev_release_mbufs(hns); 1937 hw->reset.mbuf_deferred_free = false; 1938 } 1939 rte_spinlock_unlock(&hw->lock); 1940 rte_atomic16_clear(&hns->hw.reset.resetting); 1941 hw->reset.stage = RESET_STAGE_NONE; 1942 gettimeofday(&tv, NULL); 1943 timersub(&tv, &hw->reset.start_time, &tv_delta); 1944 hns3_warn(hw, "%s reset fail delta %ld ms time=%ld.%.6ld", 1945 reset_string[hw->reset.level], 1946 tv_delta.tv_sec * MSEC_PER_SEC + 1947 tv_delta.tv_usec / USEC_PER_MSEC, 1948 tv.tv_sec, tv.tv_usec); 1949 hw->reset.level = HNS3_NONE_RESET; 1950 } 1951 1952 return -EIO; 1953 } 1954 1955 /* 1956 * The reset process can only be terminated after handshake with IMP(step3), 1957 * so that IMP can complete the reset process normally. 1958 */ 1959 void 1960 hns3_reset_abort(struct hns3_adapter *hns) 1961 { 1962 struct hns3_hw *hw = &hns->hw; 1963 struct timeval tv; 1964 int i; 1965 1966 for (i = 0; i < HNS3_QUIT_RESET_CNT; i++) { 1967 if (hw->reset.level == HNS3_NONE_RESET) 1968 break; 1969 rte_delay_ms(HNS3_QUIT_RESET_DELAY_MS); 1970 } 1971 1972 /* IMP no longer waiting the ready flag */ 1973 hns3_notify_reset_ready(hw, true); 1974 1975 rte_eal_alarm_cancel(hw->reset.ops->reset_service, hns); 1976 rte_eal_alarm_cancel(hns3_wait_callback, hw->reset.wait_data); 1977 1978 if (hw->reset.level != HNS3_NONE_RESET) { 1979 gettimeofday(&tv, NULL); 1980 hns3_err(hw, "Failed to terminate reset: %s time=%ld.%.6ld", 1981 reset_string[hw->reset.level], tv.tv_sec, tv.tv_usec); 1982 } 1983 } 1984