1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018-2019 Hisilicon Limited. 3 */ 4 5 #include <rte_alarm.h> 6 #include <rte_cycles.h> 7 #include <rte_ethdev.h> 8 #include <rte_io.h> 9 #include <rte_malloc.h> 10 11 #include "hns3_ethdev.h" 12 #include "hns3_logs.h" 13 #include "hns3_intr.h" 14 #include "hns3_regs.h" 15 #include "hns3_rxtx.h" 16 17 #define SWITCH_CONTEXT_US 10 18 19 #define HNS3_CHECK_MERGE_CNT(val) \ 20 do { \ 21 if (val) \ 22 hw->reset.stats.merge_cnt++; \ 23 } while (0) 24 25 static const char *reset_string[HNS3_MAX_RESET] = { 26 "none", "vf_func", "vf_pf_func", "vf_full", "flr", 27 "vf_global", "pf_func", "global", "IMP", 28 }; 29 30 static const struct hns3_hw_error mac_afifo_tnl_int[] = { 31 { 32 .int_msk = BIT(0), 33 .msg = "egu_cge_afifo_ecc_1bit_err", 34 .reset_level = HNS3_NONE_RESET 35 }, { 36 .int_msk = BIT(1), 37 .msg = "egu_cge_afifo_ecc_mbit_err", 38 .reset_level = HNS3_GLOBAL_RESET 39 }, { 40 .int_msk = BIT(2), 41 .msg = "egu_lge_afifo_ecc_1bit_err", 42 .reset_level = HNS3_NONE_RESET 43 }, { 44 .int_msk = BIT(3), 45 .msg = "egu_lge_afifo_ecc_mbit_err", 46 .reset_level = HNS3_GLOBAL_RESET 47 }, { 48 .int_msk = BIT(4), 49 .msg = "cge_igu_afifo_ecc_1bit_err", 50 .reset_level = HNS3_NONE_RESET 51 }, { 52 .int_msk = BIT(5), 53 .msg = "cge_igu_afifo_ecc_mbit_err", 54 .reset_level = HNS3_GLOBAL_RESET 55 }, { 56 .int_msk = BIT(6), 57 .msg = "lge_igu_afifo_ecc_1bit_err", 58 .reset_level = HNS3_NONE_RESET 59 }, { 60 .int_msk = BIT(7), 61 .msg = "lge_igu_afifo_ecc_mbit_err", 62 .reset_level = HNS3_GLOBAL_RESET 63 }, { 64 .int_msk = BIT(8), 65 .msg = "cge_igu_afifo_overflow_err", 66 .reset_level = HNS3_GLOBAL_RESET 67 }, { 68 .int_msk = BIT(9), 69 .msg = "lge_igu_afifo_overflow_err", 70 .reset_level = HNS3_GLOBAL_RESET 71 }, { 72 .int_msk = BIT(10), 73 .msg = "egu_cge_afifo_underrun_err", 74 .reset_level = HNS3_GLOBAL_RESET 75 }, { 76 .int_msk = BIT(11), 77 .msg = "egu_lge_afifo_underrun_err", 78 .reset_level = HNS3_GLOBAL_RESET 79 }, { 80 .int_msk = BIT(12), 81 .msg = "egu_ge_afifo_underrun_err", 82 .reset_level = HNS3_GLOBAL_RESET 83 }, { 84 .int_msk = BIT(13), 85 .msg = "ge_igu_afifo_overflow_err", 86 .reset_level = HNS3_GLOBAL_RESET 87 }, { 88 .int_msk = 0, 89 .msg = NULL, 90 .reset_level = HNS3_NONE_RESET 91 } 92 }; 93 94 static const struct hns3_hw_error ppu_mpf_abnormal_int_st1[] = { 95 { 96 .int_msk = 0xFFFFFFFF, 97 .msg = "rpu_rx_pkt_ecc_mbit_err", 98 .reset_level = HNS3_GLOBAL_RESET 99 }, { 100 .int_msk = 0, 101 .msg = NULL, 102 .reset_level = HNS3_NONE_RESET 103 } 104 }; 105 106 static const struct hns3_hw_error ppu_mpf_abnormal_int_st2_ras[] = { 107 { 108 .int_msk = BIT(13), 109 .msg = "rpu_rx_pkt_bit32_ecc_mbit_err", 110 .reset_level = HNS3_GLOBAL_RESET 111 }, { 112 .int_msk = BIT(14), 113 .msg = "rpu_rx_pkt_bit33_ecc_mbit_err", 114 .reset_level = HNS3_GLOBAL_RESET 115 }, { 116 .int_msk = BIT(15), 117 .msg = "rpu_rx_pkt_bit34_ecc_mbit_err", 118 .reset_level = HNS3_GLOBAL_RESET 119 }, { 120 .int_msk = BIT(16), 121 .msg = "rpu_rx_pkt_bit35_ecc_mbit_err", 122 .reset_level = HNS3_GLOBAL_RESET 123 }, { 124 .int_msk = BIT(17), 125 .msg = "rcb_tx_ring_ecc_mbit_err", 126 .reset_level = HNS3_GLOBAL_RESET 127 }, { 128 .int_msk = BIT(18), 129 .msg = "rcb_rx_ring_ecc_mbit_err", 130 .reset_level = HNS3_GLOBAL_RESET 131 }, { 132 .int_msk = BIT(19), 133 .msg = "rcb_tx_fbd_ecc_mbit_err", 134 .reset_level = HNS3_GLOBAL_RESET 135 }, { 136 .int_msk = BIT(20), 137 .msg = "rcb_rx_ebd_ecc_mbit_err", 138 .reset_level = HNS3_GLOBAL_RESET 139 }, { 140 .int_msk = BIT(21), 141 .msg = "rcb_tso_info_ecc_mbit_err", 142 .reset_level = HNS3_GLOBAL_RESET 143 }, { 144 .int_msk = BIT(22), 145 .msg = "rcb_tx_int_info_ecc_mbit_err", 146 .reset_level = HNS3_GLOBAL_RESET 147 }, { 148 .int_msk = BIT(23), 149 .msg = "rcb_rx_int_info_ecc_mbit_err", 150 .reset_level = HNS3_GLOBAL_RESET 151 }, { 152 .int_msk = BIT(24), 153 .msg = "tpu_tx_pkt_0_ecc_mbit_err", 154 .reset_level = HNS3_GLOBAL_RESET 155 }, { 156 .int_msk = BIT(25), 157 .msg = "tpu_tx_pkt_1_ecc_mbit_err", 158 .reset_level = HNS3_GLOBAL_RESET 159 }, { 160 .int_msk = BIT(26), 161 .msg = "rd_bus_err", 162 .reset_level = HNS3_GLOBAL_RESET 163 }, { 164 .int_msk = BIT(27), 165 .msg = "wr_bus_err", 166 .reset_level = HNS3_GLOBAL_RESET 167 }, { 168 .int_msk = BIT(30), 169 .msg = "ooo_ecc_err_detect", 170 .reset_level = HNS3_NONE_RESET 171 }, { 172 .int_msk = BIT(31), 173 .msg = "ooo_ecc_err_multpl", 174 .reset_level = HNS3_GLOBAL_RESET 175 }, { 176 .int_msk = 0, 177 .msg = NULL, 178 .reset_level = HNS3_NONE_RESET 179 } 180 }; 181 182 static const struct hns3_hw_error ppu_mpf_abnormal_int_st2_msix[] = { 183 { 184 .int_msk = BIT(29), 185 .msg = "rx_q_search_miss", 186 .reset_level = HNS3_NONE_RESET 187 }, { 188 .int_msk = 0, 189 .msg = NULL, 190 .reset_level = HNS3_NONE_RESET 191 } 192 }; 193 194 static const struct hns3_hw_error ssu_port_based_pf_int[] = { 195 { 196 .int_msk = BIT(0), 197 .msg = "roc_pkt_without_key_port", 198 .reset_level = HNS3_GLOBAL_RESET 199 }, { 200 .int_msk = BIT(9), 201 .msg = "low_water_line_err_port", 202 .reset_level = HNS3_NONE_RESET 203 }, { 204 .int_msk = 0, 205 .msg = NULL, 206 .reset_level = HNS3_NONE_RESET 207 } 208 }; 209 210 static const struct hns3_hw_error ppp_pf_abnormal_int[] = { 211 { 212 .int_msk = BIT(0), 213 .msg = "tx_vlan_tag_err", 214 .reset_level = HNS3_NONE_RESET 215 }, { 216 .int_msk = BIT(1), 217 .msg = "rss_list_tc_unassigned_queue_err", 218 .reset_level = HNS3_NONE_RESET 219 }, { 220 .int_msk = 0, 221 .msg = NULL, 222 .reset_level = HNS3_NONE_RESET 223 } 224 }; 225 226 static const struct hns3_hw_error ppu_pf_abnormal_int_ras[] = { 227 { 228 .int_msk = BIT(3), 229 .msg = "tx_rd_fbd_poison", 230 .reset_level = HNS3_FUNC_RESET 231 }, { 232 .int_msk = BIT(4), 233 .msg = "rx_rd_ebd_poison", 234 .reset_level = HNS3_FUNC_RESET 235 }, { 236 .int_msk = 0, 237 .msg = NULL, 238 .reset_level = HNS3_NONE_RESET 239 } 240 }; 241 242 static const struct hns3_hw_error ppu_pf_abnormal_int_msix[] = { 243 { 244 .int_msk = BIT(0), 245 .msg = "over_8bd_no_fe", 246 .reset_level = HNS3_FUNC_RESET 247 }, { 248 .int_msk = BIT(1), 249 .msg = "tso_mss_cmp_min_err", 250 .reset_level = HNS3_NONE_RESET 251 }, { 252 .int_msk = BIT(2), 253 .msg = "tso_mss_cmp_max_err", 254 .reset_level = HNS3_NONE_RESET 255 }, { 256 .int_msk = BIT(5), 257 .msg = "buf_wait_timeout", 258 .reset_level = HNS3_NONE_RESET 259 }, { 260 .int_msk = 0, 261 .msg = NULL, 262 .reset_level = HNS3_NONE_RESET 263 } 264 }; 265 266 static const struct hns3_hw_error imp_tcm_ecc_int[] = { 267 { 268 .int_msk = BIT(1), 269 .msg = "imp_itcm0_ecc_mbit_err", 270 .reset_level = HNS3_NONE_RESET 271 }, { 272 .int_msk = BIT(3), 273 .msg = "imp_itcm1_ecc_mbit_err", 274 .reset_level = HNS3_NONE_RESET 275 }, { 276 .int_msk = BIT(5), 277 .msg = "imp_itcm2_ecc_mbit_err", 278 .reset_level = HNS3_NONE_RESET 279 }, { 280 .int_msk = BIT(7), 281 .msg = "imp_itcm3_ecc_mbit_err", 282 .reset_level = HNS3_NONE_RESET 283 }, { 284 .int_msk = BIT(9), 285 .msg = "imp_dtcm0_mem0_ecc_mbit_err", 286 .reset_level = HNS3_NONE_RESET 287 }, { 288 .int_msk = BIT(11), 289 .msg = "imp_dtcm0_mem1_ecc_mbit_err", 290 .reset_level = HNS3_NONE_RESET 291 }, { 292 .int_msk = BIT(13), 293 .msg = "imp_dtcm1_mem0_ecc_mbit_err", 294 .reset_level = HNS3_NONE_RESET 295 }, { 296 .int_msk = BIT(15), 297 .msg = "imp_dtcm1_mem1_ecc_mbit_err", 298 .reset_level = HNS3_NONE_RESET 299 }, { 300 .int_msk = BIT(17), 301 .msg = "imp_itcm4_ecc_mbit_err", 302 .reset_level = HNS3_NONE_RESET 303 }, { 304 .int_msk = 0, 305 .msg = NULL, 306 .reset_level = HNS3_NONE_RESET 307 } 308 }; 309 310 static const struct hns3_hw_error cmdq_mem_ecc_int[] = { 311 { 312 .int_msk = BIT(1), 313 .msg = "cmdq_nic_rx_depth_ecc_mbit_err", 314 .reset_level = HNS3_NONE_RESET 315 }, { 316 .int_msk = BIT(3), 317 .msg = "cmdq_nic_tx_depth_ecc_mbit_err", 318 .reset_level = HNS3_NONE_RESET 319 }, { 320 .int_msk = BIT(5), 321 .msg = "cmdq_nic_rx_tail_ecc_mbit_err", 322 .reset_level = HNS3_NONE_RESET 323 }, { 324 .int_msk = BIT(7), 325 .msg = "cmdq_nic_tx_tail_ecc_mbit_err", 326 .reset_level = HNS3_NONE_RESET 327 }, { 328 .int_msk = BIT(9), 329 .msg = "cmdq_nic_rx_head_ecc_mbit_err", 330 .reset_level = HNS3_NONE_RESET 331 }, { 332 .int_msk = BIT(11), 333 .msg = "cmdq_nic_tx_head_ecc_mbit_err", 334 .reset_level = HNS3_NONE_RESET 335 }, { 336 .int_msk = BIT(13), 337 .msg = "cmdq_nic_rx_addr_ecc_mbit_err", 338 .reset_level = HNS3_NONE_RESET 339 }, { 340 .int_msk = BIT(15), 341 .msg = "cmdq_nic_tx_addr_ecc_mbit_err", 342 .reset_level = HNS3_NONE_RESET 343 }, { 344 .int_msk = 0, 345 .msg = NULL, 346 .reset_level = HNS3_NONE_RESET 347 } 348 }; 349 350 static const struct hns3_hw_error tqp_int_ecc_int[] = { 351 { 352 .int_msk = BIT(6), 353 .msg = "tqp_int_cfg_even_ecc_mbit_err", 354 .reset_level = HNS3_NONE_RESET 355 }, { 356 .int_msk = BIT(7), 357 .msg = "tqp_int_cfg_odd_ecc_mbit_err", 358 .reset_level = HNS3_NONE_RESET 359 }, { 360 .int_msk = BIT(8), 361 .msg = "tqp_int_ctrl_even_ecc_mbit_err", 362 .reset_level = HNS3_NONE_RESET 363 }, { 364 .int_msk = BIT(9), 365 .msg = "tqp_int_ctrl_odd_ecc_mbit_err", 366 .reset_level = HNS3_NONE_RESET 367 }, { 368 .int_msk = BIT(10), 369 .msg = "tx_queue_scan_int_ecc_mbit_err", 370 .reset_level = HNS3_NONE_RESET 371 }, { 372 .int_msk = BIT(11), 373 .msg = "rx_queue_scan_int_ecc_mbit_err", 374 .reset_level = HNS3_NONE_RESET 375 }, { 376 .int_msk = 0, 377 .msg = NULL, 378 .reset_level = HNS3_NONE_RESET 379 } 380 }; 381 382 static const struct hns3_hw_error imp_rd_poison_int[] = { 383 { 384 .int_msk = BIT(0), 385 .msg = "imp_rd_poison_int", 386 .reset_level = HNS3_NONE_RESET 387 }, { 388 .int_msk = 0, 389 .msg = NULL, 390 .reset_level = HNS3_NONE_RESET 391 } 392 }; 393 394 #define HNS3_SSU_MEM_ECC_ERR(x) \ 395 { \ 396 .int_msk = BIT(x), \ 397 .msg = "ssu_mem" #x "_ecc_mbit_err", \ 398 .reset_level = HNS3_GLOBAL_RESET \ 399 } 400 401 static const struct hns3_hw_error ssu_ecc_multi_bit_int_0[] = { 402 HNS3_SSU_MEM_ECC_ERR(0), 403 HNS3_SSU_MEM_ECC_ERR(1), 404 HNS3_SSU_MEM_ECC_ERR(2), 405 HNS3_SSU_MEM_ECC_ERR(3), 406 HNS3_SSU_MEM_ECC_ERR(4), 407 HNS3_SSU_MEM_ECC_ERR(5), 408 HNS3_SSU_MEM_ECC_ERR(6), 409 HNS3_SSU_MEM_ECC_ERR(7), 410 HNS3_SSU_MEM_ECC_ERR(8), 411 HNS3_SSU_MEM_ECC_ERR(9), 412 HNS3_SSU_MEM_ECC_ERR(10), 413 HNS3_SSU_MEM_ECC_ERR(11), 414 HNS3_SSU_MEM_ECC_ERR(12), 415 HNS3_SSU_MEM_ECC_ERR(13), 416 HNS3_SSU_MEM_ECC_ERR(14), 417 HNS3_SSU_MEM_ECC_ERR(15), 418 HNS3_SSU_MEM_ECC_ERR(16), 419 HNS3_SSU_MEM_ECC_ERR(17), 420 HNS3_SSU_MEM_ECC_ERR(18), 421 HNS3_SSU_MEM_ECC_ERR(19), 422 HNS3_SSU_MEM_ECC_ERR(20), 423 HNS3_SSU_MEM_ECC_ERR(21), 424 HNS3_SSU_MEM_ECC_ERR(22), 425 HNS3_SSU_MEM_ECC_ERR(23), 426 HNS3_SSU_MEM_ECC_ERR(24), 427 HNS3_SSU_MEM_ECC_ERR(25), 428 HNS3_SSU_MEM_ECC_ERR(26), 429 HNS3_SSU_MEM_ECC_ERR(27), 430 HNS3_SSU_MEM_ECC_ERR(28), 431 HNS3_SSU_MEM_ECC_ERR(29), 432 HNS3_SSU_MEM_ECC_ERR(30), 433 HNS3_SSU_MEM_ECC_ERR(31), 434 { .int_msk = 0, 435 .msg = NULL, 436 .reset_level = HNS3_NONE_RESET} 437 }; 438 439 static const struct hns3_hw_error ssu_ecc_multi_bit_int_1[] = { 440 { 441 .int_msk = BIT(0), 442 .msg = "ssu_mem32_ecc_mbit_err", 443 .reset_level = HNS3_GLOBAL_RESET 444 }, { 445 .int_msk = 0, 446 .msg = NULL, 447 .reset_level = HNS3_NONE_RESET 448 } 449 }; 450 451 static const struct hns3_hw_error ssu_common_ecc_int[] = { 452 { 453 .int_msk = BIT(0), 454 .msg = "buf_sum_err", 455 .reset_level = HNS3_NONE_RESET 456 }, { 457 .int_msk = BIT(1), 458 .msg = "ppp_mb_num_err", 459 .reset_level = HNS3_NONE_RESET 460 }, { 461 .int_msk = BIT(2), 462 .msg = "ppp_mbid_err", 463 .reset_level = HNS3_GLOBAL_RESET 464 }, { 465 .int_msk = BIT(3), 466 .msg = "ppp_rlt_mac_err", 467 .reset_level = HNS3_GLOBAL_RESET 468 }, { 469 .int_msk = BIT(4), 470 .msg = "ppp_rlt_host_err", 471 .reset_level = HNS3_GLOBAL_RESET 472 }, { 473 .int_msk = BIT(5), 474 .msg = "cks_edit_position_err", 475 .reset_level = HNS3_GLOBAL_RESET 476 }, { 477 .int_msk = BIT(6), 478 .msg = "cks_edit_condition_err", 479 .reset_level = HNS3_GLOBAL_RESET 480 }, { 481 .int_msk = BIT(7), 482 .msg = "vlan_edit_condition_err", 483 .reset_level = HNS3_GLOBAL_RESET 484 }, { 485 .int_msk = BIT(8), 486 .msg = "vlan_num_ot_err", 487 .reset_level = HNS3_GLOBAL_RESET 488 }, { 489 .int_msk = BIT(9), 490 .msg = "vlan_num_in_err", 491 .reset_level = HNS3_GLOBAL_RESET 492 }, { 493 .int_msk = 0, 494 .msg = NULL, 495 .reset_level = HNS3_NONE_RESET 496 } 497 }; 498 499 static const struct hns3_hw_error igu_int[] = { 500 { 501 .int_msk = BIT(0), 502 .msg = "igu_rx_buf0_ecc_mbit_err", 503 .reset_level = HNS3_GLOBAL_RESET 504 }, { 505 .int_msk = BIT(2), 506 .msg = "igu_rx_buf1_ecc_mbit_err", 507 .reset_level = HNS3_GLOBAL_RESET 508 }, { 509 .int_msk = 0, 510 .msg = NULL, 511 .reset_level = HNS3_NONE_RESET 512 } 513 }; 514 515 static const struct hns3_hw_error msix_ecc_int[] = { 516 { 517 .int_msk = BIT(1), 518 .msg = "msix_nic_ecc_mbit_err", 519 .reset_level = HNS3_NONE_RESET 520 }, { 521 .int_msk = 0, 522 .msg = NULL, 523 .reset_level = HNS3_NONE_RESET 524 } 525 }; 526 527 static const struct hns3_hw_error ppp_mpf_abnormal_int_st1[] = { 528 { 529 .int_msk = BIT(0), 530 .msg = "vf_vlan_ad_mem_ecc_mbit_err", 531 .reset_level = HNS3_GLOBAL_RESET 532 }, { 533 .int_msk = BIT(1), 534 .msg = "umv_mcast_group_mem_ecc_mbit_err", 535 .reset_level = HNS3_GLOBAL_RESET 536 }, { 537 .int_msk = BIT(2), 538 .msg = "umv_key_mem0_ecc_mbit_err", 539 .reset_level = HNS3_GLOBAL_RESET 540 }, { 541 .int_msk = BIT(3), 542 .msg = "umv_key_mem1_ecc_mbit_err", 543 .reset_level = HNS3_GLOBAL_RESET 544 }, { 545 .int_msk = BIT(4), 546 .msg = "umv_key_mem2_ecc_mbit_err", 547 .reset_level = HNS3_GLOBAL_RESET 548 }, { 549 .int_msk = BIT(5), 550 .msg = "umv_key_mem3_ecc_mbit_err", 551 .reset_level = HNS3_GLOBAL_RESET 552 }, { 553 .int_msk = BIT(6), 554 .msg = "umv_ad_mem_ecc_mbit_err", 555 .reset_level = HNS3_GLOBAL_RESET 556 }, { 557 .int_msk = BIT(7), 558 .msg = "rss_tc_mode_mem_ecc_mbit_err", 559 .reset_level = HNS3_GLOBAL_RESET 560 }, { 561 .int_msk = BIT(8), 562 .msg = "rss_idt_mem0_ecc_mbit_err", 563 .reset_level = HNS3_GLOBAL_RESET 564 }, { 565 .int_msk = BIT(9), 566 .msg = "rss_idt_mem1_ecc_mbit_err", 567 .reset_level = HNS3_GLOBAL_RESET 568 }, { 569 .int_msk = BIT(10), 570 .msg = "rss_idt_mem2_ecc_mbit_err", 571 .reset_level = HNS3_GLOBAL_RESET 572 }, { 573 .int_msk = BIT(11), 574 .msg = "rss_idt_mem3_ecc_mbit_err", 575 .reset_level = HNS3_GLOBAL_RESET 576 }, { 577 .int_msk = BIT(12), 578 .msg = "rss_idt_mem4_ecc_mbit_err", 579 .reset_level = HNS3_GLOBAL_RESET 580 }, { 581 .int_msk = BIT(13), 582 .msg = "rss_idt_mem5_ecc_mbit_err", 583 .reset_level = HNS3_GLOBAL_RESET 584 }, { 585 .int_msk = BIT(14), 586 .msg = "rss_idt_mem6_ecc_mbit_err", 587 .reset_level = HNS3_GLOBAL_RESET 588 }, { 589 .int_msk = BIT(15), 590 .msg = "rss_idt_mem7_ecc_mbit_err", 591 .reset_level = HNS3_GLOBAL_RESET 592 }, { 593 .int_msk = BIT(16), 594 .msg = "rss_idt_mem8_ecc_mbit_err", 595 .reset_level = HNS3_GLOBAL_RESET 596 }, { 597 .int_msk = BIT(17), 598 .msg = "rss_idt_mem9_ecc_mbit_err", 599 .reset_level = HNS3_GLOBAL_RESET 600 }, { 601 .int_msk = BIT(18), 602 .msg = "rss_idt_mem10_ecc_m1bit_err", 603 .reset_level = HNS3_GLOBAL_RESET 604 }, { 605 .int_msk = BIT(19), 606 .msg = "rss_idt_mem11_ecc_mbit_err", 607 .reset_level = HNS3_GLOBAL_RESET 608 }, { 609 .int_msk = BIT(20), 610 .msg = "rss_idt_mem12_ecc_mbit_err", 611 .reset_level = HNS3_GLOBAL_RESET 612 }, { 613 .int_msk = BIT(21), 614 .msg = "rss_idt_mem13_ecc_mbit_err", 615 .reset_level = HNS3_GLOBAL_RESET 616 }, { 617 .int_msk = BIT(22), 618 .msg = "rss_idt_mem14_ecc_mbit_err", 619 .reset_level = HNS3_GLOBAL_RESET 620 }, { 621 .int_msk = BIT(23), 622 .msg = "rss_idt_mem15_ecc_mbit_err", 623 .reset_level = HNS3_GLOBAL_RESET 624 }, { 625 .int_msk = BIT(24), 626 .msg = "port_vlan_mem_ecc_mbit_err", 627 .reset_level = HNS3_GLOBAL_RESET 628 }, { 629 .int_msk = BIT(25), 630 .msg = "mcast_linear_table_mem_ecc_mbit_err", 631 .reset_level = HNS3_GLOBAL_RESET 632 }, { 633 .int_msk = BIT(26), 634 .msg = "mcast_result_mem_ecc_mbit_err", 635 .reset_level = HNS3_GLOBAL_RESET 636 }, { 637 .int_msk = BIT(27), 638 .msg = "flow_director_ad_mem0_ecc_mbit_err", 639 .reset_level = HNS3_GLOBAL_RESET 640 }, { 641 .int_msk = BIT(28), 642 .msg = "flow_director_ad_mem1_ecc_mbit_err", 643 .reset_level = HNS3_GLOBAL_RESET 644 }, { 645 .int_msk = BIT(29), 646 .msg = "rx_vlan_tag_memory_ecc_mbit_err", 647 .reset_level = HNS3_GLOBAL_RESET 648 }, { 649 .int_msk = BIT(30), 650 .msg = "Tx_UP_mapping_config_mem_ecc_mbit_err", 651 .reset_level = HNS3_GLOBAL_RESET 652 }, { 653 .int_msk = 0, 654 .msg = NULL, 655 .reset_level = HNS3_NONE_RESET 656 } 657 }; 658 659 static const struct hns3_hw_error ppp_mpf_abnormal_int_st3[] = { 660 { 661 .int_msk = BIT(0), 662 .msg = "hfs_fifo_mem_ecc_mbit_err", 663 .reset_level = HNS3_GLOBAL_RESET 664 }, { 665 .int_msk = BIT(1), 666 .msg = "rslt_descr_fifo_mem_ecc_mbit_err", 667 .reset_level = HNS3_GLOBAL_RESET 668 }, { 669 .int_msk = BIT(2), 670 .msg = "tx_vlan_tag_mem_ecc_mbit_err", 671 .reset_level = HNS3_GLOBAL_RESET 672 }, { 673 .int_msk = BIT(3), 674 .msg = "FD_CN0_memory_ecc_mbit_err", 675 .reset_level = HNS3_GLOBAL_RESET 676 }, { 677 .int_msk = BIT(4), 678 .msg = "FD_CN1_memory_ecc_mbit_err", 679 .reset_level = HNS3_GLOBAL_RESET 680 }, { 681 .int_msk = BIT(5), 682 .msg = "GRO_AD_memory_ecc_mbit_err", 683 .reset_level = HNS3_GLOBAL_RESET 684 }, { 685 .int_msk = 0, 686 .msg = NULL, 687 .reset_level = HNS3_NONE_RESET 688 } 689 }; 690 691 static const struct hns3_hw_error ppu_mpf_abnormal_int_st3[] = { 692 { 693 .int_msk = BIT(4), 694 .msg = "gro_bd_ecc_mbit_err", 695 .reset_level = HNS3_GLOBAL_RESET 696 }, { 697 .int_msk = BIT(5), 698 .msg = "gro_context_ecc_mbit_err", 699 .reset_level = HNS3_GLOBAL_RESET 700 }, { 701 .int_msk = BIT(6), 702 .msg = "rx_stash_cfg_ecc_mbit_err", 703 .reset_level = HNS3_GLOBAL_RESET 704 }, { 705 .int_msk = BIT(7), 706 .msg = "axi_rd_fbd_ecc_mbit_err", 707 .reset_level = HNS3_GLOBAL_RESET 708 }, { 709 .int_msk = 0, 710 .msg = NULL, 711 .reset_level = HNS3_NONE_RESET 712 } 713 }; 714 715 static const struct hns3_hw_error tm_sch_int[] = { 716 { 717 .int_msk = BIT(1), 718 .msg = "tm_sch_ecc_mbit_err", 719 .reset_level = HNS3_GLOBAL_RESET 720 }, { 721 .int_msk = BIT(2), 722 .msg = "tm_sch_port_shap_sub_fifo_wr_err", 723 .reset_level = HNS3_GLOBAL_RESET 724 }, { 725 .int_msk = BIT(3), 726 .msg = "tm_sch_port_shap_sub_fifo_rd_err", 727 .reset_level = HNS3_GLOBAL_RESET 728 }, { 729 .int_msk = BIT(4), 730 .msg = "tm_sch_pg_pshap_sub_fifo_wr_err", 731 .reset_level = HNS3_GLOBAL_RESET 732 }, { 733 .int_msk = BIT(5), 734 .msg = "tm_sch_pg_pshap_sub_fifo_rd_err", 735 .reset_level = HNS3_GLOBAL_RESET 736 }, { 737 .int_msk = BIT(6), 738 .msg = "tm_sch_pg_cshap_sub_fifo_wr_err", 739 .reset_level = HNS3_GLOBAL_RESET 740 }, { 741 .int_msk = BIT(7), 742 .msg = "tm_sch_pg_cshap_sub_fifo_rd_err", 743 .reset_level = HNS3_GLOBAL_RESET 744 }, { 745 .int_msk = BIT(8), 746 .msg = "tm_sch_pri_pshap_sub_fifo_wr_err", 747 .reset_level = HNS3_GLOBAL_RESET 748 }, { 749 .int_msk = BIT(9), 750 .msg = "tm_sch_pri_pshap_sub_fifo_rd_err", 751 .reset_level = HNS3_GLOBAL_RESET 752 }, { 753 .int_msk = BIT(10), 754 .msg = "tm_sch_pri_cshap_sub_fifo_wr_err", 755 .reset_level = HNS3_GLOBAL_RESET 756 }, { 757 .int_msk = BIT(11), 758 .msg = "tm_sch_pri_cshap_sub_fifo_rd_err", 759 .reset_level = HNS3_GLOBAL_RESET 760 }, { 761 .int_msk = BIT(12), 762 .msg = "tm_sch_port_shap_offset_fifo_wr_err", 763 .reset_level = HNS3_GLOBAL_RESET 764 }, { 765 .int_msk = BIT(13), 766 .msg = "tm_sch_port_shap_offset_fifo_rd_err", 767 .reset_level = HNS3_GLOBAL_RESET 768 }, { 769 .int_msk = BIT(14), 770 .msg = "tm_sch_pg_pshap_offset_fifo_wr_err", 771 .reset_level = HNS3_GLOBAL_RESET 772 }, { 773 .int_msk = BIT(15), 774 .msg = "tm_sch_pg_pshap_offset_fifo_rd_err", 775 .reset_level = HNS3_GLOBAL_RESET 776 }, { 777 .int_msk = BIT(16), 778 .msg = "tm_sch_pg_cshap_offset_fifo_wr_err", 779 .reset_level = HNS3_GLOBAL_RESET 780 }, { 781 .int_msk = BIT(17), 782 .msg = "tm_sch_pg_cshap_offset_fifo_rd_err", 783 .reset_level = HNS3_GLOBAL_RESET 784 }, { 785 .int_msk = BIT(18), 786 .msg = "tm_sch_pri_pshap_offset_fifo_wr_err", 787 .reset_level = HNS3_GLOBAL_RESET 788 }, { 789 .int_msk = BIT(19), 790 .msg = "tm_sch_pri_pshap_offset_fifo_rd_err", 791 .reset_level = HNS3_GLOBAL_RESET 792 }, { 793 .int_msk = BIT(20), 794 .msg = "tm_sch_pri_cshap_offset_fifo_wr_err", 795 .reset_level = HNS3_GLOBAL_RESET 796 }, { 797 .int_msk = BIT(21), 798 .msg = "tm_sch_pri_cshap_offset_fifo_rd_err", 799 .reset_level = HNS3_GLOBAL_RESET 800 }, { 801 .int_msk = BIT(22), 802 .msg = "tm_sch_rq_fifo_wr_err", 803 .reset_level = HNS3_GLOBAL_RESET 804 }, { 805 .int_msk = BIT(23), 806 .msg = "tm_sch_rq_fifo_rd_err", 807 .reset_level = HNS3_GLOBAL_RESET 808 }, { 809 .int_msk = BIT(24), 810 .msg = "tm_sch_nq_fifo_wr_err", 811 .reset_level = HNS3_GLOBAL_RESET 812 }, { 813 .int_msk = BIT(25), 814 .msg = "tm_sch_nq_fifo_rd_err", 815 .reset_level = HNS3_GLOBAL_RESET 816 }, { 817 .int_msk = BIT(26), 818 .msg = "tm_sch_roce_up_fifo_wr_err", 819 .reset_level = HNS3_GLOBAL_RESET 820 }, { 821 .int_msk = BIT(27), 822 .msg = "tm_sch_roce_up_fifo_rd_err", 823 .reset_level = HNS3_GLOBAL_RESET 824 }, { 825 .int_msk = BIT(28), 826 .msg = "tm_sch_rcb_byte_fifo_wr_err", 827 .reset_level = HNS3_GLOBAL_RESET 828 }, { 829 .int_msk = BIT(29), 830 .msg = "tm_sch_rcb_byte_fifo_rd_err", 831 .reset_level = HNS3_GLOBAL_RESET 832 }, { 833 .int_msk = BIT(30), 834 .msg = "tm_sch_ssu_byte_fifo_wr_err", 835 .reset_level = HNS3_GLOBAL_RESET 836 }, { 837 .int_msk = BIT(31), 838 .msg = "tm_sch_ssu_byte_fifo_rd_err", 839 .reset_level = HNS3_GLOBAL_RESET 840 }, { 841 .int_msk = 0, 842 .msg = NULL, 843 .reset_level = HNS3_NONE_RESET 844 } 845 }; 846 847 static const struct hns3_hw_error qcn_fifo_int[] = { 848 { 849 .int_msk = BIT(0), 850 .msg = "qcn_shap_gp0_sch_fifo_rd_err", 851 .reset_level = HNS3_GLOBAL_RESET 852 }, { 853 .int_msk = BIT(1), 854 .msg = "qcn_shap_gp0_sch_fifo_wr_err", 855 .reset_level = HNS3_GLOBAL_RESET 856 }, { 857 .int_msk = BIT(2), 858 .msg = "qcn_shap_gp1_sch_fifo_rd_err", 859 .reset_level = HNS3_GLOBAL_RESET 860 }, { 861 .int_msk = BIT(3), 862 .msg = "qcn_shap_gp1_sch_fifo_wr_err", 863 .reset_level = HNS3_GLOBAL_RESET 864 }, { 865 .int_msk = BIT(4), 866 .msg = "qcn_shap_gp2_sch_fifo_rd_err", 867 .reset_level = HNS3_GLOBAL_RESET 868 }, { 869 .int_msk = BIT(5), 870 .msg = "qcn_shap_gp2_sch_fifo_wr_err", 871 .reset_level = HNS3_GLOBAL_RESET 872 }, { 873 .int_msk = BIT(6), 874 .msg = "qcn_shap_gp3_sch_fifo_rd_err", 875 .reset_level = HNS3_GLOBAL_RESET 876 }, { 877 .int_msk = BIT(7), 878 .msg = "qcn_shap_gp3_sch_fifo_wr_err", 879 .reset_level = HNS3_GLOBAL_RESET 880 }, { 881 .int_msk = BIT(8), 882 .msg = "qcn_shap_gp0_offset_fifo_rd_err", 883 .reset_level = HNS3_GLOBAL_RESET 884 }, { 885 .int_msk = BIT(9), 886 .msg = "qcn_shap_gp0_offset_fifo_wr_err", 887 .reset_level = HNS3_GLOBAL_RESET 888 }, { 889 .int_msk = BIT(10), 890 .msg = "qcn_shap_gp1_offset_fifo_rd_err", 891 .reset_level = HNS3_GLOBAL_RESET 892 }, { 893 .int_msk = BIT(11), 894 .msg = "qcn_shap_gp1_offset_fifo_wr_err", 895 .reset_level = HNS3_GLOBAL_RESET 896 }, { 897 .int_msk = BIT(12), 898 .msg = "qcn_shap_gp2_offset_fifo_rd_err", 899 .reset_level = HNS3_GLOBAL_RESET 900 }, { 901 .int_msk = BIT(13), 902 .msg = "qcn_shap_gp2_offset_fifo_wr_err", 903 .reset_level = HNS3_GLOBAL_RESET 904 }, { 905 .int_msk = BIT(14), 906 .msg = "qcn_shap_gp3_offset_fifo_rd_err", 907 .reset_level = HNS3_GLOBAL_RESET 908 }, { 909 .int_msk = BIT(15), 910 .msg = "qcn_shap_gp3_offset_fifo_wr_err", 911 .reset_level = HNS3_GLOBAL_RESET 912 }, { 913 .int_msk = BIT(16), 914 .msg = "qcn_byte_info_fifo_rd_err", 915 .reset_level = HNS3_GLOBAL_RESET 916 }, { 917 .int_msk = BIT(17), 918 .msg = "qcn_byte_info_fifo_wr_err", 919 .reset_level = HNS3_GLOBAL_RESET 920 }, { 921 .int_msk = 0, 922 .msg = NULL, 923 .reset_level = HNS3_NONE_RESET 924 } 925 }; 926 927 static const struct hns3_hw_error qcn_ecc_int[] = { 928 { 929 .int_msk = BIT(1), 930 .msg = "qcn_byte_mem_ecc_mbit_err", 931 .reset_level = HNS3_GLOBAL_RESET 932 }, { 933 .int_msk = BIT(3), 934 .msg = "qcn_time_mem_ecc_mbit_err", 935 .reset_level = HNS3_GLOBAL_RESET 936 }, { 937 .int_msk = BIT(5), 938 .msg = "qcn_fb_mem_ecc_mbit_err", 939 .reset_level = HNS3_GLOBAL_RESET 940 }, { 941 .int_msk = BIT(7), 942 .msg = "qcn_link_mem_ecc_mbit_err", 943 .reset_level = HNS3_GLOBAL_RESET 944 }, { 945 .int_msk = BIT(9), 946 .msg = "qcn_rate_mem_ecc_mbit_err", 947 .reset_level = HNS3_GLOBAL_RESET 948 }, { 949 .int_msk = BIT(11), 950 .msg = "qcn_tmplt_mem_ecc_mbit_err", 951 .reset_level = HNS3_GLOBAL_RESET 952 }, { 953 .int_msk = BIT(13), 954 .msg = "qcn_shap_cfg_mem_ecc_mbit_err", 955 .reset_level = HNS3_GLOBAL_RESET 956 }, { 957 .int_msk = BIT(15), 958 .msg = "qcn_gp0_barrel_mem_ecc_mbit_err", 959 .reset_level = HNS3_GLOBAL_RESET 960 }, { 961 .int_msk = BIT(17), 962 .msg = "qcn_gp1_barrel_mem_ecc_mbit_err", 963 .reset_level = HNS3_GLOBAL_RESET 964 }, { 965 .int_msk = BIT(19), 966 .msg = "qcn_gp2_barrel_mem_ecc_mbit_err", 967 .reset_level = HNS3_GLOBAL_RESET 968 }, { 969 .int_msk = BIT(21), 970 .msg = "qcn_gp3_barral_mem_ecc_mbit_err", 971 .reset_level = HNS3_GLOBAL_RESET 972 }, { 973 .int_msk = 0, 974 .msg = NULL, 975 .reset_level = HNS3_NONE_RESET 976 } 977 }; 978 979 static const struct hns3_hw_error ncsi_ecc_int[] = { 980 { 981 .int_msk = BIT(1), 982 .msg = "ncsi_tx_ecc_mbit_err", 983 .reset_level = HNS3_NONE_RESET 984 }, { 985 .int_msk = 0, 986 .msg = NULL, 987 .reset_level = HNS3_NONE_RESET 988 } 989 }; 990 991 static const struct hns3_hw_error ssu_fifo_overflow_int[] = { 992 { 993 .int_msk = BIT(0), 994 .msg = "ig_mac_inf_int", 995 .reset_level = HNS3_GLOBAL_RESET 996 }, { 997 .int_msk = BIT(1), 998 .msg = "ig_host_inf_int", 999 .reset_level = HNS3_GLOBAL_RESET 1000 }, { 1001 .int_msk = BIT(2), 1002 .msg = "ig_roc_buf_int", 1003 .reset_level = HNS3_GLOBAL_RESET 1004 }, { 1005 .int_msk = BIT(3), 1006 .msg = "ig_host_data_fifo_int", 1007 .reset_level = HNS3_GLOBAL_RESET 1008 }, { 1009 .int_msk = BIT(4), 1010 .msg = "ig_host_key_fifo_int", 1011 .reset_level = HNS3_GLOBAL_RESET 1012 }, { 1013 .int_msk = BIT(5), 1014 .msg = "tx_qcn_fifo_int", 1015 .reset_level = HNS3_GLOBAL_RESET 1016 }, { 1017 .int_msk = BIT(6), 1018 .msg = "rx_qcn_fifo_int", 1019 .reset_level = HNS3_GLOBAL_RESET 1020 }, { 1021 .int_msk = BIT(7), 1022 .msg = "tx_pf_rd_fifo_int", 1023 .reset_level = HNS3_GLOBAL_RESET 1024 }, { 1025 .int_msk = BIT(8), 1026 .msg = "rx_pf_rd_fifo_int", 1027 .reset_level = HNS3_GLOBAL_RESET 1028 }, { 1029 .int_msk = BIT(9), 1030 .msg = "qm_eof_fifo_int", 1031 .reset_level = HNS3_GLOBAL_RESET 1032 }, { 1033 .int_msk = BIT(10), 1034 .msg = "mb_rlt_fifo_int", 1035 .reset_level = HNS3_GLOBAL_RESET 1036 }, { 1037 .int_msk = BIT(11), 1038 .msg = "dup_uncopy_fifo_int", 1039 .reset_level = HNS3_GLOBAL_RESET 1040 }, { 1041 .int_msk = BIT(12), 1042 .msg = "dup_cnt_rd_fifo_int", 1043 .reset_level = HNS3_GLOBAL_RESET 1044 }, { 1045 .int_msk = BIT(13), 1046 .msg = "dup_cnt_drop_fifo_int", 1047 .reset_level = HNS3_GLOBAL_RESET 1048 }, { 1049 .int_msk = BIT(14), 1050 .msg = "dup_cnt_wrb_fifo_int", 1051 .reset_level = HNS3_GLOBAL_RESET 1052 }, { 1053 .int_msk = BIT(15), 1054 .msg = "host_cmd_fifo_int", 1055 .reset_level = HNS3_GLOBAL_RESET 1056 }, { 1057 .int_msk = BIT(16), 1058 .msg = "mac_cmd_fifo_int", 1059 .reset_level = HNS3_GLOBAL_RESET 1060 }, { 1061 .int_msk = BIT(17), 1062 .msg = "host_cmd_bitmap_empty_int", 1063 .reset_level = HNS3_GLOBAL_RESET 1064 }, { 1065 .int_msk = BIT(18), 1066 .msg = "mac_cmd_bitmap_empty_int", 1067 .reset_level = HNS3_GLOBAL_RESET 1068 }, { 1069 .int_msk = BIT(19), 1070 .msg = "dup_bitmap_empty_int", 1071 .reset_level = HNS3_GLOBAL_RESET 1072 }, { 1073 .int_msk = BIT(20), 1074 .msg = "out_queue_bitmap_empty_int", 1075 .reset_level = HNS3_GLOBAL_RESET 1076 }, { 1077 .int_msk = BIT(21), 1078 .msg = "bank2_bitmap_empty_int", 1079 .reset_level = HNS3_GLOBAL_RESET 1080 }, { 1081 .int_msk = BIT(22), 1082 .msg = "bank1_bitmap_empty_int", 1083 .reset_level = HNS3_GLOBAL_RESET 1084 }, { 1085 .int_msk = BIT(23), 1086 .msg = "bank0_bitmap_empty_int", 1087 .reset_level = HNS3_GLOBAL_RESET 1088 }, { 1089 .int_msk = 0, 1090 .msg = NULL, 1091 .reset_level = HNS3_NONE_RESET 1092 } 1093 }; 1094 1095 static const struct hns3_hw_error ssu_ets_tcg_int[] = { 1096 { 1097 .int_msk = BIT(0), 1098 .msg = "ets_rd_int_rx_tcg", 1099 .reset_level = HNS3_GLOBAL_RESET 1100 }, { 1101 .int_msk = BIT(1), 1102 .msg = "ets_wr_int_rx_tcg", 1103 .reset_level = HNS3_GLOBAL_RESET 1104 }, { 1105 .int_msk = BIT(2), 1106 .msg = "ets_rd_int_tx_tcg", 1107 .reset_level = HNS3_GLOBAL_RESET 1108 }, { 1109 .int_msk = BIT(3), 1110 .msg = "ets_wr_int_tx_tcg", 1111 .reset_level = HNS3_GLOBAL_RESET 1112 }, { 1113 .int_msk = 0, 1114 .msg = NULL, 1115 .reset_level = HNS3_NONE_RESET 1116 } 1117 }; 1118 1119 static const struct hns3_hw_error igu_egu_tnl_int[] = { 1120 { 1121 .int_msk = BIT(0), 1122 .msg = "rx_buf_overflow", 1123 .reset_level = HNS3_GLOBAL_RESET 1124 }, { 1125 .int_msk = BIT(1), 1126 .msg = "rx_stp_fifo_overflow", 1127 .reset_level = HNS3_GLOBAL_RESET 1128 }, { 1129 .int_msk = BIT(2), 1130 .msg = "rx_stp_fifo_underflow", 1131 .reset_level = HNS3_GLOBAL_RESET 1132 }, { 1133 .int_msk = BIT(3), 1134 .msg = "tx_buf_overflow", 1135 .reset_level = HNS3_GLOBAL_RESET 1136 }, { 1137 .int_msk = BIT(4), 1138 .msg = "tx_buf_underrun", 1139 .reset_level = HNS3_GLOBAL_RESET 1140 }, { 1141 .int_msk = BIT(5), 1142 .msg = "rx_stp_buf_overflow", 1143 .reset_level = HNS3_GLOBAL_RESET 1144 }, { 1145 .int_msk = 0, 1146 .msg = NULL, 1147 .reset_level = HNS3_NONE_RESET 1148 } 1149 }; 1150 1151 static const struct hns3_hw_error ssu_port_based_err_int[] = { 1152 { 1153 .int_msk = BIT(0), 1154 .msg = "roc_pkt_without_key_port", 1155 .reset_level = HNS3_FUNC_RESET 1156 }, { 1157 .int_msk = BIT(1), 1158 .msg = "tpu_pkt_without_key_port", 1159 .reset_level = HNS3_GLOBAL_RESET 1160 }, { 1161 .int_msk = BIT(2), 1162 .msg = "igu_pkt_without_key_port", 1163 .reset_level = HNS3_GLOBAL_RESET 1164 }, { 1165 .int_msk = BIT(3), 1166 .msg = "roc_eof_mis_match_port", 1167 .reset_level = HNS3_GLOBAL_RESET 1168 }, { 1169 .int_msk = BIT(4), 1170 .msg = "tpu_eof_mis_match_port", 1171 .reset_level = HNS3_GLOBAL_RESET 1172 }, { 1173 .int_msk = BIT(5), 1174 .msg = "igu_eof_mis_match_port", 1175 .reset_level = HNS3_GLOBAL_RESET 1176 }, { 1177 .int_msk = BIT(6), 1178 .msg = "roc_sof_mis_match_port", 1179 .reset_level = HNS3_GLOBAL_RESET 1180 }, { 1181 .int_msk = BIT(7), 1182 .msg = "tpu_sof_mis_match_port", 1183 .reset_level = HNS3_GLOBAL_RESET 1184 }, { 1185 .int_msk = BIT(8), 1186 .msg = "igu_sof_mis_match_port", 1187 .reset_level = HNS3_GLOBAL_RESET 1188 }, { 1189 .int_msk = BIT(11), 1190 .msg = "ets_rd_int_rx_port", 1191 .reset_level = HNS3_GLOBAL_RESET 1192 }, { 1193 .int_msk = BIT(12), 1194 .msg = "ets_wr_int_rx_port", 1195 .reset_level = HNS3_GLOBAL_RESET 1196 }, { 1197 .int_msk = BIT(13), 1198 .msg = "ets_rd_int_tx_port", 1199 .reset_level = HNS3_GLOBAL_RESET 1200 }, { 1201 .int_msk = BIT(14), 1202 .msg = "ets_wr_int_tx_port", 1203 .reset_level = HNS3_GLOBAL_RESET 1204 }, { 1205 .int_msk = 0, 1206 .msg = NULL, 1207 .reset_level = HNS3_NONE_RESET 1208 } 1209 }; 1210 1211 static const struct hns3_hw_error_desc mpf_ras_err_tbl[] = { 1212 { 1213 .desc_offset = 0, 1214 .data_offset = 0, 1215 .msg = "IMP_TCM_ECC_INT_STS", 1216 .hw_err = imp_tcm_ecc_int 1217 }, { 1218 .desc_offset = 0, 1219 .data_offset = 1, 1220 .msg = "CMDQ_MEM_ECC_INT_STS", 1221 .hw_err = cmdq_mem_ecc_int 1222 }, { 1223 .desc_offset = 0, 1224 .data_offset = 2, 1225 .msg = "IMP_RD_POISON_INT_STS", 1226 .hw_err = imp_rd_poison_int 1227 }, { 1228 .desc_offset = 0, 1229 .data_offset = 3, 1230 .msg = "TQP_INT_ECC_INT_STS", 1231 .hw_err = tqp_int_ecc_int 1232 }, { 1233 .desc_offset = 0, 1234 .data_offset = 4, 1235 .msg = "MSIX_ECC_INT_STS", 1236 .hw_err = msix_ecc_int 1237 }, { 1238 .desc_offset = 2, 1239 .data_offset = 2, 1240 .msg = "SSU_ECC_MULTI_BIT_INT_0", 1241 .hw_err = ssu_ecc_multi_bit_int_0 1242 }, { 1243 .desc_offset = 2, 1244 .data_offset = 3, 1245 .msg = "SSU_ECC_MULTI_BIT_INT_1", 1246 .hw_err = ssu_ecc_multi_bit_int_1 1247 }, { 1248 .desc_offset = 2, 1249 .data_offset = 4, 1250 .msg = "SSU_COMMON_ERR_INT", 1251 .hw_err = ssu_common_ecc_int 1252 }, { 1253 .desc_offset = 3, 1254 .data_offset = 0, 1255 .msg = "IGU_INT_STS", 1256 .hw_err = igu_int 1257 }, { 1258 .desc_offset = 4, 1259 .data_offset = 1, 1260 .msg = "PPP_MPF_ABNORMAL_INT_ST1", 1261 .hw_err = ppp_mpf_abnormal_int_st1 1262 }, { 1263 .desc_offset = 4, 1264 .data_offset = 3, 1265 .msg = "PPP_MPF_ABNORMAL_INT_ST3", 1266 .hw_err = ppp_mpf_abnormal_int_st3 1267 }, { 1268 .desc_offset = 5, 1269 .data_offset = 1, 1270 .msg = "PPU_MPF_ABNORMAL_INT_ST1", 1271 .hw_err = ppu_mpf_abnormal_int_st1 1272 }, { 1273 .desc_offset = 5, 1274 .data_offset = 2, 1275 .msg = "PPU_MPF_ABNORMAL_INT_ST2_RAS", 1276 .hw_err = ppu_mpf_abnormal_int_st2_ras 1277 }, { 1278 .desc_offset = 5, 1279 .data_offset = 3, 1280 .msg = "PPU_MPF_ABNORMAL_INT_ST3", 1281 .hw_err = ppu_mpf_abnormal_int_st3 1282 }, { 1283 .desc_offset = 6, 1284 .data_offset = 0, 1285 .msg = "TM_SCH_RINT", 1286 .hw_err = tm_sch_int 1287 }, { 1288 .desc_offset = 7, 1289 .data_offset = 0, 1290 .msg = "QCN_FIFO_RINT", 1291 .hw_err = qcn_fifo_int 1292 }, { 1293 .desc_offset = 7, 1294 .data_offset = 1, 1295 .msg = "QCN_ECC_RINT", 1296 .hw_err = qcn_ecc_int 1297 }, { 1298 .desc_offset = 9, 1299 .data_offset = 0, 1300 .msg = "NCSI_ECC_INT_RPT", 1301 .hw_err = ncsi_ecc_int 1302 }, { 1303 .desc_offset = 0, 1304 .data_offset = 0, 1305 .msg = NULL, 1306 .hw_err = NULL 1307 } 1308 }; 1309 1310 static const struct hns3_hw_error_desc pf_ras_err_tbl[] = { 1311 { 1312 .desc_offset = 0, 1313 .data_offset = 0, 1314 .msg = "SSU_PORT_BASED_ERR_INT_RAS", 1315 .hw_err = ssu_port_based_err_int 1316 }, { 1317 .desc_offset = 0, 1318 .data_offset = 1, 1319 .msg = "SSU_FIFO_OVERFLOW_INT", 1320 .hw_err = ssu_fifo_overflow_int 1321 }, { 1322 .desc_offset = 0, 1323 .data_offset = 2, 1324 .msg = "SSU_ETS_TCG_INT", 1325 .hw_err = ssu_ets_tcg_int 1326 }, { 1327 .desc_offset = 1, 1328 .data_offset = 0, 1329 .msg = "IGU_EGU_TNL_INT_STS", 1330 .hw_err = igu_egu_tnl_int 1331 }, { 1332 .desc_offset = 3, 1333 .data_offset = 0, 1334 .msg = "PPU_PF_ABNORMAL_INT_ST_RAS", 1335 .hw_err = ppu_pf_abnormal_int_ras 1336 }, { 1337 .desc_offset = 0, 1338 .data_offset = 0, 1339 .msg = NULL, 1340 .hw_err = NULL 1341 } 1342 }; 1343 1344 static const struct hns3_hw_error_desc mpf_msix_err_tbl[] = { 1345 { 1346 .desc_offset = 1, 1347 .data_offset = 0, 1348 .msg = "MAC_AFIFO_TNL_INT_R", 1349 .hw_err = mac_afifo_tnl_int 1350 }, { 1351 .desc_offset = 5, 1352 .data_offset = 2, 1353 .msg = "PPU_MPF_ABNORMAL_INT_ST2_MSIX", 1354 .hw_err = ppu_mpf_abnormal_int_st2_msix 1355 }, { 1356 .desc_offset = 0, 1357 .data_offset = 0, 1358 .msg = NULL, 1359 .hw_err = NULL 1360 } 1361 }; 1362 1363 static const struct hns3_hw_error_desc pf_msix_err_tbl[] = { 1364 { 1365 .desc_offset = 0, 1366 .data_offset = 0, 1367 .msg = "SSU_PORT_BASED_ERR_INT_MSIX", 1368 .hw_err = ssu_port_based_pf_int 1369 }, { 1370 .desc_offset = 2, 1371 .data_offset = 0, 1372 .msg = "PPP_PF_ABNORMAL_INT_ST0", 1373 .hw_err = ppp_pf_abnormal_int 1374 }, { 1375 .desc_offset = 3, 1376 .data_offset = 0, 1377 .msg = "PPU_PF_ABNORMAL_INT_ST_MSIX", 1378 .hw_err = ppu_pf_abnormal_int_msix 1379 }, { 1380 .desc_offset = 0, 1381 .data_offset = 0, 1382 .msg = NULL, 1383 .hw_err = NULL 1384 } 1385 }; 1386 1387 enum hns3_hw_err_type { 1388 MPF_MSIX_ERR, 1389 PF_MSIX_ERR, 1390 MPF_RAS_ERR, 1391 PF_RAS_ERR, 1392 }; 1393 1394 static int 1395 hns3_config_ncsi_hw_err_int(struct hns3_adapter *hns, bool en) 1396 { 1397 struct hns3_hw *hw = &hns->hw; 1398 struct hns3_cmd_desc desc; 1399 int ret; 1400 1401 /* configure NCSI error interrupts */ 1402 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_NCSI_INT_EN, false); 1403 if (en) 1404 desc.data[0] = rte_cpu_to_le_32(HNS3_NCSI_ERR_INT_EN); 1405 1406 ret = hns3_cmd_send(hw, &desc, 1); 1407 if (ret) 1408 hns3_err(hw, "fail to %s NCSI error interrupts, ret = %d", 1409 en ? "enable" : "disable", ret); 1410 1411 return ret; 1412 } 1413 1414 static int 1415 enable_igu_egu_err_intr(struct hns3_adapter *hns, bool en) 1416 { 1417 struct hns3_hw *hw = &hns->hw; 1418 struct hns3_cmd_desc desc; 1419 int ret; 1420 1421 /* configure IGU,EGU error interrupts */ 1422 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_IGU_COMMON_INT_EN, false); 1423 if (en) 1424 desc.data[0] = rte_cpu_to_le_32(HNS3_IGU_ERR_INT_ENABLE); 1425 else 1426 desc.data[0] = rte_cpu_to_le_32(HNS3_IGU_ERR_INT_DISABLE); 1427 1428 desc.data[1] = rte_cpu_to_le_32(HNS3_IGU_ERR_INT_EN_MASK); 1429 1430 ret = hns3_cmd_send(hw, &desc, 1); 1431 if (ret) { 1432 hns3_err(hw, "fail to %s IGU common interrupts, ret = %d", 1433 en ? "enable" : "disable", ret); 1434 return ret; 1435 } 1436 1437 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_IGU_EGU_TNL_INT_EN, false); 1438 if (en) 1439 desc.data[0] = rte_cpu_to_le_32(HNS3_IGU_TNL_ERR_INT_EN); 1440 1441 desc.data[1] = rte_cpu_to_le_32(HNS3_IGU_TNL_ERR_INT_EN_MASK); 1442 1443 ret = hns3_cmd_send(hw, &desc, 1); 1444 if (ret) { 1445 hns3_err(hw, "fail to %s IGU-EGU TNL interrupts, ret = %d", 1446 en ? "enable" : "disable", ret); 1447 return ret; 1448 } 1449 1450 return hns3_config_ncsi_hw_err_int(hns, en); 1451 } 1452 1453 static int 1454 config_ppp_err_intr(struct hns3_adapter *hns, uint32_t cmd, bool en) 1455 { 1456 struct hns3_hw *hw = &hns->hw; 1457 struct hns3_cmd_desc desc[2]; 1458 int ret; 1459 1460 /* configure PPP error interrupts */ 1461 hns3_cmd_setup_basic_desc(&desc[0], cmd, false); 1462 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1463 hns3_cmd_setup_basic_desc(&desc[1], cmd, false); 1464 1465 if (cmd == HNS3_OPC_PPP_CMD0_INT_CMD) { 1466 if (en) { 1467 desc[0].data[0] = 1468 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT0_EN); 1469 desc[0].data[1] = 1470 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT1_EN); 1471 desc[0].data[4] = 1472 rte_cpu_to_le_32(HNS3_PPP_PF_ERR_INT_EN); 1473 } 1474 1475 desc[1].data[0] = 1476 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT0_EN_MASK); 1477 desc[1].data[1] = 1478 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT1_EN_MASK); 1479 desc[1].data[2] = 1480 rte_cpu_to_le_32(HNS3_PPP_PF_ERR_INT_EN_MASK); 1481 } else if (cmd == HNS3_OPC_PPP_CMD1_INT_CMD) { 1482 if (en) { 1483 desc[0].data[0] = 1484 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT2_EN); 1485 desc[0].data[1] = 1486 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT3_EN); 1487 } 1488 1489 desc[1].data[0] = 1490 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT2_EN_MASK); 1491 desc[1].data[1] = 1492 rte_cpu_to_le_32(HNS3_PPP_MPF_ECC_ERR_INT3_EN_MASK); 1493 } 1494 1495 ret = hns3_cmd_send(hw, &desc[0], 2); 1496 if (ret) 1497 hns3_err(hw, "fail to %s PPP error int, ret = %d", 1498 en ? "enable" : "disable", ret); 1499 1500 return ret; 1501 } 1502 1503 static int 1504 enable_ppp_err_intr(struct hns3_adapter *hns, bool en) 1505 { 1506 int ret; 1507 1508 ret = config_ppp_err_intr(hns, HNS3_OPC_PPP_CMD0_INT_CMD, en); 1509 if (ret) 1510 return ret; 1511 1512 return config_ppp_err_intr(hns, HNS3_OPC_PPP_CMD1_INT_CMD, en); 1513 } 1514 1515 static int 1516 enable_ssu_err_intr(struct hns3_adapter *hns, bool en) 1517 { 1518 struct hns3_hw *hw = &hns->hw; 1519 struct hns3_cmd_desc desc[2]; 1520 int ret; 1521 1522 /* configure SSU ecc error interrupts */ 1523 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_SSU_ECC_INT_CMD, false); 1524 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1525 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_SSU_ECC_INT_CMD, false); 1526 if (en) { 1527 desc[0].data[0] = 1528 rte_cpu_to_le_32(HNS3_SSU_1BIT_ECC_ERR_INT_EN); 1529 desc[0].data[1] = 1530 rte_cpu_to_le_32(HNS3_SSU_MULTI_BIT_ECC_ERR_INT_EN); 1531 desc[0].data[4] = 1532 rte_cpu_to_le_32(HNS3_SSU_BIT32_ECC_ERR_INT_EN); 1533 } 1534 1535 desc[1].data[0] = rte_cpu_to_le_32(HNS3_SSU_1BIT_ECC_ERR_INT_EN_MASK); 1536 desc[1].data[1] = 1537 rte_cpu_to_le_32(HNS3_SSU_MULTI_BIT_ECC_ERR_INT_EN_MASK); 1538 desc[1].data[2] = rte_cpu_to_le_32(HNS3_SSU_BIT32_ECC_ERR_INT_EN_MASK); 1539 1540 ret = hns3_cmd_send(hw, &desc[0], 2); 1541 if (ret) { 1542 hns3_err(hw, "fail to %s SSU ECC error interrupt, ret = %d", 1543 en ? "enable" : "disable", ret); 1544 return ret; 1545 } 1546 1547 /* configure SSU common error interrupts */ 1548 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_SSU_COMMON_INT_CMD, false); 1549 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1550 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_SSU_COMMON_INT_CMD, false); 1551 1552 if (en) { 1553 desc[0].data[0] = rte_cpu_to_le_32(HNS3_SSU_COMMON_INT_EN); 1554 desc[0].data[1] = 1555 rte_cpu_to_le_32(HNS3_SSU_PORT_BASED_ERR_INT_EN); 1556 desc[0].data[2] = 1557 rte_cpu_to_le_32(HNS3_SSU_FIFO_OVERFLOW_ERR_INT_EN); 1558 } 1559 1560 desc[1].data[0] = rte_cpu_to_le_32(HNS3_SSU_COMMON_INT_EN_MASK | 1561 HNS3_SSU_PORT_BASED_ERR_INT_EN_MASK); 1562 desc[1].data[1] = 1563 rte_cpu_to_le_32(HNS3_SSU_FIFO_OVERFLOW_ERR_INT_EN_MASK); 1564 1565 ret = hns3_cmd_send(hw, &desc[0], 2); 1566 if (ret) 1567 hns3_err(hw, "fail to %s SSU COMMON error intr, ret = %d", 1568 en ? "enable" : "disable", ret); 1569 1570 return ret; 1571 } 1572 1573 void 1574 hns3_config_mac_tnl_int(struct hns3_hw *hw, bool en) 1575 { 1576 struct hns3_cmd_desc desc; 1577 int ret; 1578 1579 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_TNL_INT_EN, false); 1580 if (en) 1581 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_EN); 1582 else 1583 desc.data[0] = 0; 1584 1585 desc.data[1] = rte_cpu_to_le_32(HNS3_MAC_TNL_INT_EN_MASK); 1586 1587 ret = hns3_cmd_send(hw, &desc, 1); 1588 if (ret) 1589 hns3_err(hw, "fail to %s mac tnl intr, ret = %d", 1590 en ? "enable" : "disable", ret); 1591 } 1592 1593 static int 1594 config_ppu_err_intrs(struct hns3_adapter *hns, uint32_t cmd, bool en) 1595 { 1596 struct hns3_hw *hw = &hns->hw; 1597 struct hns3_cmd_desc desc[2]; 1598 int num = 1; 1599 1600 /* configure PPU error interrupts */ 1601 switch (cmd) { 1602 case HNS3_OPC_PPU_MPF_ECC_INT_CMD: 1603 hns3_cmd_setup_basic_desc(&desc[0], cmd, false); 1604 desc[0].flag |= HNS3_CMD_FLAG_NEXT; 1605 hns3_cmd_setup_basic_desc(&desc[1], cmd, false); 1606 if (en) { 1607 desc[0].data[0] = HNS3_PPU_MPF_ABNORMAL_INT0_EN; 1608 desc[0].data[1] = HNS3_PPU_MPF_ABNORMAL_INT1_EN; 1609 desc[1].data[3] = HNS3_PPU_MPF_ABNORMAL_INT3_EN; 1610 desc[1].data[4] = HNS3_PPU_MPF_ABNORMAL_INT2_EN; 1611 } 1612 1613 desc[1].data[0] = HNS3_PPU_MPF_ABNORMAL_INT0_EN_MASK; 1614 desc[1].data[1] = HNS3_PPU_MPF_ABNORMAL_INT1_EN_MASK; 1615 desc[1].data[2] = HNS3_PPU_MPF_ABNORMAL_INT2_EN_MASK; 1616 desc[1].data[3] |= HNS3_PPU_MPF_ABNORMAL_INT3_EN_MASK; 1617 num = 2; 1618 break; 1619 case HNS3_OPC_PPU_MPF_OTHER_INT_CMD: 1620 hns3_cmd_setup_basic_desc(&desc[0], cmd, false); 1621 if (en) 1622 desc[0].data[0] = HNS3_PPU_MPF_ABNORMAL_INT2_EN2; 1623 1624 desc[0].data[2] = HNS3_PPU_MPF_ABNORMAL_INT2_EN2_MASK; 1625 break; 1626 case HNS3_OPC_PPU_PF_OTHER_INT_CMD: 1627 hns3_cmd_setup_basic_desc(&desc[0], cmd, false); 1628 if (en) 1629 desc[0].data[0] = HNS3_PPU_PF_ABNORMAL_INT_EN; 1630 1631 desc[0].data[2] = HNS3_PPU_PF_ABNORMAL_INT_EN_MASK; 1632 break; 1633 default: 1634 hns3_err(hw, 1635 "Invalid cmd(%u) to configure PPU error interrupts.", 1636 cmd); 1637 return -EINVAL; 1638 } 1639 1640 return hns3_cmd_send(hw, &desc[0], num); 1641 } 1642 1643 static int 1644 enable_ppu_err_intr(struct hns3_adapter *hns, bool en) 1645 { 1646 struct hns3_hw *hw = &hns->hw; 1647 int ret; 1648 1649 ret = config_ppu_err_intrs(hns, HNS3_OPC_PPU_MPF_ECC_INT_CMD, en); 1650 if (ret) { 1651 hns3_err(hw, "fail to %s PPU MPF ECC error intr, ret = %d", 1652 en ? "enable" : "disable", ret); 1653 return ret; 1654 } 1655 1656 ret = config_ppu_err_intrs(hns, HNS3_OPC_PPU_MPF_OTHER_INT_CMD, en); 1657 if (ret) { 1658 hns3_err(hw, "fail to %s PPU MPF other intr, ret = %d", 1659 en ? "enable" : "disable", ret); 1660 return ret; 1661 } 1662 1663 ret = config_ppu_err_intrs(hns, HNS3_OPC_PPU_PF_OTHER_INT_CMD, en); 1664 if (ret) 1665 hns3_err(hw, "fail to %s PPU PF error interrupts, ret = %d", 1666 en ? "enable" : "disable", ret); 1667 return ret; 1668 } 1669 1670 static int 1671 enable_tm_err_intr(struct hns3_adapter *hns, bool en) 1672 { 1673 struct hns3_hw *hw = &hns->hw; 1674 struct hns3_cmd_desc desc; 1675 int ret; 1676 1677 /* configure TM SCH error interrupts */ 1678 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_SCH_ECC_INT_EN, false); 1679 if (en) 1680 desc.data[0] = rte_cpu_to_le_32(HNS3_TM_SCH_ECC_ERR_INT_EN); 1681 1682 ret = hns3_cmd_send(hw, &desc, 1); 1683 if (ret) { 1684 hns3_err(hw, "fail to %s TM SCH interrupts, ret = %d", 1685 en ? "enable" : "disable", ret); 1686 return ret; 1687 } 1688 1689 /* configure TM QCN hw errors */ 1690 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_TM_QCN_MEM_INT_CFG, true); 1691 ret = hns3_cmd_send(hw, &desc, 1); 1692 if (ret) { 1693 hns3_err(hw, "fail to read TM QCN CFG status, ret = %d\n", ret); 1694 return ret; 1695 } 1696 1697 hns3_cmd_reuse_desc(&desc, false); 1698 if (en) 1699 desc.data[1] = rte_cpu_to_le_32(HNS3_TM_QCN_MEM_ERR_INT_EN); 1700 1701 ret = hns3_cmd_send(hw, &desc, 1); 1702 if (ret) 1703 hns3_err(hw, "fail to %s TM QCN mem errors, ret = %d\n", 1704 en ? "enable" : "disable", ret); 1705 1706 return ret; 1707 } 1708 1709 static int 1710 enable_common_err_intr(struct hns3_adapter *hns, bool en) 1711 { 1712 struct hns3_hw *hw = &hns->hw; 1713 struct hns3_cmd_desc desc[2]; 1714 int ret; 1715 1716 /* configure common error interrupts */ 1717 hns3_cmd_setup_basic_desc(&desc[0], HNS3_OPC_COMMON_ECC_INT_CFG, false); 1718 desc[0].flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_NEXT); 1719 hns3_cmd_setup_basic_desc(&desc[1], HNS3_OPC_COMMON_ECC_INT_CFG, false); 1720 1721 if (en) { 1722 desc[0].data[0] = 1723 rte_cpu_to_le_32(HNS3_IMP_TCM_ECC_ERR_INT_EN); 1724 desc[0].data[2] = 1725 rte_cpu_to_le_32(HNS3_CMDQ_NIC_ECC_ERR_INT_EN); 1726 desc[0].data[3] = 1727 rte_cpu_to_le_32(HNS3_IMP_RD_POISON_ERR_INT_EN); 1728 desc[0].data[4] = 1729 rte_cpu_to_le_32(HNS3_TQP_ECC_ERR_INT_EN | 1730 HNS3_MSIX_SRAM_ECC_ERR_INT_EN); 1731 desc[0].data[5] = 1732 rte_cpu_to_le_32(HNS3_IMP_ITCM4_ECC_ERR_INT_EN); 1733 } 1734 1735 desc[1].data[0] = rte_cpu_to_le_32(HNS3_IMP_TCM_ECC_ERR_INT_EN_MASK); 1736 desc[1].data[2] = rte_cpu_to_le_32(HNS3_CMDQ_NIC_ECC_ERR_INT_EN_MASK); 1737 desc[1].data[3] = rte_cpu_to_le_32(HNS3_IMP_RD_POISON_ERR_INT_EN_MASK); 1738 desc[1].data[4] = rte_cpu_to_le_32(HNS3_TQP_ECC_ERR_INT_EN_MASK | 1739 HNS3_MSIX_SRAM_ECC_ERR_INT_EN_MASK); 1740 desc[1].data[5] = rte_cpu_to_le_32(HNS3_IMP_ITCM4_ECC_ERR_INT_EN_MASK); 1741 1742 ret = hns3_cmd_send(hw, &desc[0], RTE_DIM(desc)); 1743 if (ret) 1744 hns3_err(hw, "fail to %s common err interrupts, ret = %d\n", 1745 en ? "enable" : "disable", ret); 1746 1747 return ret; 1748 } 1749 1750 static int 1751 enable_mac_err_intr(struct hns3_adapter *hns, bool en) 1752 { 1753 struct hns3_hw *hw = &hns->hw; 1754 struct hns3_cmd_desc desc; 1755 int ret; 1756 1757 /* configure MAC common error interrupts */ 1758 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_MAC_COMMON_INT_EN, false); 1759 if (en) 1760 desc.data[0] = rte_cpu_to_le_32(HNS3_MAC_COMMON_ERR_INT_EN); 1761 1762 desc.data[1] = rte_cpu_to_le_32(HNS3_MAC_COMMON_ERR_INT_EN_MASK); 1763 1764 ret = hns3_cmd_send(hw, &desc, 1); 1765 if (ret) 1766 hns3_err(hw, "fail to %s MAC COMMON error intr: %d", 1767 en ? "enable" : "disable", ret); 1768 1769 return ret; 1770 } 1771 1772 static const struct hns3_hw_blk hw_blk[] = { 1773 { 1774 .name = "IGU_EGU", 1775 .enable_err_intr = enable_igu_egu_err_intr, 1776 }, 1777 { 1778 .name = "PPP", 1779 .enable_err_intr = enable_ppp_err_intr, 1780 }, 1781 { 1782 .name = "SSU", 1783 .enable_err_intr = enable_ssu_err_intr, 1784 }, 1785 { 1786 .name = "PPU", 1787 .enable_err_intr = enable_ppu_err_intr, 1788 }, 1789 { 1790 .name = "TM", 1791 .enable_err_intr = enable_tm_err_intr, 1792 }, 1793 { 1794 .name = "COMMON", 1795 .enable_err_intr = enable_common_err_intr, 1796 }, 1797 { 1798 .name = "MAC", 1799 .enable_err_intr = enable_mac_err_intr, 1800 }, 1801 { 1802 .name = NULL, 1803 .enable_err_intr = NULL, 1804 } 1805 }; 1806 1807 int 1808 hns3_enable_hw_error_intr(struct hns3_adapter *hns, bool en) 1809 { 1810 const struct hns3_hw_blk *module = hw_blk; 1811 int ret = 0; 1812 1813 while (module->enable_err_intr) { 1814 ret = module->enable_err_intr(hns, en); 1815 if (ret) 1816 return ret; 1817 1818 module++; 1819 } 1820 1821 return ret; 1822 } 1823 1824 static enum hns3_reset_level 1825 hns3_find_highest_level(struct hns3_adapter *hns, const char *reg, 1826 const struct hns3_hw_error *err, uint32_t err_sts) 1827 { 1828 enum hns3_reset_level reset_level = HNS3_FUNC_RESET; 1829 struct hns3_hw *hw = &hns->hw; 1830 bool need_reset = false; 1831 1832 while (err->msg) { 1833 if (err->int_msk & err_sts) { 1834 hns3_warn(hw, "%s %s found [error status=0x%x]", 1835 reg, err->msg, err_sts); 1836 if (err->reset_level != HNS3_NONE_RESET && 1837 err->reset_level >= reset_level) { 1838 reset_level = err->reset_level; 1839 need_reset = true; 1840 } 1841 } 1842 err++; 1843 } 1844 if (need_reset) 1845 return reset_level; 1846 else 1847 return HNS3_NONE_RESET; 1848 } 1849 1850 static int 1851 query_num_bds(struct hns3_hw *hw, bool is_ras, uint32_t *mpf_bd_num, 1852 uint32_t *pf_bd_num) 1853 { 1854 uint32_t mpf_min_bd_num, pf_min_bd_num; 1855 uint32_t mpf_bd_num_val, pf_bd_num_val; 1856 enum hns3_opcode_type opcode; 1857 struct hns3_cmd_desc desc; 1858 int ret; 1859 1860 if (is_ras) { 1861 opcode = HNS3_OPC_QUERY_RAS_INT_STS_BD_NUM; 1862 mpf_min_bd_num = HNS3_MPF_RAS_INT_MIN_BD_NUM; 1863 pf_min_bd_num = HNS3_PF_RAS_INT_MIN_BD_NUM; 1864 } else { 1865 opcode = HNS3_OPC_QUERY_MSIX_INT_STS_BD_NUM; 1866 mpf_min_bd_num = HNS3_MPF_MSIX_INT_MIN_BD_NUM; 1867 pf_min_bd_num = HNS3_PF_MSIX_INT_MIN_BD_NUM; 1868 } 1869 1870 hns3_cmd_setup_basic_desc(&desc, opcode, true); 1871 ret = hns3_cmd_send(hw, &desc, 1); 1872 if (ret) { 1873 hns3_err(hw, "query num bds in msix failed, ret = %d", ret); 1874 return ret; 1875 } 1876 1877 mpf_bd_num_val = rte_le_to_cpu_32(desc.data[0]); 1878 pf_bd_num_val = rte_le_to_cpu_32(desc.data[1]); 1879 if (mpf_bd_num_val < mpf_min_bd_num || pf_bd_num_val < pf_min_bd_num) { 1880 hns3_err(hw, "error bd num: mpf(%u), min_mpf(%u), " 1881 "pf(%u), min_pf(%u)\n", mpf_bd_num_val, mpf_min_bd_num, 1882 pf_bd_num_val, pf_min_bd_num); 1883 return -EINVAL; 1884 } 1885 1886 *mpf_bd_num = mpf_bd_num_val; 1887 *pf_bd_num = pf_bd_num_val; 1888 1889 return 0; 1890 } 1891 1892 void 1893 hns3_intr_unregister(const struct rte_intr_handle *hdl, 1894 rte_intr_callback_fn cb_fn, void *cb_arg) 1895 { 1896 int retry_cnt = 0; 1897 int ret; 1898 1899 do { 1900 ret = rte_intr_callback_unregister(hdl, cb_fn, cb_arg); 1901 if (ret >= 0) { 1902 break; 1903 } else if (ret != -EAGAIN) { 1904 PMD_INIT_LOG(ERR, "Failed to unregister intr: %d", ret); 1905 break; 1906 } 1907 rte_delay_ms(HNS3_INTR_UNREG_FAIL_DELAY_MS); 1908 } while (retry_cnt++ < HNS3_INTR_UNREG_FAIL_RETRY_CNT); 1909 } 1910 1911 static uint32_t 1912 hns3_get_hw_error_status(struct hns3_cmd_desc *desc, uint8_t desc_offset, 1913 uint8_t data_offset) 1914 { 1915 uint32_t status; 1916 uint32_t *desc_data; 1917 1918 if (desc_offset == 0) 1919 status = rte_le_to_cpu_32(desc[desc_offset].data[data_offset]); 1920 else { 1921 desc_data = (uint32_t *)&desc[desc_offset]; 1922 status = rte_le_to_cpu_32(*(desc_data + data_offset)); 1923 } 1924 1925 return status; 1926 } 1927 1928 static int 1929 hns3_handle_hw_error(struct hns3_adapter *hns, struct hns3_cmd_desc *desc, 1930 int num, uint64_t *levels, enum hns3_hw_err_type err_type) 1931 { 1932 const struct hns3_hw_error_desc *err = pf_ras_err_tbl; 1933 enum hns3_opcode_type opcode; 1934 enum hns3_reset_level req_level; 1935 struct hns3_hw *hw = &hns->hw; 1936 uint32_t status; 1937 int ret; 1938 1939 switch (err_type) { 1940 case MPF_MSIX_ERR: 1941 err = mpf_msix_err_tbl; 1942 opcode = HNS3_OPC_QUERY_CLEAR_ALL_MPF_MSIX_INT; 1943 break; 1944 case PF_MSIX_ERR: 1945 err = pf_msix_err_tbl; 1946 opcode = HNS3_OPC_QUERY_CLEAR_ALL_PF_MSIX_INT; 1947 break; 1948 case MPF_RAS_ERR: 1949 err = mpf_ras_err_tbl; 1950 opcode = HNS3_OPC_QUERY_CLEAR_MPF_RAS_INT; 1951 break; 1952 case PF_RAS_ERR: 1953 err = pf_ras_err_tbl; 1954 opcode = HNS3_OPC_QUERY_CLEAR_PF_RAS_INT; 1955 break; 1956 default: 1957 hns3_err(hw, "error hardware err_type = %d\n", err_type); 1958 return -EINVAL; 1959 } 1960 1961 /* query all hardware errors */ 1962 hns3_cmd_setup_basic_desc(&desc[0], opcode, true); 1963 ret = hns3_cmd_send(hw, &desc[0], num); 1964 if (ret) { 1965 hns3_err(hw, "query hw err int 0x%x cmd failed, ret = %d\n", 1966 opcode, ret); 1967 return ret; 1968 } 1969 1970 /* traverses the error table and process based on the error type */ 1971 while (err->msg) { 1972 status = hns3_get_hw_error_status(desc, err->desc_offset, 1973 err->data_offset); 1974 if (status) { 1975 /* 1976 * set the reset_level or non_reset flag based on 1977 * the error type and add error statistics. here just 1978 * set the flag, the actual reset action is in 1979 * hns3_msix_process. 1980 */ 1981 req_level = hns3_find_highest_level(hns, err->msg, 1982 err->hw_err, 1983 status); 1984 hns3_atomic_set_bit(req_level, levels); 1985 } 1986 err++; 1987 } 1988 1989 /* clear all hardware errors */ 1990 hns3_cmd_reuse_desc(&desc[0], false); 1991 ret = hns3_cmd_send(hw, &desc[0], num); 1992 if (ret) 1993 hns3_err(hw, "clear all hw err int cmd failed, ret = %d\n", 1994 ret); 1995 1996 return ret; 1997 } 1998 1999 void 2000 hns3_handle_msix_error(struct hns3_adapter *hns, uint64_t *levels) 2001 { 2002 uint32_t mpf_bd_num, pf_bd_num, bd_num; 2003 struct hns3_hw *hw = &hns->hw; 2004 struct hns3_cmd_desc *desc; 2005 int ret; 2006 2007 /* query the number of bds for the MSIx int status */ 2008 ret = query_num_bds(hw, false, &mpf_bd_num, &pf_bd_num); 2009 if (ret) { 2010 hns3_err(hw, "fail to query msix int status bd num: ret = %d", 2011 ret); 2012 return; 2013 } 2014 2015 bd_num = RTE_MAX(mpf_bd_num, pf_bd_num); 2016 desc = rte_zmalloc(NULL, bd_num * sizeof(struct hns3_cmd_desc), 0); 2017 if (desc == NULL) { 2018 hns3_err(hw, 2019 "fail to zmalloc desc for handling msix error, size = %zu", 2020 bd_num * sizeof(struct hns3_cmd_desc)); 2021 return; 2022 } 2023 2024 /* handle all main PF MSIx errors */ 2025 ret = hns3_handle_hw_error(hns, desc, mpf_bd_num, levels, MPF_MSIX_ERR); 2026 if (ret) { 2027 hns3_err(hw, "fail to handle all main pf msix errors, ret = %d", 2028 ret); 2029 goto out; 2030 } 2031 2032 memset(desc, 0, bd_num * sizeof(struct hns3_cmd_desc)); 2033 2034 /* handle all PF MSIx errors */ 2035 ret = hns3_handle_hw_error(hns, desc, pf_bd_num, levels, PF_MSIX_ERR); 2036 if (ret) { 2037 hns3_err(hw, "fail to handle all pf msix errors, ret = %d", 2038 ret); 2039 goto out; 2040 } 2041 2042 out: 2043 rte_free(desc); 2044 } 2045 2046 void 2047 hns3_handle_ras_error(struct hns3_adapter *hns, uint64_t *levels) 2048 { 2049 uint32_t mpf_bd_num, pf_bd_num, bd_num; 2050 struct hns3_hw *hw = &hns->hw; 2051 struct hns3_cmd_desc *desc; 2052 uint32_t status; 2053 int ret; 2054 2055 status = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG); 2056 if ((status & HNS3_RAS_REG_NFE_MASK) == 0) 2057 return; 2058 2059 /* query the number of bds for the RAS int status */ 2060 ret = query_num_bds(hw, true, &mpf_bd_num, &pf_bd_num); 2061 if (ret) { 2062 hns3_err(hw, "fail to query ras int status bd num: ret = %d", 2063 ret); 2064 return; 2065 } 2066 2067 bd_num = RTE_MAX(mpf_bd_num, pf_bd_num); 2068 desc = rte_zmalloc(NULL, bd_num * sizeof(struct hns3_cmd_desc), 0); 2069 if (desc == NULL) { 2070 hns3_err(hw, 2071 "fail to zmalloc desc for handing ras error, size = %zu", 2072 bd_num * sizeof(struct hns3_cmd_desc)); 2073 return; 2074 } 2075 2076 /* handle all main PF RAS errors */ 2077 ret = hns3_handle_hw_error(hns, desc, mpf_bd_num, levels, MPF_RAS_ERR); 2078 if (ret) { 2079 hns3_err(hw, "fail to handle all main pf ras errors, ret = %d", 2080 ret); 2081 goto out; 2082 } 2083 2084 memset(desc, 0, bd_num * sizeof(struct hns3_cmd_desc)); 2085 2086 /* handle all PF RAS errors */ 2087 ret = hns3_handle_hw_error(hns, desc, pf_bd_num, levels, PF_RAS_ERR); 2088 if (ret) { 2089 hns3_err(hw, "fail to handle all pf ras errors, ret = %d", ret); 2090 goto out; 2091 } 2092 2093 out: 2094 rte_free(desc); 2095 } 2096 2097 int 2098 hns3_reset_init(struct hns3_hw *hw) 2099 { 2100 rte_spinlock_init(&hw->lock); 2101 hw->reset.level = HNS3_NONE_RESET; 2102 hw->reset.stage = RESET_STAGE_NONE; 2103 hw->reset.request = 0; 2104 hw->reset.pending = 0; 2105 hw->reset.resetting = 0; 2106 __atomic_store_n(&hw->reset.disable_cmd, 0, __ATOMIC_RELAXED); 2107 hw->reset.wait_data = rte_zmalloc("wait_data", 2108 sizeof(struct hns3_wait_data), 0); 2109 if (!hw->reset.wait_data) { 2110 PMD_INIT_LOG(ERR, "Failed to allocate memory for wait_data"); 2111 return -ENOMEM; 2112 } 2113 return 0; 2114 } 2115 2116 void 2117 hns3_schedule_reset(struct hns3_adapter *hns) 2118 { 2119 struct hns3_hw *hw = &hns->hw; 2120 2121 /* Reschedule the reset process after successful initialization */ 2122 if (hw->adapter_state == HNS3_NIC_UNINITIALIZED) { 2123 __atomic_store_n(&hw->reset.schedule, SCHEDULE_PENDING, 2124 __ATOMIC_RELAXED); 2125 return; 2126 } 2127 2128 if (hw->adapter_state >= HNS3_NIC_CLOSED) 2129 return; 2130 2131 /* Schedule restart alarm if it is not scheduled yet */ 2132 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) == 2133 SCHEDULE_REQUESTED) 2134 return; 2135 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) == 2136 SCHEDULE_DEFERRED) 2137 rte_eal_alarm_cancel(hw->reset.ops->reset_service, hns); 2138 __atomic_store_n(&hw->reset.schedule, SCHEDULE_REQUESTED, 2139 __ATOMIC_RELAXED); 2140 2141 rte_eal_alarm_set(SWITCH_CONTEXT_US, hw->reset.ops->reset_service, hns); 2142 } 2143 2144 void 2145 hns3_schedule_delayed_reset(struct hns3_adapter *hns) 2146 { 2147 #define DEFERRED_SCHED_US (3 * MSEC_PER_SEC * USEC_PER_MSEC) 2148 struct hns3_hw *hw = &hns->hw; 2149 2150 /* Do nothing if it is uninited or closed */ 2151 if (hw->adapter_state == HNS3_NIC_UNINITIALIZED || 2152 hw->adapter_state >= HNS3_NIC_CLOSED) { 2153 return; 2154 } 2155 2156 if (__atomic_load_n(&hw->reset.schedule, __ATOMIC_RELAXED) != 2157 SCHEDULE_NONE) 2158 return; 2159 __atomic_store_n(&hw->reset.schedule, SCHEDULE_DEFERRED, 2160 __ATOMIC_RELAXED); 2161 rte_eal_alarm_set(DEFERRED_SCHED_US, hw->reset.ops->reset_service, hns); 2162 } 2163 2164 void 2165 hns3_wait_callback(void *param) 2166 { 2167 struct hns3_wait_data *data = (struct hns3_wait_data *)param; 2168 struct hns3_adapter *hns = data->hns; 2169 struct hns3_hw *hw = &hns->hw; 2170 uint64_t msec; 2171 bool done; 2172 2173 data->count--; 2174 if (data->check_completion) { 2175 /* 2176 * Check if the current time exceeds the deadline 2177 * or a pending reset coming, or reset during close. 2178 */ 2179 msec = get_timeofday_ms(); 2180 if (msec > data->end_ms || is_reset_pending(hns) || 2181 hw->adapter_state == HNS3_NIC_CLOSING) { 2182 done = false; 2183 data->count = 0; 2184 } else 2185 done = data->check_completion(hw); 2186 } else 2187 done = true; 2188 2189 if (!done && data->count > 0) { 2190 rte_eal_alarm_set(data->interval, hns3_wait_callback, data); 2191 return; 2192 } 2193 if (done) 2194 data->result = HNS3_WAIT_SUCCESS; 2195 else { 2196 hns3_err(hw, "%s wait timeout at stage %d", 2197 reset_string[hw->reset.level], hw->reset.stage); 2198 data->result = HNS3_WAIT_TIMEOUT; 2199 } 2200 hns3_schedule_reset(hns); 2201 } 2202 2203 void 2204 hns3_notify_reset_ready(struct hns3_hw *hw, bool enable) 2205 { 2206 uint32_t reg_val; 2207 2208 reg_val = hns3_read_dev(hw, HNS3_CMDQ_TX_DEPTH_REG); 2209 if (enable) 2210 reg_val |= HNS3_NIC_SW_RST_RDY; 2211 else 2212 reg_val &= ~HNS3_NIC_SW_RST_RDY; 2213 2214 hns3_write_dev(hw, HNS3_CMDQ_TX_DEPTH_REG, reg_val); 2215 } 2216 2217 int 2218 hns3_reset_req_hw_reset(struct hns3_adapter *hns) 2219 { 2220 struct hns3_hw *hw = &hns->hw; 2221 2222 if (hw->reset.wait_data->result == HNS3_WAIT_UNKNOWN) { 2223 hw->reset.wait_data->hns = hns; 2224 hw->reset.wait_data->check_completion = NULL; 2225 hw->reset.wait_data->interval = HNS3_RESET_SYNC_US; 2226 hw->reset.wait_data->count = 1; 2227 hw->reset.wait_data->result = HNS3_WAIT_REQUEST; 2228 rte_eal_alarm_set(hw->reset.wait_data->interval, 2229 hns3_wait_callback, hw->reset.wait_data); 2230 return -EAGAIN; 2231 } else if (hw->reset.wait_data->result == HNS3_WAIT_REQUEST) 2232 return -EAGAIN; 2233 2234 /* inform hardware that preparatory work is done */ 2235 hns3_notify_reset_ready(hw, true); 2236 return 0; 2237 } 2238 2239 static void 2240 hns3_clear_reset_level(struct hns3_hw *hw, uint64_t *levels) 2241 { 2242 uint64_t merge_cnt = hw->reset.stats.merge_cnt; 2243 int64_t tmp; 2244 2245 switch (hw->reset.level) { 2246 case HNS3_IMP_RESET: 2247 hns3_atomic_clear_bit(HNS3_IMP_RESET, levels); 2248 tmp = hns3_test_and_clear_bit(HNS3_GLOBAL_RESET, levels); 2249 HNS3_CHECK_MERGE_CNT(tmp); 2250 tmp = hns3_test_and_clear_bit(HNS3_FUNC_RESET, levels); 2251 HNS3_CHECK_MERGE_CNT(tmp); 2252 break; 2253 case HNS3_GLOBAL_RESET: 2254 hns3_atomic_clear_bit(HNS3_GLOBAL_RESET, levels); 2255 tmp = hns3_test_and_clear_bit(HNS3_FUNC_RESET, levels); 2256 HNS3_CHECK_MERGE_CNT(tmp); 2257 break; 2258 case HNS3_FUNC_RESET: 2259 hns3_atomic_clear_bit(HNS3_FUNC_RESET, levels); 2260 break; 2261 case HNS3_VF_RESET: 2262 hns3_atomic_clear_bit(HNS3_VF_RESET, levels); 2263 tmp = hns3_test_and_clear_bit(HNS3_VF_PF_FUNC_RESET, levels); 2264 HNS3_CHECK_MERGE_CNT(tmp); 2265 tmp = hns3_test_and_clear_bit(HNS3_VF_FUNC_RESET, levels); 2266 HNS3_CHECK_MERGE_CNT(tmp); 2267 break; 2268 case HNS3_VF_FULL_RESET: 2269 hns3_atomic_clear_bit(HNS3_VF_FULL_RESET, levels); 2270 tmp = hns3_test_and_clear_bit(HNS3_VF_FUNC_RESET, levels); 2271 HNS3_CHECK_MERGE_CNT(tmp); 2272 break; 2273 case HNS3_VF_PF_FUNC_RESET: 2274 hns3_atomic_clear_bit(HNS3_VF_PF_FUNC_RESET, levels); 2275 tmp = hns3_test_and_clear_bit(HNS3_VF_FUNC_RESET, levels); 2276 HNS3_CHECK_MERGE_CNT(tmp); 2277 break; 2278 case HNS3_VF_FUNC_RESET: 2279 hns3_atomic_clear_bit(HNS3_VF_FUNC_RESET, levels); 2280 break; 2281 case HNS3_FLR_RESET: 2282 hns3_atomic_clear_bit(HNS3_FLR_RESET, levels); 2283 break; 2284 case HNS3_NONE_RESET: 2285 default: 2286 return; 2287 }; 2288 if (merge_cnt != hw->reset.stats.merge_cnt) 2289 hns3_warn(hw, 2290 "No need to do low-level reset after %s reset. " 2291 "merge cnt: %" PRIx64 " total merge cnt: %" PRIx64, 2292 reset_string[hw->reset.level], 2293 hw->reset.stats.merge_cnt - merge_cnt, 2294 hw->reset.stats.merge_cnt); 2295 } 2296 2297 static bool 2298 hns3_reset_err_handle(struct hns3_adapter *hns) 2299 { 2300 #define MAX_RESET_FAIL_CNT 5 2301 2302 struct hns3_hw *hw = &hns->hw; 2303 2304 if (hw->adapter_state == HNS3_NIC_CLOSING) 2305 goto reset_fail; 2306 2307 if (is_reset_pending(hns)) { 2308 hw->reset.attempts = 0; 2309 hw->reset.stats.fail_cnt++; 2310 hns3_warn(hw, "%s reset fail because new Reset is pending " 2311 "attempts:%" PRIx64, 2312 reset_string[hw->reset.level], 2313 hw->reset.stats.fail_cnt); 2314 hw->reset.level = HNS3_NONE_RESET; 2315 return true; 2316 } 2317 2318 hw->reset.attempts++; 2319 if (hw->reset.attempts < MAX_RESET_FAIL_CNT) { 2320 hns3_atomic_set_bit(hw->reset.level, &hw->reset.pending); 2321 hns3_warn(hw, "%s retry to reset attempts: %d", 2322 reset_string[hw->reset.level], 2323 hw->reset.attempts); 2324 return true; 2325 } 2326 2327 /* 2328 * Failure to reset does not mean that the network port is 2329 * completely unavailable, so cmd still needs to be initialized. 2330 * Regardless of whether the execution is successful or not, the 2331 * flow after execution must be continued. 2332 */ 2333 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED)) 2334 (void)hns3_cmd_init(hw); 2335 reset_fail: 2336 hw->reset.attempts = 0; 2337 hw->reset.stats.fail_cnt++; 2338 hns3_warn(hw, "%s reset fail fail_cnt:%" PRIx64 " success_cnt:%" PRIx64 2339 " global_cnt:%" PRIx64 " imp_cnt:%" PRIx64 2340 " request_cnt:%" PRIx64 " exec_cnt:%" PRIx64 2341 " merge_cnt:%" PRIx64 "adapter_state:%d", 2342 reset_string[hw->reset.level], hw->reset.stats.fail_cnt, 2343 hw->reset.stats.success_cnt, hw->reset.stats.global_cnt, 2344 hw->reset.stats.imp_cnt, hw->reset.stats.request_cnt, 2345 hw->reset.stats.exec_cnt, hw->reset.stats.merge_cnt, 2346 hw->adapter_state); 2347 2348 /* IMP no longer waiting the ready flag */ 2349 hns3_notify_reset_ready(hw, true); 2350 return false; 2351 } 2352 2353 static int 2354 hns3_reset_pre(struct hns3_adapter *hns) 2355 { 2356 struct hns3_hw *hw = &hns->hw; 2357 struct timeval tv; 2358 int ret; 2359 2360 if (hw->reset.stage == RESET_STAGE_NONE) { 2361 __atomic_store_n(&hns->hw.reset.resetting, 1, __ATOMIC_RELAXED); 2362 hw->reset.stage = RESET_STAGE_DOWN; 2363 ret = hw->reset.ops->stop_service(hns); 2364 gettimeofday(&tv, NULL); 2365 if (ret) { 2366 hns3_warn(hw, "Reset step1 down fail=%d time=%ld.%.6ld", 2367 ret, tv.tv_sec, tv.tv_usec); 2368 return ret; 2369 } 2370 hns3_warn(hw, "Reset step1 down success time=%ld.%.6ld", 2371 tv.tv_sec, tv.tv_usec); 2372 hw->reset.stage = RESET_STAGE_PREWAIT; 2373 } 2374 if (hw->reset.stage == RESET_STAGE_PREWAIT) { 2375 ret = hw->reset.ops->prepare_reset(hns); 2376 gettimeofday(&tv, NULL); 2377 if (ret) { 2378 hns3_warn(hw, 2379 "Reset step2 prepare wait fail=%d time=%ld.%.6ld", 2380 ret, tv.tv_sec, tv.tv_usec); 2381 return ret; 2382 } 2383 hns3_warn(hw, "Reset step2 prepare wait success time=%ld.%.6ld", 2384 tv.tv_sec, tv.tv_usec); 2385 hw->reset.stage = RESET_STAGE_REQ_HW_RESET; 2386 hw->reset.wait_data->result = HNS3_WAIT_UNKNOWN; 2387 } 2388 return 0; 2389 } 2390 2391 static int 2392 hns3_reset_post(struct hns3_adapter *hns) 2393 { 2394 #define TIMEOUT_RETRIES_CNT 5 2395 struct hns3_hw *hw = &hns->hw; 2396 struct timeval tv_delta; 2397 struct timeval tv; 2398 int ret = 0; 2399 2400 if (hw->adapter_state == HNS3_NIC_CLOSING) { 2401 hns3_warn(hw, "Don't do reset_post during closing, just uninit cmd"); 2402 hns3_cmd_uninit(hw); 2403 return -EPERM; 2404 } 2405 2406 if (hw->reset.stage == RESET_STAGE_DEV_INIT) { 2407 rte_spinlock_lock(&hw->lock); 2408 if (hw->reset.mbuf_deferred_free) { 2409 hns3_dev_release_mbufs(hns); 2410 hw->reset.mbuf_deferred_free = false; 2411 } 2412 ret = hw->reset.ops->reinit_dev(hns); 2413 rte_spinlock_unlock(&hw->lock); 2414 gettimeofday(&tv, NULL); 2415 if (ret) { 2416 hns3_warn(hw, "Reset step5 devinit fail=%d retries=%d", 2417 ret, hw->reset.retries); 2418 goto err; 2419 } 2420 hns3_warn(hw, "Reset step5 devinit success time=%ld.%.6ld", 2421 tv.tv_sec, tv.tv_usec); 2422 hw->reset.retries = 0; 2423 hw->reset.stage = RESET_STAGE_RESTORE; 2424 rte_eal_alarm_set(SWITCH_CONTEXT_US, 2425 hw->reset.ops->reset_service, hns); 2426 return -EAGAIN; 2427 } 2428 if (hw->reset.stage == RESET_STAGE_RESTORE) { 2429 rte_spinlock_lock(&hw->lock); 2430 ret = hw->reset.ops->restore_conf(hns); 2431 rte_spinlock_unlock(&hw->lock); 2432 gettimeofday(&tv, NULL); 2433 if (ret) { 2434 hns3_warn(hw, 2435 "Reset step6 restore fail=%d retries=%d", 2436 ret, hw->reset.retries); 2437 goto err; 2438 } 2439 hns3_warn(hw, "Reset step6 restore success time=%ld.%.6ld", 2440 tv.tv_sec, tv.tv_usec); 2441 hw->reset.retries = 0; 2442 hw->reset.stage = RESET_STAGE_DONE; 2443 } 2444 if (hw->reset.stage == RESET_STAGE_DONE) { 2445 /* IMP will wait ready flag before reset */ 2446 hns3_notify_reset_ready(hw, false); 2447 hns3_clear_reset_level(hw, &hw->reset.pending); 2448 __atomic_store_n(&hns->hw.reset.resetting, 0, __ATOMIC_RELAXED); 2449 hw->reset.attempts = 0; 2450 hw->reset.stats.success_cnt++; 2451 hw->reset.stage = RESET_STAGE_NONE; 2452 rte_spinlock_lock(&hw->lock); 2453 hw->reset.ops->start_service(hns); 2454 rte_spinlock_unlock(&hw->lock); 2455 gettimeofday(&tv, NULL); 2456 timersub(&tv, &hw->reset.start_time, &tv_delta); 2457 hns3_warn(hw, "%s reset done fail_cnt:%" PRIx64 2458 " success_cnt:%" PRIx64 " global_cnt:%" PRIx64 2459 " imp_cnt:%" PRIx64 " request_cnt:%" PRIx64 2460 " exec_cnt:%" PRIx64 " merge_cnt:%" PRIx64, 2461 reset_string[hw->reset.level], 2462 hw->reset.stats.fail_cnt, hw->reset.stats.success_cnt, 2463 hw->reset.stats.global_cnt, hw->reset.stats.imp_cnt, 2464 hw->reset.stats.request_cnt, hw->reset.stats.exec_cnt, 2465 hw->reset.stats.merge_cnt); 2466 hns3_warn(hw, 2467 "%s reset done delta %ld ms time=%ld.%.6ld", 2468 reset_string[hw->reset.level], 2469 tv_delta.tv_sec * MSEC_PER_SEC + 2470 tv_delta.tv_usec / USEC_PER_MSEC, 2471 tv.tv_sec, tv.tv_usec); 2472 hw->reset.level = HNS3_NONE_RESET; 2473 } 2474 return 0; 2475 2476 err: 2477 if (ret == -ETIME) { 2478 hw->reset.retries++; 2479 if (hw->reset.retries < TIMEOUT_RETRIES_CNT) { 2480 rte_eal_alarm_set(HNS3_RESET_SYNC_US, 2481 hw->reset.ops->reset_service, hns); 2482 return -EAGAIN; 2483 } 2484 } 2485 hw->reset.retries = 0; 2486 return -EIO; 2487 } 2488 2489 /* 2490 * There are three scenarios as follows: 2491 * When the reset is not in progress, the reset process starts. 2492 * During the reset process, if the reset level has not changed, 2493 * the reset process continues; otherwise, the reset process is aborted. 2494 * hw->reset.level new_level action 2495 * HNS3_NONE_RESET HNS3_XXXX_RESET start reset 2496 * HNS3_XXXX_RESET HNS3_XXXX_RESET continue reset 2497 * HNS3_LOW_RESET HNS3_HIGH_RESET abort 2498 */ 2499 int 2500 hns3_reset_process(struct hns3_adapter *hns, enum hns3_reset_level new_level) 2501 { 2502 struct hns3_hw *hw = &hns->hw; 2503 struct timeval tv_delta; 2504 struct timeval tv; 2505 int ret; 2506 2507 if (hw->reset.level == HNS3_NONE_RESET) { 2508 hw->reset.level = new_level; 2509 hw->reset.stats.exec_cnt++; 2510 gettimeofday(&hw->reset.start_time, NULL); 2511 hns3_warn(hw, "Start %s reset time=%ld.%.6ld", 2512 reset_string[hw->reset.level], 2513 hw->reset.start_time.tv_sec, 2514 hw->reset.start_time.tv_usec); 2515 } 2516 2517 if (is_reset_pending(hns)) { 2518 gettimeofday(&tv, NULL); 2519 hns3_warn(hw, 2520 "%s reset is aborted by high level time=%ld.%.6ld", 2521 reset_string[hw->reset.level], tv.tv_sec, tv.tv_usec); 2522 if (hw->reset.wait_data->result == HNS3_WAIT_REQUEST) 2523 rte_eal_alarm_cancel(hns3_wait_callback, 2524 hw->reset.wait_data); 2525 goto err; 2526 } 2527 2528 ret = hns3_reset_pre(hns); 2529 if (ret) 2530 goto err; 2531 2532 if (hw->reset.stage == RESET_STAGE_REQ_HW_RESET) { 2533 ret = hns3_reset_req_hw_reset(hns); 2534 if (ret == -EAGAIN) 2535 return ret; 2536 gettimeofday(&tv, NULL); 2537 hns3_warn(hw, 2538 "Reset step3 request IMP reset success time=%ld.%.6ld", 2539 tv.tv_sec, tv.tv_usec); 2540 hw->reset.stage = RESET_STAGE_WAIT; 2541 hw->reset.wait_data->result = HNS3_WAIT_UNKNOWN; 2542 } 2543 if (hw->reset.stage == RESET_STAGE_WAIT) { 2544 ret = hw->reset.ops->wait_hardware_ready(hns); 2545 if (ret) 2546 goto retry; 2547 gettimeofday(&tv, NULL); 2548 hns3_warn(hw, "Reset step4 reset wait success time=%ld.%.6ld", 2549 tv.tv_sec, tv.tv_usec); 2550 hw->reset.stage = RESET_STAGE_DEV_INIT; 2551 } 2552 2553 ret = hns3_reset_post(hns); 2554 if (ret) 2555 goto retry; 2556 2557 return 0; 2558 retry: 2559 if (ret == -EAGAIN) 2560 return ret; 2561 err: 2562 hns3_clear_reset_level(hw, &hw->reset.pending); 2563 if (hns3_reset_err_handle(hns)) { 2564 hw->reset.stage = RESET_STAGE_PREWAIT; 2565 hns3_schedule_reset(hns); 2566 } else { 2567 rte_spinlock_lock(&hw->lock); 2568 if (hw->reset.mbuf_deferred_free) { 2569 hns3_dev_release_mbufs(hns); 2570 hw->reset.mbuf_deferred_free = false; 2571 } 2572 rte_spinlock_unlock(&hw->lock); 2573 __atomic_store_n(&hns->hw.reset.resetting, 0, __ATOMIC_RELAXED); 2574 hw->reset.stage = RESET_STAGE_NONE; 2575 gettimeofday(&tv, NULL); 2576 timersub(&tv, &hw->reset.start_time, &tv_delta); 2577 hns3_warn(hw, "%s reset fail delta %ld ms time=%ld.%.6ld", 2578 reset_string[hw->reset.level], 2579 tv_delta.tv_sec * MSEC_PER_SEC + 2580 tv_delta.tv_usec / USEC_PER_MSEC, 2581 tv.tv_sec, tv.tv_usec); 2582 hw->reset.level = HNS3_NONE_RESET; 2583 } 2584 2585 return -EIO; 2586 } 2587 2588 /* 2589 * The reset process can only be terminated after handshake with IMP(step3), 2590 * so that IMP can complete the reset process normally. 2591 */ 2592 void 2593 hns3_reset_abort(struct hns3_adapter *hns) 2594 { 2595 struct hns3_hw *hw = &hns->hw; 2596 struct timeval tv; 2597 int i; 2598 2599 for (i = 0; i < HNS3_QUIT_RESET_CNT; i++) { 2600 if (hw->reset.level == HNS3_NONE_RESET) 2601 break; 2602 rte_delay_ms(HNS3_QUIT_RESET_DELAY_MS); 2603 } 2604 2605 /* IMP no longer waiting the ready flag */ 2606 hns3_notify_reset_ready(hw, true); 2607 2608 rte_eal_alarm_cancel(hw->reset.ops->reset_service, hns); 2609 rte_eal_alarm_cancel(hns3_wait_callback, hw->reset.wait_data); 2610 2611 if (hw->reset.level != HNS3_NONE_RESET) { 2612 gettimeofday(&tv, NULL); 2613 hns3_err(hw, "Failed to terminate reset: %s time=%ld.%.6ld", 2614 reset_string[hw->reset.level], tv.tv_sec, tv.tv_usec); 2615 } 2616 } 2617