1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018-2021 HiSilicon Limited. 3 */ 4 5 #ifndef _HNS3_CMD_H_ 6 #define _HNS3_CMD_H_ 7 8 #include <stdint.h> 9 10 #define HNS3_CMDQ_TX_TIMEOUT 30000 11 #define HNS3_CMDQ_CLEAR_WAIT_TIME 200 12 #define HNS3_CMDQ_RX_INVLD_B 0 13 #define HNS3_CMDQ_RX_OUTVLD_B 1 14 #define HNS3_CMD_DESC_ALIGNMENT 4096 15 #define HNS3_CMD_FLAG_NEXT BIT(2) 16 17 struct hns3_hw; 18 19 #define HNS3_CMD_DESC_DATA_NUM 6 20 struct hns3_cmd_desc { 21 uint16_t opcode; 22 uint16_t flag; 23 uint16_t retval; 24 uint16_t rsv; 25 uint32_t data[HNS3_CMD_DESC_DATA_NUM]; 26 }; 27 28 struct hns3_cmq_ring { 29 uint64_t desc_dma_addr; 30 struct hns3_cmd_desc *desc; 31 struct hns3_hw *hw; 32 33 uint16_t buf_size; 34 uint16_t desc_num; /* max number of cmq descriptor */ 35 uint32_t next_to_use; 36 uint32_t next_to_clean; 37 uint8_t ring_type; /* cmq ring type */ 38 rte_spinlock_t lock; /* Command queue lock */ 39 40 const void *zone; /* memory zone */ 41 }; 42 43 enum hns3_cmd_return_status { 44 HNS3_CMD_EXEC_SUCCESS = 0, 45 HNS3_CMD_NO_AUTH = 1, 46 HNS3_CMD_NOT_SUPPORTED = 2, 47 HNS3_CMD_QUEUE_FULL = 3, 48 HNS3_CMD_NEXT_ERR = 4, 49 HNS3_CMD_UNEXE_ERR = 5, 50 HNS3_CMD_PARA_ERR = 6, 51 HNS3_CMD_RESULT_ERR = 7, 52 HNS3_CMD_TIMEOUT = 8, 53 HNS3_CMD_HILINK_ERR = 9, 54 HNS3_CMD_QUEUE_ILLEGAL = 10, 55 HNS3_CMD_INVALID = 11, 56 HNS3_CMD_ROH_CHECK_FAIL = 12 57 }; 58 59 struct hns3_misc_vector { 60 uint8_t *addr; 61 int vector_irq; 62 }; 63 64 struct hns3_cmq { 65 struct hns3_cmq_ring csq; 66 struct hns3_cmq_ring crq; 67 uint16_t tx_timeout; 68 enum hns3_cmd_return_status last_status; 69 }; 70 71 enum hns3_opcode_type { 72 /* Generic commands */ 73 HNS3_OPC_QUERY_FW_VER = 0x0001, 74 HNS3_OPC_CFG_RST_TRIGGER = 0x0020, 75 HNS3_OPC_GBL_RST_STATUS = 0x0021, 76 HNS3_OPC_QUERY_FUNC_STATUS = 0x0022, 77 HNS3_OPC_QUERY_PF_RSRC = 0x0023, 78 HNS3_OPC_QUERY_VF_RSRC = 0x0024, 79 HNS3_OPC_GET_CFG_PARAM = 0x0025, 80 HNS3_OPC_PF_RST_DONE = 0x0026, 81 82 HNS3_OPC_STATS_64_BIT = 0x0030, 83 HNS3_OPC_STATS_32_BIT = 0x0031, 84 HNS3_OPC_STATS_MAC = 0x0032, 85 HNS3_OPC_QUERY_MAC_REG_NUM = 0x0033, 86 HNS3_OPC_STATS_MAC_ALL = 0x0034, 87 88 HNS3_OPC_QUERY_REG_NUM = 0x0040, 89 HNS3_OPC_QUERY_32_BIT_REG = 0x0041, 90 HNS3_OPC_QUERY_64_BIT_REG = 0x0042, 91 HNS3_OPC_DFX_BD_NUM = 0x0043, 92 HNS3_OPC_DFX_BIOS_COMMON_REG = 0x0044, 93 HNS3_OPC_DFX_SSU_REG_0 = 0x0045, 94 HNS3_OPC_DFX_SSU_REG_1 = 0x0046, 95 HNS3_OPC_DFX_IGU_EGU_REG = 0x0047, 96 HNS3_OPC_DFX_RPU_REG_0 = 0x0048, 97 HNS3_OPC_DFX_RPU_REG_1 = 0x0049, 98 HNS3_OPC_DFX_NCSI_REG = 0x004A, 99 HNS3_OPC_DFX_RTC_REG = 0x004B, 100 HNS3_OPC_DFX_PPP_REG = 0x004C, 101 HNS3_OPC_DFX_RCB_REG = 0x004D, 102 HNS3_OPC_DFX_TQP_REG = 0x004E, 103 HNS3_OPC_DFX_SSU_REG_2 = 0x004F, 104 105 HNS3_OPC_QUERY_DEV_SPECS = 0x0050, 106 107 HNS3_OPC_SSU_DROP_REG = 0x0065, 108 109 /* MAC command */ 110 HNS3_OPC_CONFIG_MAC_MODE = 0x0301, 111 HNS3_OPC_CONFIG_AN_MODE = 0x0304, 112 HNS3_OPC_QUERY_LINK_STATUS = 0x0307, 113 HNS3_OPC_CONFIG_MAX_FRM_SIZE = 0x0308, 114 HNS3_OPC_CONFIG_SPEED_DUP = 0x0309, 115 HNS3_OPC_QUERY_MAC_TNL_INT = 0x0310, 116 HNS3_OPC_MAC_TNL_INT_EN = 0x0311, 117 HNS3_OPC_CLEAR_MAC_TNL_INT = 0x0312, 118 HNS3_OPC_CONFIG_FEC_MODE = 0x031A, 119 120 /* PTP command */ 121 HNS3_OPC_PTP_INT_EN = 0x0501, 122 HNS3_OPC_CFG_PTP_MODE = 0x0507, 123 124 /* PFC/Pause commands */ 125 HNS3_OPC_CFG_MAC_PAUSE_EN = 0x0701, 126 HNS3_OPC_CFG_PFC_PAUSE_EN = 0x0702, 127 HNS3_OPC_CFG_MAC_PARA = 0x0703, 128 HNS3_OPC_CFG_PFC_PARA = 0x0704, 129 HNS3_OPC_QUERY_MAC_TX_PKT_CNT = 0x0705, 130 HNS3_OPC_QUERY_MAC_RX_PKT_CNT = 0x0706, 131 HNS3_OPC_QUERY_PFC_TX_PKT_CNT = 0x0707, 132 HNS3_OPC_QUERY_PFC_RX_PKT_CNT = 0x0708, 133 HNS3_OPC_PRI_TO_TC_MAPPING = 0x0709, 134 HNS3_OPC_QOS_MAP = 0x070A, 135 136 /* ETS/scheduler commands */ 137 HNS3_OPC_TM_PG_TO_PRI_LINK = 0x0804, 138 HNS3_OPC_TM_QS_TO_PRI_LINK = 0x0805, 139 HNS3_OPC_TM_NQ_TO_QS_LINK = 0x0806, 140 HNS3_OPC_TM_RQ_TO_QS_LINK = 0x0807, 141 HNS3_OPC_TM_PORT_WEIGHT = 0x0808, 142 HNS3_OPC_TM_PG_WEIGHT = 0x0809, 143 HNS3_OPC_TM_QS_WEIGHT = 0x080A, 144 HNS3_OPC_TM_PRI_WEIGHT = 0x080B, 145 HNS3_OPC_TM_PRI_C_SHAPPING = 0x080C, 146 HNS3_OPC_TM_PRI_P_SHAPPING = 0x080D, 147 HNS3_OPC_TM_PG_C_SHAPPING = 0x080E, 148 HNS3_OPC_TM_PG_P_SHAPPING = 0x080F, 149 HNS3_OPC_TM_PORT_SHAPPING = 0x0810, 150 HNS3_OPC_TM_PG_SCH_MODE_CFG = 0x0812, 151 HNS3_OPC_TM_PRI_SCH_MODE_CFG = 0x0813, 152 HNS3_OPC_TM_QS_SCH_MODE_CFG = 0x0814, 153 HNS3_OPC_TM_BP_TO_QSET_MAPPING = 0x0815, 154 HNS3_OPC_ETS_TC_WEIGHT = 0x0843, 155 HNS3_OPC_QSET_DFX_STS = 0x0844, 156 HNS3_OPC_PRI_DFX_STS = 0x0845, 157 HNS3_OPC_PG_DFX_STS = 0x0846, 158 HNS3_OPC_PORT_DFX_STS = 0x0847, 159 HNS3_OPC_SCH_NQ_CNT = 0x0848, 160 HNS3_OPC_SCH_RQ_CNT = 0x0849, 161 HNS3_OPC_TM_INTERNAL_STS = 0x0850, 162 HNS3_OPC_TM_INTERNAL_CNT = 0x0851, 163 HNS3_OPC_TM_INTERNAL_STS_1 = 0x0852, 164 165 HNS3_OPC_TM_PORT_LIMIT_RATE = 0x0870, 166 HNS3_OPC_TM_TC_LIMIT_RATE = 0x0871, 167 168 /* Mailbox cmd */ 169 HNS3_OPC_MBX_VF_TO_PF = 0x2001, 170 171 /* Packet buffer allocate commands */ 172 HNS3_OPC_TX_BUFF_ALLOC = 0x0901, 173 HNS3_OPC_RX_PRIV_BUFF_ALLOC = 0x0902, 174 HNS3_OPC_RX_PRIV_WL_ALLOC = 0x0903, 175 HNS3_OPC_RX_COM_THRD_ALLOC = 0x0904, 176 HNS3_OPC_RX_COM_WL_ALLOC = 0x0905, 177 178 /* TQP management command */ 179 HNS3_OPC_SET_TQP_MAP = 0x0A01, 180 181 /* TQP commands */ 182 HNS3_OPC_QUERY_TX_STATUS = 0x0B03, 183 HNS3_OPC_QUERY_RX_STATUS = 0x0B13, 184 HNS3_OPC_CFG_COM_TQP_QUEUE = 0x0B20, 185 HNS3_OPC_RESET_TQP_QUEUE = 0x0B22, 186 HNS3_OPC_RESET_TQP_QUEUE_INDEP = 0x0B23, 187 188 /* TSO command */ 189 HNS3_OPC_TSO_GENERIC_CONFIG = 0x0C01, 190 HNS3_OPC_GRO_GENERIC_CONFIG = 0x0C10, 191 192 /* RSS commands */ 193 HNS3_OPC_RSS_GENERIC_CONFIG = 0x0D01, 194 HNS3_OPC_RSS_INPUT_TUPLE = 0x0D02, 195 HNS3_OPC_RSS_INDIR_TABLE = 0x0D07, 196 HNS3_OPC_RSS_TC_MODE = 0x0D08, 197 198 /* Promisuous mode command */ 199 HNS3_OPC_CFG_PROMISC_MODE = 0x0E01, 200 201 /* Vlan offload commands */ 202 HNS3_OPC_VLAN_PORT_TX_CFG = 0x0F01, 203 HNS3_OPC_VLAN_PORT_RX_CFG = 0x0F02, 204 205 /* MAC commands */ 206 HNS3_OPC_MAC_VLAN_ADD = 0x1000, 207 HNS3_OPC_MAC_VLAN_REMOVE = 0x1001, 208 HNS3_OPC_MAC_VLAN_TYPE_ID = 0x1002, 209 HNS3_OPC_MAC_VLAN_INSERT = 0x1003, 210 HNS3_OPC_MAC_VLAN_ALLOCATE = 0x1004, 211 HNS3_OPC_MAC_ETHTYPE_ADD = 0x1010, 212 213 /* VLAN commands */ 214 HNS3_OPC_VLAN_FILTER_CTRL = 0x1100, 215 HNS3_OPC_VLAN_FILTER_PF_CFG = 0x1101, 216 HNS3_OPC_VLAN_FILTER_VF_CFG = 0x1102, 217 218 /* Flow Director command */ 219 HNS3_OPC_FD_MODE_CTRL = 0x1200, 220 HNS3_OPC_FD_GET_ALLOCATION = 0x1201, 221 HNS3_OPC_FD_KEY_CONFIG = 0x1202, 222 HNS3_OPC_FD_TCAM_OP = 0x1203, 223 HNS3_OPC_FD_AD_OP = 0x1204, 224 HNS3_OPC_FD_COUNTER_OP = 0x1205, 225 226 /* Clear hardware state command */ 227 HNS3_OPC_CLEAR_HW_STATE = 0x700B, 228 229 /* Firmware stats command */ 230 HNS3_OPC_FIRMWARE_COMPAT_CFG = 0x701A, 231 /* Firmware control phy command */ 232 HNS3_OPC_PHY_PARAM_CFG = 0x7025, 233 234 /* SFP command */ 235 HNS3_OPC_GET_SFP_EEPROM = 0x7100, 236 HNS3_OPC_GET_SFP_EXIST = 0x7101, 237 HNS3_OPC_GET_SFP_INFO = 0x7104, 238 239 /* Interrupts commands */ 240 HNS3_OPC_ADD_RING_TO_VECTOR = 0x1503, 241 HNS3_OPC_DEL_RING_TO_VECTOR = 0x1504, 242 243 /* Error INT commands */ 244 HNS3_OPC_MAC_COMMON_INT_EN = 0x030E, 245 HNS3_OPC_TM_SCH_ECC_INT_EN = 0x0829, 246 HNS3_OPC_SSU_ECC_INT_CMD = 0x0989, 247 HNS3_OPC_SSU_COMMON_INT_CMD = 0x098C, 248 HNS3_OPC_PPU_MPF_ECC_INT_CMD = 0x0B40, 249 HNS3_OPC_PPU_MPF_OTHER_INT_CMD = 0x0B41, 250 HNS3_OPC_PPU_PF_OTHER_INT_CMD = 0x0B42, 251 HNS3_OPC_COMMON_ECC_INT_CFG = 0x1505, 252 HNS3_OPC_QUERY_RAS_INT_STS_BD_NUM = 0x1510, 253 HNS3_OPC_QUERY_CLEAR_MPF_RAS_INT = 0x1511, 254 HNS3_OPC_QUERY_CLEAR_PF_RAS_INT = 0x1512, 255 HNS3_OPC_QUERY_MSIX_INT_STS_BD_NUM = 0x1513, 256 HNS3_OPC_QUERY_CLEAR_ALL_MPF_MSIX_INT = 0x1514, 257 HNS3_OPC_QUERY_CLEAR_ALL_PF_MSIX_INT = 0x1515, 258 HNS3_OPC_QUERY_ALL_ERR_BD_NUM = 0x1516, 259 HNS3_OPC_QUERY_ALL_ERR_INFO = 0x1517, 260 HNS3_OPC_IGU_EGU_TNL_INT_EN = 0x1803, 261 HNS3_OPC_IGU_COMMON_INT_EN = 0x1806, 262 HNS3_OPC_TM_QCN_MEM_INT_CFG = 0x1A14, 263 HNS3_OPC_PPP_CMD0_INT_CMD = 0x2100, 264 HNS3_OPC_PPP_CMD1_INT_CMD = 0x2101, 265 HNS3_OPC_NCSI_INT_EN = 0x2401, 266 }; 267 268 #define HNS3_CMD_FLAG_IN BIT(0) 269 #define HNS3_CMD_FLAG_OUT BIT(1) 270 #define HNS3_CMD_FLAG_NEXT BIT(2) 271 #define HNS3_CMD_FLAG_WR BIT(3) 272 #define HNS3_CMD_FLAG_NO_INTR BIT(4) 273 #define HNS3_CMD_FLAG_ERR_INTR BIT(5) 274 275 #define HNS3_MPF_RAS_INT_MIN_BD_NUM 10 276 #define HNS3_PF_RAS_INT_MIN_BD_NUM 4 277 #define HNS3_MPF_MSIX_INT_MIN_BD_NUM 10 278 #define HNS3_PF_MSIX_INT_MIN_BD_NUM 4 279 280 #define HNS3_BUF_SIZE_UNIT 256 281 #define HNS3_BUF_MUL_BY 2 282 #define HNS3_BUF_DIV_BY 2 283 #define NEED_RESERVE_TC_NUM 2 284 #define BUF_MAX_PERCENT 100 285 #define BUF_RESERVE_PERCENT 90 286 287 #define HNS3_MAX_TC_NUM 8 288 #define HNS3_TC0_PRI_BUF_EN_B 15 /* Bit 15 indicate enable or not */ 289 #define HNS3_BUF_UNIT_S 7 /* Buf size is united by 128 bytes */ 290 #define HNS3_TX_BUFF_RSV_NUM 8 291 struct hns3_tx_buff_alloc_cmd { 292 uint16_t tx_pkt_buff[HNS3_MAX_TC_NUM]; 293 uint8_t tx_buff_rsv[HNS3_TX_BUFF_RSV_NUM]; 294 }; 295 296 struct hns3_rx_priv_buff_cmd { 297 uint16_t buf_num[HNS3_MAX_TC_NUM]; 298 uint16_t shared_buf; 299 uint8_t rsv[6]; 300 }; 301 302 #define HNS3_FW_VERSION_BYTE3_S 24 303 #define HNS3_FW_VERSION_BYTE3_M GENMASK(31, 24) 304 #define HNS3_FW_VERSION_BYTE2_S 16 305 #define HNS3_FW_VERSION_BYTE2_M GENMASK(23, 16) 306 #define HNS3_FW_VERSION_BYTE1_S 8 307 #define HNS3_FW_VERSION_BYTE1_M GENMASK(15, 8) 308 #define HNS3_FW_VERSION_BYTE0_S 0 309 #define HNS3_FW_VERSION_BYTE0_M GENMASK(7, 0) 310 311 enum HNS3_CAPS_BITS { 312 /* 313 * The following capability index definitions must be the same as those 314 * of the firmware. 315 */ 316 HNS3_CAPS_FD_QUEUE_REGION_B = 2, 317 HNS3_CAPS_PTP_B, 318 HNS3_CAPS_TX_PUSH_B = 6, 319 HNS3_CAPS_PHY_IMP_B = 7, 320 HNS3_CAPS_TQP_TXRX_INDEP_B, 321 HNS3_CAPS_HW_PAD_B, 322 HNS3_CAPS_STASH_B, 323 HNS3_CAPS_UDP_TUNNEL_CSUM_B, 324 HNS3_CAPS_RAS_IMP_B, 325 HNS3_CAPS_RXD_ADV_LAYOUT_B = 15, 326 HNS3_CAPS_TM_B = 17, 327 }; 328 329 /* Capabilities of VF dependent on the PF */ 330 enum HNS3VF_CAPS_BITS { 331 /* 332 * The following capability index definitions must be the same as those 333 * in kernel side PF. 334 */ 335 HNS3VF_CAPS_VLAN_FLT_MOD_B = 0, 336 }; 337 338 enum HNS3_API_CAP_BITS { 339 HNS3_API_CAP_FLEX_RSS_TBL_B, 340 }; 341 342 #define HNS3_QUERY_CAP_LENGTH 3 343 struct hns3_query_version_cmd { 344 uint32_t firmware; 345 uint32_t hardware; 346 uint32_t api_caps; 347 uint32_t caps[HNS3_QUERY_CAP_LENGTH]; /* capabilities of device */ 348 }; 349 350 #define HNS3_RX_PRIV_EN_B 15 351 #define HNS3_TC_NUM_ONE_DESC 4 352 struct hns3_priv_wl { 353 uint16_t high; 354 uint16_t low; 355 }; 356 357 struct hns3_rx_priv_wl_buf { 358 struct hns3_priv_wl tc_wl[HNS3_TC_NUM_ONE_DESC]; 359 }; 360 361 struct hns3_rx_com_thrd { 362 struct hns3_priv_wl com_thrd[HNS3_TC_NUM_ONE_DESC]; 363 }; 364 365 struct hns3_rx_com_wl { 366 struct hns3_priv_wl com_wl; 367 }; 368 369 struct hns3_waterline { 370 uint32_t low; 371 uint32_t high; 372 }; 373 374 struct hns3_tc_thrd { 375 uint32_t low; 376 uint32_t high; 377 }; 378 379 struct hns3_priv_buf { 380 struct hns3_waterline wl; /* Waterline for low and high */ 381 uint32_t buf_size; /* TC private buffer size */ 382 uint32_t tx_buf_size; 383 uint32_t enable; /* Enable TC private buffer or not */ 384 }; 385 386 struct hns3_shared_buf { 387 struct hns3_waterline self; 388 struct hns3_tc_thrd tc_thrd[HNS3_MAX_TC_NUM]; 389 uint32_t buf_size; 390 }; 391 392 struct hns3_pkt_buf_alloc { 393 struct hns3_priv_buf priv_buf[HNS3_MAX_TC_NUM]; 394 struct hns3_shared_buf s_buf; 395 }; 396 397 #define HNS3_RX_COM_WL_EN_B 15 398 struct hns3_rx_com_wl_buf_cmd { 399 uint16_t high_wl; 400 uint16_t low_wl; 401 uint8_t rsv[20]; 402 }; 403 404 #define HNS3_RX_PKT_EN_B 15 405 struct hns3_rx_pkt_buf_cmd { 406 uint16_t high_pkt; 407 uint16_t low_pkt; 408 uint8_t rsv[20]; 409 }; 410 411 #define HNS3_PF_STATE_DONE_B 0 412 #define HNS3_PF_STATE_MAIN_B 1 413 #define HNS3_PF_STATE_BOND_B 2 414 #define HNS3_PF_STATE_MAC_N_B 6 415 #define HNS3_PF_MAC_NUM_MASK 0x3 416 #define HNS3_PF_STATE_MAIN BIT(HNS3_PF_STATE_MAIN_B) 417 #define HNS3_PF_STATE_DONE BIT(HNS3_PF_STATE_DONE_B) 418 #define HNS3_VF_RST_STATE_NUM 4 419 struct hns3_func_status_cmd { 420 uint32_t vf_rst_state[HNS3_VF_RST_STATE_NUM]; 421 uint8_t pf_state; 422 uint8_t mac_id; 423 uint8_t rsv1; 424 uint8_t pf_cnt_in_mac; 425 uint8_t pf_num; 426 uint8_t vf_num; 427 uint8_t rsv[2]; 428 }; 429 430 #define HNS3_PF_VEC_NUM_S 0 431 #define HNS3_PF_VEC_NUM_M GENMASK(15, 0) 432 #define HNS3_MIN_VECTOR_NUM 2 /* one for msi-x, another for IO */ 433 struct hns3_pf_res_cmd { 434 uint16_t tqp_num; 435 uint16_t buf_size; 436 uint16_t msixcap_localid_ba_nic; 437 uint16_t nic_pf_intr_vector_number; 438 uint16_t roce_pf_intr_vector_number; 439 uint16_t pf_own_fun_number; 440 uint16_t tx_buf_size; 441 uint16_t dv_buf_size; 442 /* number of queues that exceed 1024 */ 443 uint16_t ext_tqp_num; 444 uint16_t roh_pf_intr_vector_number; 445 uint32_t rsv[1]; 446 }; 447 448 #define HNS3_VF_VEC_NUM_S 0 449 #define HNS3_VF_VEC_NUM_M GENMASK(7, 0) 450 struct hns3_vf_res_cmd { 451 uint16_t tqp_num; 452 uint16_t reserved; 453 uint16_t msixcap_localid_ba_nic; 454 uint16_t msixcap_localid_ba_rocee; 455 uint16_t vf_intr_vector_number; 456 uint16_t rsv[7]; 457 }; 458 459 #define HNS3_UMV_SPC_ALC_B 0 460 struct hns3_umv_spc_alc_cmd { 461 uint8_t allocate; 462 uint8_t rsv1[3]; 463 uint32_t space_size; 464 uint8_t rsv2[16]; 465 }; 466 467 #define HNS3_CFG_OFFSET_S 0 468 #define HNS3_CFG_OFFSET_M GENMASK(19, 0) 469 #define HNS3_CFG_RD_LEN_S 24 470 #define HNS3_CFG_RD_LEN_M GENMASK(27, 24) 471 #define HNS3_CFG_RD_LEN_BYTES 16 472 #define HNS3_CFG_RD_LEN_UNIT 4 473 474 #define HNS3_CFG_TC_NUM_S 8 475 #define HNS3_CFG_TC_NUM_M GENMASK(15, 8) 476 #define HNS3_CFG_TQP_DESC_N_S 16 477 #define HNS3_CFG_TQP_DESC_N_M GENMASK(31, 16) 478 #define HNS3_CFG_PHY_ADDR_S 0 479 #define HNS3_CFG_PHY_ADDR_M GENMASK(7, 0) 480 #define HNS3_CFG_MEDIA_TP_S 8 481 #define HNS3_CFG_MEDIA_TP_M GENMASK(15, 8) 482 #define HNS3_CFG_RX_BUF_LEN_S 16 483 #define HNS3_CFG_RX_BUF_LEN_M GENMASK(31, 16) 484 #define HNS3_CFG_MAC_ADDR_H_S 0 485 #define HNS3_CFG_MAC_ADDR_H_M GENMASK(15, 0) 486 #define HNS3_CFG_DEFAULT_SPEED_S 16 487 #define HNS3_CFG_DEFAULT_SPEED_M GENMASK(23, 16) 488 #define HNS3_CFG_RSS_SIZE_S 24 489 #define HNS3_CFG_RSS_SIZE_M GENMASK(31, 24) 490 #define HNS3_CFG_SPEED_ABILITY_S 0 491 #define HNS3_CFG_SPEED_ABILITY_M GENMASK(7, 0) 492 #define HNS3_CFG_UMV_TBL_SPACE_S 16 493 #define HNS3_CFG_UMV_TBL_SPACE_M GENMASK(31, 16) 494 #define HNS3_CFG_EXT_RSS_SIZE_S 0 495 #define HNS3_CFG_EXT_RSS_SIZE_M GENMASK(3, 0) 496 497 #define HNS3_ACCEPT_TAG1_B 0 498 #define HNS3_ACCEPT_UNTAG1_B 1 499 #define HNS3_PORT_INS_TAG1_EN_B 2 500 #define HNS3_PORT_INS_TAG2_EN_B 3 501 #define HNS3_CFG_NIC_ROCE_SEL_B 4 502 #define HNS3_ACCEPT_TAG2_B 5 503 #define HNS3_ACCEPT_UNTAG2_B 6 504 #define HNS3_TAG_SHIFT_MODE_EN_B 7 505 506 #define HNS3_REM_TAG1_EN_B 0 507 #define HNS3_REM_TAG2_EN_B 1 508 #define HNS3_SHOW_TAG1_EN_B 2 509 #define HNS3_SHOW_TAG2_EN_B 3 510 #define HNS3_DISCARD_TAG1_EN_B 5 511 #define HNS3_DISCARD_TAG2_EN_B 6 512 513 /* Factor used to calculate offset and bitmap of VF num */ 514 #define HNS3_VF_NUM_PER_CMD 64 515 #define HNS3_VF_NUM_PER_BYTE 8 516 517 struct hns3_cfg_param_cmd { 518 uint32_t offset; 519 uint32_t rsv; 520 uint32_t param[4]; 521 }; 522 523 #define HNS3_VPORT_VTAG_RX_CFG_CMD_VF_BITMAP_NUM 8 524 struct hns3_vport_vtag_rx_cfg_cmd { 525 uint8_t vport_vlan_cfg; 526 uint8_t vf_offset; 527 uint8_t rsv1[6]; 528 uint8_t vf_bitmap[HNS3_VPORT_VTAG_RX_CFG_CMD_VF_BITMAP_NUM]; 529 uint8_t rsv2[8]; 530 }; 531 532 struct hns3_vport_vtag_tx_cfg_cmd { 533 uint8_t vport_vlan_cfg; 534 uint8_t vf_offset; 535 uint8_t rsv1[2]; 536 uint16_t def_vlan_tag1; 537 uint16_t def_vlan_tag2; 538 uint8_t vf_bitmap[8]; 539 uint8_t rsv2[8]; 540 }; 541 542 543 struct hns3_vlan_filter_ctrl_cmd { 544 uint8_t vlan_type; 545 uint8_t vlan_fe; 546 uint8_t rsv1[2]; 547 uint8_t vf_id; 548 uint8_t rsv2[19]; 549 }; 550 551 #define HNS3_VLAN_OFFSET_BITMAP_NUM 20 552 struct hns3_vlan_filter_pf_cfg_cmd { 553 uint8_t vlan_offset; 554 uint8_t vlan_cfg; 555 uint8_t rsv[2]; 556 uint8_t vlan_offset_bitmap[HNS3_VLAN_OFFSET_BITMAP_NUM]; 557 }; 558 559 #define HNS3_VLAN_FILTER_VF_CFG_CMD_VF_BITMAP_NUM 16 560 struct hns3_vlan_filter_vf_cfg_cmd { 561 uint16_t vlan_id; 562 uint8_t resp_code; 563 uint8_t rsv; 564 uint8_t vlan_cfg; 565 uint8_t rsv1[3]; 566 uint8_t vf_bitmap[HNS3_VLAN_FILTER_VF_CFG_CMD_VF_BITMAP_NUM]; 567 }; 568 569 struct hns3_tx_vlan_type_cfg_cmd { 570 uint16_t ot_vlan_type; 571 uint16_t in_vlan_type; 572 uint8_t rsv[20]; 573 }; 574 575 struct hns3_rx_vlan_type_cfg_cmd { 576 uint16_t ot_fst_vlan_type; 577 uint16_t ot_sec_vlan_type; 578 uint16_t in_fst_vlan_type; 579 uint16_t in_sec_vlan_type; 580 uint8_t rsv[16]; 581 }; 582 583 #define HNS3_TSO_MSS_MIN_S 0 584 #define HNS3_TSO_MSS_MIN_M GENMASK(13, 0) 585 586 #define HNS3_TSO_MSS_MAX_S 16 587 #define HNS3_TSO_MSS_MAX_M GENMASK(29, 16) 588 589 struct hns3_cfg_tso_status_cmd { 590 rte_le16_t tso_mss_min; 591 rte_le16_t tso_mss_max; 592 uint8_t rsv[20]; 593 }; 594 595 #define HNS3_GRO_EN_B 0 596 struct hns3_cfg_gro_status_cmd { 597 rte_le16_t gro_en; 598 uint8_t rsv[22]; 599 }; 600 601 #define HNS3_TSO_MSS_MIN 256 602 #define HNS3_TSO_MSS_MAX 9668 603 604 #define HNS3_RSS_HASH_KEY_OFFSET_B 4 605 606 #define HNS3_RSS_CFG_TBL_SIZE 16 607 #define HNS3_RSS_HASH_KEY_NUM 16 608 /* Configure the algorithm mode and Hash Key, opcode:0x0D01 */ 609 struct hns3_rss_generic_config_cmd { 610 /* Hash_algorithm(8.0~8.3), hash_key_offset(8.4~8.7) */ 611 uint8_t hash_config; 612 uint8_t rsv[7]; 613 uint8_t hash_key[HNS3_RSS_HASH_KEY_NUM]; 614 }; 615 616 /* Configure the tuple selection for RSS hash input, opcode:0x0D02 */ 617 struct hns3_rss_input_tuple_cmd { 618 uint64_t tuple_field; 619 uint8_t rsv[16]; 620 }; 621 622 #define HNS3_RSS_CFG_TBL_SIZE 16 623 #define HNS3_RSS_CFG_TBL_SIZE_H 4 624 #define HNS3_RSS_CFG_TBL_BW_H 2 625 #define HNS3_RSS_CFG_TBL_BW_L 8 626 627 /* Configure the indirection table, opcode:0x0D07 */ 628 struct hns3_rss_indirection_table_cmd { 629 uint16_t start_table_index; /* Bit3~0 must be 0x0. */ 630 uint16_t rss_set_bitmap; 631 uint8_t rss_result_h[HNS3_RSS_CFG_TBL_SIZE_H]; 632 uint8_t rss_result_l[HNS3_RSS_CFG_TBL_SIZE]; 633 }; 634 635 #define HNS3_RSS_TC_OFFSET_S 0 636 #define HNS3_RSS_TC_OFFSET_M GENMASK(10, 0) 637 #define HNS3_RSS_TC_SIZE_MSB_S 11 638 #define HNS3_RSS_TC_SIZE_MSB_OFFSET 3 639 #define HNS3_RSS_TC_SIZE_S 12 640 #define HNS3_RSS_TC_SIZE_M GENMASK(14, 12) 641 #define HNS3_RSS_TC_VALID_B 15 642 643 /* Configure the tc_size and tc_offset, opcode:0x0D08 */ 644 struct hns3_rss_tc_mode_cmd { 645 uint16_t rss_tc_mode[HNS3_MAX_TC_NUM]; 646 uint8_t rsv[8]; 647 }; 648 649 #define HNS3_LINK_STATUS_UP_B 0 650 #define HNS3_LINK_STATUS_UP_M BIT(HNS3_LINK_STATUS_UP_B) 651 struct hns3_link_status_cmd { 652 uint8_t status; 653 uint8_t rsv[23]; 654 }; 655 656 struct hns3_promisc_param { 657 uint8_t vf_id; 658 uint8_t enable; 659 }; 660 661 #define HNS3_PROMISC_TX_EN_B BIT(4) 662 #define HNS3_PROMISC_RX_EN_B BIT(5) 663 #define HNS3_PROMISC_EN_B 1 664 #define HNS3_PROMISC_EN_ALL 0x7 665 #define HNS3_PROMISC_EN_UC 0x1 666 #define HNS3_PROMISC_EN_MC 0x2 667 #define HNS3_PROMISC_EN_BC 0x4 668 struct hns3_promisc_cfg_cmd { 669 uint8_t flag; 670 uint8_t vf_id; 671 uint16_t rsv0; 672 uint8_t rsv1[20]; 673 }; 674 675 enum hns3_promisc_type { 676 HNS3_UNICAST = 1, 677 HNS3_MULTICAST = 2, 678 HNS3_BROADCAST = 3, 679 }; 680 681 #define HNS3_LINK_EVENT_REPORT_EN_B 0 682 #define HNS3_NCSI_ERROR_REPORT_EN_B 1 683 #define HNS3_FIRMWARE_PHY_DRIVER_EN_B 2 684 struct hns3_firmware_compat_cmd { 685 uint32_t compat; 686 uint8_t rsv[20]; 687 }; 688 689 /* Bitmap flags in supported, advertising and lp_advertising */ 690 #define HNS3_PHY_LINK_SPEED_10M_HD_BIT BIT(0) 691 #define HNS3_PHY_LINK_SPEED_10M_BIT BIT(1) 692 #define HNS3_PHY_LINK_SPEED_100M_HD_BIT BIT(2) 693 #define HNS3_PHY_LINK_SPEED_100M_BIT BIT(3) 694 #define HNS3_PHY_LINK_SPEED_1000M_BIT BIT(5) 695 #define HNS3_PHY_LINK_MODE_AUTONEG_BIT BIT(6) 696 #define HNS3_PHY_LINK_MODE_PAUSE_BIT BIT(13) 697 #define HNS3_PHY_LINK_MODE_ASYM_PAUSE_BIT BIT(14) 698 699 #define HNS3_PHY_PARAM_CFG_BD_NUM 2 700 struct hns3_phy_params_bd0_cmd { 701 uint32_t speed; 702 #define HNS3_PHY_DUPLEX_CFG_B 0 703 uint8_t duplex; 704 #define HNS3_PHY_AUTONEG_CFG_B 0 705 uint8_t autoneg; 706 uint8_t eth_tp_mdix; 707 uint8_t eth_tp_mdix_ctrl; 708 uint8_t port; 709 uint8_t transceiver; 710 uint8_t phy_address; 711 uint8_t rsv; 712 uint32_t supported; 713 uint32_t advertising; 714 uint32_t lp_advertising; 715 }; 716 717 struct hns3_phy_params_bd1_cmd { 718 uint8_t master_slave_cfg; 719 uint8_t master_slave_state; 720 uint8_t rsv1[2]; 721 uint32_t rsv2[5]; 722 }; 723 724 #define HNS3_MAC_TX_EN_B 6 725 #define HNS3_MAC_RX_EN_B 7 726 #define HNS3_MAC_PAD_TX_B 11 727 #define HNS3_MAC_PAD_RX_B 12 728 #define HNS3_MAC_1588_TX_B 13 729 #define HNS3_MAC_1588_RX_B 14 730 #define HNS3_MAC_APP_LP_B 15 731 #define HNS3_MAC_LINE_LP_B 16 732 #define HNS3_MAC_FCS_TX_B 17 733 #define HNS3_MAC_RX_OVERSIZE_TRUNCATE_B 18 734 #define HNS3_MAC_RX_FCS_STRIP_B 19 735 #define HNS3_MAC_RX_FCS_B 20 736 #define HNS3_MAC_TX_UNDER_MIN_ERR_B 21 737 #define HNS3_MAC_TX_OVERSIZE_TRUNCATE_B 22 738 739 struct hns3_config_mac_mode_cmd { 740 uint32_t txrx_pad_fcs_loop_en; 741 uint8_t rsv[20]; 742 }; 743 744 #define HNS3_CFG_SPEED_10M 6 745 #define HNS3_CFG_SPEED_100M 7 746 #define HNS3_CFG_SPEED_1G 0 747 #define HNS3_CFG_SPEED_10G 1 748 #define HNS3_CFG_SPEED_25G 2 749 #define HNS3_CFG_SPEED_40G 3 750 #define HNS3_CFG_SPEED_50G 4 751 #define HNS3_CFG_SPEED_100G 5 752 #define HNS3_CFG_SPEED_200G 8 753 754 #define HNS3_CFG_SPEED_S 0 755 #define HNS3_CFG_SPEED_M GENMASK(5, 0) 756 #define HNS3_CFG_DUPLEX_B 7 757 #define HNS3_CFG_DUPLEX_M BIT(HNS3_CFG_DUPLEX_B) 758 759 #define HNS3_CFG_MAC_SPEED_CHANGE_EN_B 0 760 761 struct hns3_config_mac_speed_dup_cmd { 762 uint8_t speed_dup; 763 uint8_t mac_change_fec_en; 764 uint8_t rsv[22]; 765 }; 766 767 #define HNS3_TQP_ENABLE_B 0 768 769 #define HNS3_MAC_CFG_AN_EN_B 0 770 #define HNS3_MAC_CFG_AN_INT_EN_B 1 771 #define HNS3_MAC_CFG_AN_INT_MSK_B 2 772 #define HNS3_MAC_CFG_AN_INT_CLR_B 3 773 #define HNS3_MAC_CFG_AN_RST_B 4 774 775 #define HNS3_MAC_CFG_AN_EN BIT(HNS3_MAC_CFG_AN_EN_B) 776 777 struct hns3_config_auto_neg_cmd { 778 uint32_t cfg_an_cmd_flag; 779 uint8_t rsv[20]; 780 }; 781 782 #define HNS3_SFP_INFO_BD0_LEN 20UL 783 #define HNS3_SFP_INFO_BDX_LEN 24UL 784 785 struct hns3_sfp_info_bd0_cmd { 786 uint16_t offset; 787 uint16_t read_len; 788 uint8_t data[HNS3_SFP_INFO_BD0_LEN]; 789 }; 790 791 struct hns3_sfp_type { 792 uint8_t type; 793 uint8_t ext_type; 794 }; 795 796 /* Bitmap flags in supported_speed */ 797 #define HNS3_FIBER_LINK_SPEED_1G_BIT BIT(0) 798 #define HNS3_FIBER_LINK_SPEED_10G_BIT BIT(1) 799 #define HNS3_FIBER_LINK_SPEED_25G_BIT BIT(2) 800 #define HNS3_FIBER_LINK_SPEED_50G_BIT BIT(3) 801 #define HNS3_FIBER_LINK_SPEED_100G_BIT BIT(4) 802 #define HNS3_FIBER_LINK_SPEED_40G_BIT BIT(5) 803 #define HNS3_FIBER_LINK_SPEED_100M_BIT BIT(6) 804 #define HNS3_FIBER_LINK_SPEED_10M_BIT BIT(7) 805 #define HNS3_FIBER_LINK_SPEED_200G_BIT BIT(8) 806 807 struct hns3_sfp_info_cmd { 808 uint32_t sfp_speed; 809 uint8_t query_type; /* 0: sfp speed, 1: active */ 810 uint8_t active_fec; /* current FEC mode */ 811 uint8_t autoneg; /* current autoneg state */ 812 /* 0: not support autoneg, 1: support autoneg */ 813 uint8_t autoneg_ability; 814 uint32_t supported_speed; /* speed supported by current media */ 815 uint32_t module_type; 816 uint8_t rsv1[8]; 817 }; 818 819 #define HNS3_MAC_CFG_FEC_AUTO_EN_B 0 820 #define HNS3_MAC_CFG_FEC_MODE_S 1 821 #define HNS3_MAC_CFG_FEC_MODE_M GENMASK(3, 1) 822 #define HNS3_MAC_FEC_OFF 0 823 #define HNS3_MAC_FEC_BASER 1 824 #define HNS3_MAC_FEC_RS 2 825 826 /* Configure FEC mode, opcode:0x031A */ 827 struct hns3_config_fec_cmd { 828 uint8_t fec_mode; 829 uint8_t rsv[23]; 830 }; 831 832 #define HNS3_MAC_MGR_MASK_VLAN_B BIT(0) 833 #define HNS3_MAC_MGR_MASK_MAC_B BIT(1) 834 #define HNS3_MAC_MGR_MASK_ETHERTYPE_B BIT(2) 835 #define HNS3_MAC_ETHERTYPE_LLDP 0x88cc 836 837 struct hns3_mac_mgr_tbl_entry_cmd { 838 uint8_t flags; 839 uint8_t resp_code; 840 uint16_t vlan_tag; 841 uint32_t mac_addr_hi32; 842 uint16_t mac_addr_lo16; 843 uint16_t rsv1; 844 uint16_t ethter_type; 845 uint16_t egress_port; 846 uint16_t egress_queue; 847 uint8_t sw_port_id_aware; 848 uint8_t rsv2; 849 uint8_t i_port_bitmap; 850 uint8_t i_port_direction; 851 uint8_t rsv3[2]; 852 }; 853 854 struct hns3_cfg_com_tqp_queue_cmd { 855 uint16_t tqp_id; 856 uint16_t stream_id; 857 uint8_t enable; 858 uint8_t rsv[19]; 859 }; 860 861 #define HNS3_TQP_MAP_TYPE_PF 0 862 #define HNS3_TQP_MAP_TYPE_VF 1 863 #define HNS3_TQP_MAP_TYPE_B 0 864 #define HNS3_TQP_MAP_EN_B 1 865 866 struct hns3_tqp_map_cmd { 867 uint16_t tqp_id; /* Absolute tqp id for in this pf */ 868 uint8_t tqp_vf; /* VF id */ 869 uint8_t tqp_flag; /* Indicate it's pf or vf tqp */ 870 uint16_t tqp_vid; /* Virtual id in this pf/vf */ 871 uint8_t rsv[18]; 872 }; 873 874 enum hns3_ring_type { 875 HNS3_RING_TYPE_TX, 876 HNS3_RING_TYPE_RX 877 }; 878 879 enum hns3_int_gl_idx { 880 HNS3_RING_GL_RX, 881 HNS3_RING_GL_TX, 882 HNS3_RING_GL_IMMEDIATE = 3 883 }; 884 885 #define HNS3_RING_GL_IDX_S 0 886 #define HNS3_RING_GL_IDX_M GENMASK(1, 0) 887 888 #define HNS3_VECTOR_ELEMENTS_PER_CMD 10 889 890 #define HNS3_INT_TYPE_S 0 891 #define HNS3_INT_TYPE_M GENMASK(1, 0) 892 #define HNS3_TQP_ID_S 2 893 #define HNS3_TQP_ID_M GENMASK(12, 2) 894 #define HNS3_INT_GL_IDX_S 13 895 #define HNS3_INT_GL_IDX_M GENMASK(14, 13) 896 #define HNS3_TQP_INT_ID_L_S 0 897 #define HNS3_TQP_INT_ID_L_M GENMASK(7, 0) 898 #define HNS3_TQP_INT_ID_H_S 8 899 #define HNS3_TQP_INT_ID_H_M GENMASK(15, 8) 900 struct hns3_ctrl_vector_chain_cmd { 901 uint8_t int_vector_id; /* the low order of the interrupt id */ 902 uint8_t int_cause_num; 903 uint16_t tqp_type_and_id[HNS3_VECTOR_ELEMENTS_PER_CMD]; 904 uint8_t vfid; 905 uint8_t int_vector_id_h; /* the high order of the interrupt id */ 906 }; 907 908 struct hns3_config_max_frm_size_cmd { 909 uint16_t max_frm_size; 910 uint8_t min_frm_size; 911 uint8_t rsv[21]; 912 }; 913 914 enum hns3_mac_vlan_tbl_opcode { 915 HNS3_MAC_VLAN_ADD, /* Add new or modify mac_vlan */ 916 HNS3_MAC_VLAN_UPDATE, /* Modify other fields of this table */ 917 HNS3_MAC_VLAN_REMOVE, /* Remove a entry through mac_vlan key */ 918 HNS3_MAC_VLAN_LKUP, /* Lookup a entry through mac_vlan key */ 919 }; 920 921 enum hns3_mac_vlan_add_resp_code { 922 HNS3_ADD_UC_OVERFLOW = 2, /* ADD failed for UC overflow */ 923 HNS3_ADD_MC_OVERFLOW, /* ADD failed for MC overflow */ 924 }; 925 926 #define HNS3_MC_MAC_VLAN_ADD_DESC_NUM 3 927 928 #define HNS3_MAC_VLAN_BIT0_EN_B 0 929 #define HNS3_MAC_VLAN_BIT1_EN_B 1 930 #define HNS3_MAC_EPORT_SW_EN_B 12 931 #define HNS3_MAC_EPORT_TYPE_B 11 932 #define HNS3_MAC_EPORT_VFID_S 3 933 #define HNS3_MAC_EPORT_VFID_M GENMASK(10, 3) 934 #define HNS3_MAC_EPORT_PFID_S 0 935 #define HNS3_MAC_EPORT_PFID_M GENMASK(2, 0) 936 struct hns3_mac_vlan_tbl_entry_cmd { 937 uint8_t flags; 938 uint8_t resp_code; 939 uint16_t vlan_tag; 940 uint32_t mac_addr_hi32; 941 uint16_t mac_addr_lo16; 942 uint16_t rsv1; 943 uint8_t entry_type; 944 uint8_t mc_mac_en; 945 uint16_t egress_port; 946 uint16_t egress_queue; 947 uint8_t rsv2[6]; 948 }; 949 950 #define HNS3_TQP_RESET_B 0 951 struct hns3_reset_tqp_queue_cmd { 952 uint16_t tqp_id; 953 uint8_t reset_req; 954 uint8_t ready_to_reset; 955 uint8_t queue_direction; 956 uint8_t rsv[19]; 957 }; 958 959 #define HNS3_CFG_RESET_MAC_B 3 960 #define HNS3_CFG_RESET_FUNC_B 7 961 #define HNS3_CFG_RESET_RCB_B 1 962 struct hns3_reset_cmd { 963 uint8_t mac_func_reset; 964 uint8_t fun_reset_vfid; 965 uint8_t fun_reset_rcb; 966 uint8_t rsv1; 967 uint16_t fun_reset_rcb_vqid_start; 968 uint16_t fun_reset_rcb_vqid_num; 969 uint8_t fun_reset_rcb_return_status; 970 uint8_t rsv2[15]; 971 }; 972 973 #define HNS3_QUERY_DEV_SPECS_BD_NUM 4 974 struct hns3_dev_specs_0_cmd { 975 uint32_t rsv0; 976 uint32_t mac_entry_num; 977 uint32_t mng_entry_num; 978 uint16_t rss_ind_tbl_size; 979 uint16_t rss_key_size; 980 uint16_t intr_ql_max; 981 uint8_t max_non_tso_bd_num; 982 uint8_t rsv1; 983 uint32_t max_tm_rate; 984 }; 985 986 struct hns3_query_rpu_cmd { 987 uint32_t tc_queue_num; 988 uint32_t rsv1[2]; 989 uint32_t rpu_rx_pkt_drop_cnt; 990 uint32_t rsv2[2]; 991 }; 992 993 #define HNS3_OPC_SSU_DROP_REG_NUM 2 994 995 struct hns3_query_ssu_cmd { 996 uint8_t rxtx; 997 uint8_t rsv[3]; 998 uint32_t full_drop_cnt; 999 uint32_t part_drop_cnt; 1000 uint32_t oq_drop_cnt; 1001 uint32_t rev1[2]; 1002 }; 1003 1004 #define HNS3_PTP_ENABLE_B 0 1005 #define HNS3_PTP_TX_ENABLE_B 1 1006 #define HNS3_PTP_RX_ENABLE_B 2 1007 1008 #define HNS3_PTP_TYPE_S 0 1009 #define HNS3_PTP_TYPE_M (0x3 << HNS3_PTP_TYPE_S) 1010 1011 #define ALL_PTP_V2_TYPE 0xF 1012 #define HNS3_PTP_MESSAGE_TYPE_S 0 1013 #define HNS3_PTP_MESSAGE_TYPE_M (0xF << HNS3_PTP_MESSAGE_TYPE_S) 1014 1015 #define PTP_TYPE_L2_V2_TYPE 0 1016 1017 struct hns3_ptp_mode_cfg_cmd { 1018 uint8_t enable; 1019 uint8_t ptp_type; 1020 uint8_t v2_message_type_1; 1021 uint8_t v2_message_type_0; 1022 uint8_t rsv[20]; 1023 }; 1024 1025 struct hns3_ptp_int_cmd { 1026 uint8_t int_en; 1027 uint8_t rsvd[23]; 1028 }; 1029 1030 #define HNS3_MAX_TQP_NUM_HIP08_PF 64 1031 #define HNS3_DEFAULT_TX_BUF 0x4000 /* 16k bytes */ 1032 #define HNS3_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */ 1033 #define HNS3_DEFAULT_DV 0xA000 /* 40k byte */ 1034 #define HNS3_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */ 1035 #define HNS3_NON_DCB_ADDITIONAL_BUF 0x1400 /* 5120 byte */ 1036 1037 #define HNS3_TYPE_CRQ 0 1038 #define HNS3_TYPE_CSQ 1 1039 1040 #define HNS3_NIC_SW_RST_RDY_B 16 1041 #define HNS3_NIC_SW_RST_RDY BIT(HNS3_NIC_SW_RST_RDY_B) 1042 #define HNS3_NIC_CMQ_DESC_NUM 1024 1043 #define HNS3_NIC_CMQ_DESC_NUM_S 3 1044 1045 #define HNS3_CMD_SEND_SYNC(flag) \ 1046 ((flag) & HNS3_CMD_FLAG_NO_INTR) 1047 1048 void hns3_cmd_reuse_desc(struct hns3_cmd_desc *desc, bool is_read); 1049 void hns3_cmd_setup_basic_desc(struct hns3_cmd_desc *desc, 1050 enum hns3_opcode_type opcode, bool is_read); 1051 int hns3_cmd_send(struct hns3_hw *hw, struct hns3_cmd_desc *desc, int num); 1052 int hns3_cmd_init_queue(struct hns3_hw *hw); 1053 int hns3_cmd_init(struct hns3_hw *hw); 1054 void hns3_cmd_destroy_queue(struct hns3_hw *hw); 1055 void hns3_cmd_uninit(struct hns3_hw *hw); 1056 1057 #endif /* _HNS3_CMD_H_ */ 1058