1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018-2019 Hisilicon Limited. 3 */ 4 5 #include <ethdev_pci.h> 6 #include <rte_io.h> 7 8 #include "hns3_ethdev.h" 9 #include "hns3_regs.h" 10 #include "hns3_intr.h" 11 #include "hns3_logs.h" 12 13 #define hns3_is_csq(ring) ((ring)->flag & HNS3_TYPE_CSQ) 14 15 #define cmq_ring_to_dev(ring) (&(ring)->dev->pdev->dev) 16 17 static int 18 hns3_ring_space(struct hns3_cmq_ring *ring) 19 { 20 int ntu = ring->next_to_use; 21 int ntc = ring->next_to_clean; 22 int used = (ntu - ntc + ring->desc_num) % ring->desc_num; 23 24 return ring->desc_num - used - 1; 25 } 26 27 static bool 28 is_valid_csq_clean_head(struct hns3_cmq_ring *ring, int head) 29 { 30 int ntu = ring->next_to_use; 31 int ntc = ring->next_to_clean; 32 33 if (ntu > ntc) 34 return head >= ntc && head <= ntu; 35 36 return head >= ntc || head <= ntu; 37 } 38 39 /* 40 * hns3_allocate_dma_mem - Specific memory alloc for command function. 41 * Malloc a memzone, which is a contiguous portion of physical memory identified 42 * by a name. 43 * @ring: pointer to the ring structure 44 * @size: size of memory requested 45 * @alignment: what to align the allocation to 46 */ 47 static int 48 hns3_allocate_dma_mem(struct hns3_hw *hw, struct hns3_cmq_ring *ring, 49 uint64_t size, uint32_t alignment) 50 { 51 const struct rte_memzone *mz = NULL; 52 char z_name[RTE_MEMZONE_NAMESIZE]; 53 54 snprintf(z_name, sizeof(z_name), "hns3_dma_%" PRIu64, rte_rand()); 55 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 56 RTE_MEMZONE_IOVA_CONTIG, alignment, 57 RTE_PGSIZE_2M); 58 if (mz == NULL) 59 return -ENOMEM; 60 61 ring->buf_size = size; 62 ring->desc = mz->addr; 63 ring->desc_dma_addr = mz->iova; 64 ring->zone = (const void *)mz; 65 hns3_dbg(hw, "memzone %s allocated with physical address: %" PRIu64, 66 mz->name, ring->desc_dma_addr); 67 68 return 0; 69 } 70 71 static void 72 hns3_free_dma_mem(struct hns3_hw *hw, struct hns3_cmq_ring *ring) 73 { 74 hns3_dbg(hw, "memzone %s to be freed with physical address: %" PRIu64, 75 ((const struct rte_memzone *)ring->zone)->name, 76 ring->desc_dma_addr); 77 rte_memzone_free((const struct rte_memzone *)ring->zone); 78 ring->buf_size = 0; 79 ring->desc = NULL; 80 ring->desc_dma_addr = 0; 81 ring->zone = NULL; 82 } 83 84 static int 85 hns3_alloc_cmd_desc(struct hns3_hw *hw, struct hns3_cmq_ring *ring) 86 { 87 int size = ring->desc_num * sizeof(struct hns3_cmd_desc); 88 89 if (hns3_allocate_dma_mem(hw, ring, size, HNS3_CMD_DESC_ALIGNMENT)) { 90 hns3_err(hw, "allocate dma mem failed"); 91 return -ENOMEM; 92 } 93 94 return 0; 95 } 96 97 static void 98 hns3_free_cmd_desc(struct hns3_hw *hw, struct hns3_cmq_ring *ring) 99 { 100 if (ring->desc) 101 hns3_free_dma_mem(hw, ring); 102 } 103 104 static int 105 hns3_alloc_cmd_queue(struct hns3_hw *hw, int ring_type) 106 { 107 struct hns3_cmq_ring *ring = 108 (ring_type == HNS3_TYPE_CSQ) ? &hw->cmq.csq : &hw->cmq.crq; 109 int ret; 110 111 ring->ring_type = ring_type; 112 ring->hw = hw; 113 114 ret = hns3_alloc_cmd_desc(hw, ring); 115 if (ret) 116 hns3_err(hw, "descriptor %s alloc error %d", 117 (ring_type == HNS3_TYPE_CSQ) ? "CSQ" : "CRQ", ret); 118 119 return ret; 120 } 121 122 void 123 hns3_cmd_reuse_desc(struct hns3_cmd_desc *desc, bool is_read) 124 { 125 desc->flag = rte_cpu_to_le_16(HNS3_CMD_FLAG_NO_INTR | HNS3_CMD_FLAG_IN); 126 if (is_read) 127 desc->flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_WR); 128 else 129 desc->flag &= rte_cpu_to_le_16(~HNS3_CMD_FLAG_WR); 130 } 131 132 void 133 hns3_cmd_setup_basic_desc(struct hns3_cmd_desc *desc, 134 enum hns3_opcode_type opcode, bool is_read) 135 { 136 memset((void *)desc, 0, sizeof(struct hns3_cmd_desc)); 137 desc->opcode = rte_cpu_to_le_16(opcode); 138 desc->flag = rte_cpu_to_le_16(HNS3_CMD_FLAG_NO_INTR | HNS3_CMD_FLAG_IN); 139 140 if (is_read) 141 desc->flag |= rte_cpu_to_le_16(HNS3_CMD_FLAG_WR); 142 } 143 144 static void 145 hns3_cmd_clear_regs(struct hns3_hw *hw) 146 { 147 hns3_write_dev(hw, HNS3_CMDQ_TX_ADDR_L_REG, 0); 148 hns3_write_dev(hw, HNS3_CMDQ_TX_ADDR_H_REG, 0); 149 hns3_write_dev(hw, HNS3_CMDQ_TX_DEPTH_REG, 0); 150 hns3_write_dev(hw, HNS3_CMDQ_TX_HEAD_REG, 0); 151 hns3_write_dev(hw, HNS3_CMDQ_TX_TAIL_REG, 0); 152 hns3_write_dev(hw, HNS3_CMDQ_RX_ADDR_L_REG, 0); 153 hns3_write_dev(hw, HNS3_CMDQ_RX_ADDR_H_REG, 0); 154 hns3_write_dev(hw, HNS3_CMDQ_RX_DEPTH_REG, 0); 155 hns3_write_dev(hw, HNS3_CMDQ_RX_HEAD_REG, 0); 156 hns3_write_dev(hw, HNS3_CMDQ_RX_TAIL_REG, 0); 157 } 158 159 static void 160 hns3_cmd_config_regs(struct hns3_cmq_ring *ring) 161 { 162 uint64_t dma = ring->desc_dma_addr; 163 164 if (ring->ring_type == HNS3_TYPE_CSQ) { 165 hns3_write_dev(ring->hw, HNS3_CMDQ_TX_ADDR_L_REG, 166 lower_32_bits(dma)); 167 hns3_write_dev(ring->hw, HNS3_CMDQ_TX_ADDR_H_REG, 168 upper_32_bits(dma)); 169 hns3_write_dev(ring->hw, HNS3_CMDQ_TX_DEPTH_REG, 170 ring->desc_num >> HNS3_NIC_CMQ_DESC_NUM_S | 171 HNS3_NIC_SW_RST_RDY); 172 hns3_write_dev(ring->hw, HNS3_CMDQ_TX_HEAD_REG, 0); 173 hns3_write_dev(ring->hw, HNS3_CMDQ_TX_TAIL_REG, 0); 174 } else { 175 hns3_write_dev(ring->hw, HNS3_CMDQ_RX_ADDR_L_REG, 176 lower_32_bits(dma)); 177 hns3_write_dev(ring->hw, HNS3_CMDQ_RX_ADDR_H_REG, 178 upper_32_bits(dma)); 179 hns3_write_dev(ring->hw, HNS3_CMDQ_RX_DEPTH_REG, 180 ring->desc_num >> HNS3_NIC_CMQ_DESC_NUM_S); 181 hns3_write_dev(ring->hw, HNS3_CMDQ_RX_HEAD_REG, 0); 182 hns3_write_dev(ring->hw, HNS3_CMDQ_RX_TAIL_REG, 0); 183 } 184 } 185 186 static void 187 hns3_cmd_init_regs(struct hns3_hw *hw) 188 { 189 hns3_cmd_config_regs(&hw->cmq.csq); 190 hns3_cmd_config_regs(&hw->cmq.crq); 191 } 192 193 static int 194 hns3_cmd_csq_clean(struct hns3_hw *hw) 195 { 196 struct hns3_cmq_ring *csq = &hw->cmq.csq; 197 uint32_t head; 198 int clean; 199 200 head = hns3_read_dev(hw, HNS3_CMDQ_TX_HEAD_REG); 201 if (!is_valid_csq_clean_head(csq, head)) { 202 hns3_err(hw, "wrong cmd head (%u, %u-%u)", head, 203 csq->next_to_use, csq->next_to_clean); 204 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 205 __atomic_store_n(&hw->reset.disable_cmd, 1, 206 __ATOMIC_RELAXED); 207 hns3_schedule_delayed_reset(HNS3_DEV_HW_TO_ADAPTER(hw)); 208 } 209 210 return -EIO; 211 } 212 213 clean = (head - csq->next_to_clean + csq->desc_num) % csq->desc_num; 214 csq->next_to_clean = head; 215 return clean; 216 } 217 218 static int 219 hns3_cmd_csq_done(struct hns3_hw *hw) 220 { 221 uint32_t head = hns3_read_dev(hw, HNS3_CMDQ_TX_HEAD_REG); 222 223 return head == hw->cmq.csq.next_to_use; 224 } 225 226 static bool 227 hns3_is_special_opcode(uint16_t opcode) 228 { 229 /* 230 * These commands have several descriptors, 231 * and use the first one to save opcode and return value. 232 */ 233 uint16_t spec_opcode[] = {HNS3_OPC_STATS_64_BIT, 234 HNS3_OPC_STATS_32_BIT, 235 HNS3_OPC_STATS_MAC, 236 HNS3_OPC_STATS_MAC_ALL, 237 HNS3_OPC_QUERY_32_BIT_REG, 238 HNS3_OPC_QUERY_64_BIT_REG}; 239 uint32_t i; 240 241 for (i = 0; i < ARRAY_SIZE(spec_opcode); i++) 242 if (spec_opcode[i] == opcode) 243 return true; 244 245 return false; 246 } 247 248 static int 249 hns3_cmd_convert_err_code(uint16_t desc_ret) 250 { 251 static const struct { 252 uint16_t imp_errcode; 253 int linux_errcode; 254 } hns3_cmdq_status[] = { 255 {HNS3_CMD_EXEC_SUCCESS, 0}, 256 {HNS3_CMD_NO_AUTH, -EPERM}, 257 {HNS3_CMD_NOT_SUPPORTED, -EOPNOTSUPP}, 258 {HNS3_CMD_QUEUE_FULL, -EXFULL}, 259 {HNS3_CMD_NEXT_ERR, -ENOSR}, 260 {HNS3_CMD_UNEXE_ERR, -ENOTBLK}, 261 {HNS3_CMD_PARA_ERR, -EINVAL}, 262 {HNS3_CMD_RESULT_ERR, -ERANGE}, 263 {HNS3_CMD_TIMEOUT, -ETIME}, 264 {HNS3_CMD_HILINK_ERR, -ENOLINK}, 265 {HNS3_CMD_QUEUE_ILLEGAL, -ENXIO}, 266 {HNS3_CMD_INVALID, -EBADR}, 267 {HNS3_CMD_ROH_CHECK_FAIL, -EINVAL} 268 }; 269 270 uint32_t i; 271 272 for (i = 0; i < ARRAY_SIZE(hns3_cmdq_status); i++) 273 if (hns3_cmdq_status[i].imp_errcode == desc_ret) 274 return hns3_cmdq_status[i].linux_errcode; 275 276 return -EREMOTEIO; 277 } 278 279 static int 280 hns3_cmd_get_hardware_reply(struct hns3_hw *hw, 281 struct hns3_cmd_desc *desc, int num, int ntc) 282 { 283 uint16_t opcode, desc_ret; 284 int current_ntc = ntc; 285 int handle; 286 287 opcode = rte_le_to_cpu_16(desc[0].opcode); 288 for (handle = 0; handle < num; handle++) { 289 /* Get the result of hardware write back */ 290 desc[handle] = hw->cmq.csq.desc[current_ntc]; 291 292 current_ntc++; 293 if (current_ntc == hw->cmq.csq.desc_num) 294 current_ntc = 0; 295 } 296 297 if (likely(!hns3_is_special_opcode(opcode))) 298 desc_ret = rte_le_to_cpu_16(desc[num - 1].retval); 299 else 300 desc_ret = rte_le_to_cpu_16(desc[0].retval); 301 302 hw->cmq.last_status = desc_ret; 303 return hns3_cmd_convert_err_code(desc_ret); 304 } 305 306 static int hns3_cmd_poll_reply(struct hns3_hw *hw) 307 { 308 struct hns3_adapter *hns = HNS3_DEV_HW_TO_ADAPTER(hw); 309 uint32_t timeout = 0; 310 311 do { 312 if (hns3_cmd_csq_done(hw)) 313 return 0; 314 315 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED)) { 316 hns3_err(hw, 317 "Don't wait for reply because of disable_cmd"); 318 return -EBUSY; 319 } 320 321 if (is_reset_pending(hns)) { 322 hns3_err(hw, "Don't wait for reply because of reset pending"); 323 return -EIO; 324 } 325 326 rte_delay_us(1); 327 timeout++; 328 } while (timeout < hw->cmq.tx_timeout); 329 hns3_err(hw, "Wait for reply timeout"); 330 return -ETIME; 331 } 332 333 /* 334 * hns3_cmd_send - send command to command queue 335 * 336 * @param hw 337 * pointer to the hw struct 338 * @param desc 339 * prefilled descriptor for describing the command 340 * @param num 341 * the number of descriptors to be sent 342 * @return 343 * - -EBUSY if detect device is in resetting 344 * - -EIO if detect cmd csq corrupted (due to reset) or 345 * there is reset pending 346 * - -ENOMEM/-ETIME/...(Non-Zero) if other error case 347 * - Zero if operation completed successfully 348 * 349 * Note -BUSY/-EIO only used in reset case 350 * 351 * Note this is the main send command for command queue, it 352 * sends the queue, cleans the queue, etc 353 */ 354 int 355 hns3_cmd_send(struct hns3_hw *hw, struct hns3_cmd_desc *desc, int num) 356 { 357 struct hns3_cmd_desc *desc_to_use; 358 int handle = 0; 359 int retval; 360 uint32_t ntc; 361 362 if (__atomic_load_n(&hw->reset.disable_cmd, __ATOMIC_RELAXED)) 363 return -EBUSY; 364 365 rte_spinlock_lock(&hw->cmq.csq.lock); 366 367 /* Clean the command send queue */ 368 retval = hns3_cmd_csq_clean(hw); 369 if (retval < 0) { 370 rte_spinlock_unlock(&hw->cmq.csq.lock); 371 return retval; 372 } 373 374 if (num > hns3_ring_space(&hw->cmq.csq)) { 375 rte_spinlock_unlock(&hw->cmq.csq.lock); 376 return -ENOMEM; 377 } 378 379 /* 380 * Record the location of desc in the ring for this time 381 * which will be use for hardware to write back 382 */ 383 ntc = hw->cmq.csq.next_to_use; 384 385 while (handle < num) { 386 desc_to_use = &hw->cmq.csq.desc[hw->cmq.csq.next_to_use]; 387 *desc_to_use = desc[handle]; 388 (hw->cmq.csq.next_to_use)++; 389 if (hw->cmq.csq.next_to_use == hw->cmq.csq.desc_num) 390 hw->cmq.csq.next_to_use = 0; 391 handle++; 392 } 393 394 /* Write to hardware */ 395 hns3_write_dev(hw, HNS3_CMDQ_TX_TAIL_REG, hw->cmq.csq.next_to_use); 396 397 /* 398 * If the command is sync, wait for the firmware to write back, 399 * if multi descriptors to be sent, use the first one to check. 400 */ 401 if (HNS3_CMD_SEND_SYNC(rte_le_to_cpu_16(desc->flag))) { 402 retval = hns3_cmd_poll_reply(hw); 403 if (!retval) 404 retval = hns3_cmd_get_hardware_reply(hw, desc, num, 405 ntc); 406 } 407 408 rte_spinlock_unlock(&hw->cmq.csq.lock); 409 return retval; 410 } 411 412 static void 413 hns3_parse_capability(struct hns3_hw *hw, 414 struct hns3_query_version_cmd *cmd) 415 { 416 uint32_t caps = rte_le_to_cpu_32(cmd->caps[0]); 417 418 if (hns3_get_bit(caps, HNS3_CAPS_UDP_GSO_B)) 419 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_UDP_GSO_B, 1); 420 if (hns3_get_bit(caps, HNS3_CAPS_FD_QUEUE_REGION_B)) 421 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_FD_QUEUE_REGION_B, 422 1); 423 if (hns3_get_bit(caps, HNS3_CAPS_PTP_B)) 424 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_PTP_B, 1); 425 if (hns3_get_bit(caps, HNS3_CAPS_TX_PUSH_B)) 426 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_TX_PUSH_B, 1); 427 if (hns3_get_bit(caps, HNS3_CAPS_PHY_IMP_B)) 428 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_COPPER_B, 1); 429 if (hns3_get_bit(caps, HNS3_CAPS_TQP_TXRX_INDEP_B)) 430 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_INDEP_TXRX_B, 1); 431 if (hns3_get_bit(caps, HNS3_CAPS_STASH_B)) 432 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_STASH_B, 1); 433 if (hns3_get_bit(caps, HNS3_CAPS_RXD_ADV_LAYOUT_B)) 434 hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, 435 1); 436 } 437 438 static uint32_t 439 hns3_build_api_caps(void) 440 { 441 uint32_t api_caps = 0; 442 443 hns3_set_bit(api_caps, HNS3_API_CAP_FLEX_RSS_TBL_B, 1); 444 445 return rte_cpu_to_le_32(api_caps); 446 } 447 448 static enum hns3_cmd_status 449 hns3_cmd_query_firmware_version_and_capability(struct hns3_hw *hw) 450 { 451 struct hns3_query_version_cmd *resp; 452 struct hns3_cmd_desc desc; 453 int ret; 454 455 hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_QUERY_FW_VER, 1); 456 resp = (struct hns3_query_version_cmd *)desc.data; 457 resp->api_caps = hns3_build_api_caps(); 458 459 /* Initialize the cmd function */ 460 ret = hns3_cmd_send(hw, &desc, 1); 461 if (ret) 462 return ret; 463 464 hw->fw_version = rte_le_to_cpu_32(resp->firmware); 465 hns3_parse_capability(hw, resp); 466 467 return 0; 468 } 469 470 int 471 hns3_cmd_init_queue(struct hns3_hw *hw) 472 { 473 int ret; 474 475 /* Setup the lock for command queue */ 476 rte_spinlock_init(&hw->cmq.csq.lock); 477 rte_spinlock_init(&hw->cmq.crq.lock); 478 479 /* 480 * Clear up all command register, 481 * in case there are some residual values 482 */ 483 hns3_cmd_clear_regs(hw); 484 485 /* Setup the queue entries for use cmd queue */ 486 hw->cmq.csq.desc_num = HNS3_NIC_CMQ_DESC_NUM; 487 hw->cmq.crq.desc_num = HNS3_NIC_CMQ_DESC_NUM; 488 489 /* Setup Tx write back timeout */ 490 hw->cmq.tx_timeout = HNS3_CMDQ_TX_TIMEOUT; 491 492 /* Setup queue rings */ 493 ret = hns3_alloc_cmd_queue(hw, HNS3_TYPE_CSQ); 494 if (ret) { 495 PMD_INIT_LOG(ERR, "CSQ ring setup error %d", ret); 496 return ret; 497 } 498 499 ret = hns3_alloc_cmd_queue(hw, HNS3_TYPE_CRQ); 500 if (ret) { 501 PMD_INIT_LOG(ERR, "CRQ ring setup error %d", ret); 502 goto err_crq; 503 } 504 505 return 0; 506 507 err_crq: 508 hns3_free_cmd_desc(hw, &hw->cmq.csq); 509 510 return ret; 511 } 512 513 int 514 hns3_cmd_init(struct hns3_hw *hw) 515 { 516 uint32_t version; 517 int ret; 518 519 rte_spinlock_lock(&hw->cmq.csq.lock); 520 rte_spinlock_lock(&hw->cmq.crq.lock); 521 522 hw->cmq.csq.next_to_clean = 0; 523 hw->cmq.csq.next_to_use = 0; 524 hw->cmq.crq.next_to_clean = 0; 525 hw->cmq.crq.next_to_use = 0; 526 hw->mbx_resp.head = 0; 527 hw->mbx_resp.tail = 0; 528 hw->mbx_resp.lost = 0; 529 hns3_cmd_init_regs(hw); 530 531 rte_spinlock_unlock(&hw->cmq.crq.lock); 532 rte_spinlock_unlock(&hw->cmq.csq.lock); 533 534 /* 535 * Check if there is new reset pending, because the higher level 536 * reset may happen when lower level reset is being processed. 537 */ 538 if (is_reset_pending(HNS3_DEV_HW_TO_ADAPTER(hw))) { 539 PMD_INIT_LOG(ERR, "New reset pending, keep disable cmd"); 540 ret = -EBUSY; 541 goto err_cmd_init; 542 } 543 __atomic_store_n(&hw->reset.disable_cmd, 0, __ATOMIC_RELAXED); 544 545 ret = hns3_cmd_query_firmware_version_and_capability(hw); 546 if (ret) { 547 PMD_INIT_LOG(ERR, "firmware version query failed %d", ret); 548 goto err_cmd_init; 549 } 550 551 version = hw->fw_version; 552 PMD_INIT_LOG(INFO, "The firmware version is %lu.%lu.%lu.%lu", 553 hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M, 554 HNS3_FW_VERSION_BYTE3_S), 555 hns3_get_field(version, HNS3_FW_VERSION_BYTE2_M, 556 HNS3_FW_VERSION_BYTE2_S), 557 hns3_get_field(version, HNS3_FW_VERSION_BYTE1_M, 558 HNS3_FW_VERSION_BYTE1_S), 559 hns3_get_field(version, HNS3_FW_VERSION_BYTE0_M, 560 HNS3_FW_VERSION_BYTE0_S)); 561 562 return 0; 563 564 err_cmd_init: 565 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED); 566 return ret; 567 } 568 569 static void 570 hns3_destroy_queue(struct hns3_hw *hw, struct hns3_cmq_ring *ring) 571 { 572 rte_spinlock_lock(&ring->lock); 573 574 hns3_free_cmd_desc(hw, ring); 575 576 rte_spinlock_unlock(&ring->lock); 577 } 578 579 void 580 hns3_cmd_destroy_queue(struct hns3_hw *hw) 581 { 582 hns3_destroy_queue(hw, &hw->cmq.csq); 583 hns3_destroy_queue(hw, &hw->cmq.crq); 584 } 585 586 void 587 hns3_cmd_uninit(struct hns3_hw *hw) 588 { 589 __atomic_store_n(&hw->reset.disable_cmd, 1, __ATOMIC_RELAXED); 590 591 /* 592 * A delay is added to ensure that the register cleanup operations 593 * will not be performed concurrently with the firmware command and 594 * ensure that all the reserved commands are executed. 595 * Concurrency may occur in two scenarios: asynchronous command and 596 * timeout command. If the command fails to be executed due to busy 597 * scheduling, the command will be processed in the next scheduling 598 * of the firmware. 599 */ 600 rte_delay_ms(HNS3_CMDQ_CLEAR_WAIT_TIME); 601 602 rte_spinlock_lock(&hw->cmq.csq.lock); 603 rte_spinlock_lock(&hw->cmq.crq.lock); 604 hns3_cmd_clear_regs(hw); 605 rte_spinlock_unlock(&hw->cmq.crq.lock); 606 rte_spinlock_unlock(&hw->cmq.csq.lock); 607 } 608