1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2017 Huawei Technologies Co., Ltd 3 */ 4 5 #ifndef _HINIC_PMD_TX_H_ 6 #define _HINIC_PMD_TX_H_ 7 8 #define HINIC_DEFAULT_TX_FREE_THRESH 32 9 #define HINIC_MAX_TX_FREE_BULK 64 10 11 #define HINIC_GET_WQ_HEAD(txq) ((txq)->wq->queue_buf_vaddr) 12 13 #define HINIC_GET_WQ_TAIL(txq) \ 14 ((txq)->wq->queue_buf_vaddr + (txq)->wq->wq_buf_size) 15 16 #define HINIC_TX_CKSUM_OFFLOAD_MASK ( \ 17 PKT_TX_IP_CKSUM | \ 18 PKT_TX_TCP_CKSUM | \ 19 PKT_TX_UDP_CKSUM | \ 20 PKT_TX_SCTP_CKSUM | \ 21 PKT_TX_OUTER_IP_CKSUM | \ 22 PKT_TX_TCP_SEG) 23 24 enum sq_wqe_type { 25 SQ_NORMAL_WQE = 0, 26 }; 27 28 /* tx offload info */ 29 struct hinic_tx_offload_info { 30 u8 outer_l2_len; 31 u8 outer_l3_type; 32 u16 outer_l3_len; 33 34 u8 inner_l2_len; 35 u8 inner_l3_type; 36 u16 inner_l3_len; 37 38 u8 tunnel_length; 39 u8 tunnel_type; 40 u8 inner_l4_type; 41 u8 inner_l4_len; 42 43 u16 payload_offset; 44 u8 inner_l4_tcp_udp; 45 u8 rsvd0; 46 }; 47 48 /* tx sge info */ 49 struct hinic_wqe_info { 50 u16 pi; 51 u16 owner; 52 u16 around; 53 u16 seq_wqebbs; 54 u16 sge_cnt; 55 u16 cpy_mbuf_cnt; 56 }; 57 58 struct hinic_sq_ctrl { 59 u32 ctrl_fmt; 60 u32 queue_info; 61 }; 62 63 struct hinic_sq_task { 64 u32 pkt_info0; 65 u32 pkt_info1; 66 u32 pkt_info2; 67 u32 ufo_v6_identify; 68 u32 pkt_info4; 69 u32 rsvd5; 70 }; 71 72 struct hinic_sq_bufdesc { 73 struct hinic_sge sge; 74 u32 rsvd; 75 }; 76 77 struct hinic_sq_wqe { 78 /* sq wqe control section */ 79 struct hinic_sq_ctrl ctrl; 80 81 /* sq task control section */ 82 struct hinic_sq_task task; 83 84 /* sq sge section start address, 1~127 sges */ 85 struct hinic_sq_bufdesc buf_descs[0]; 86 }; 87 88 struct hinic_txq_stats { 89 u64 packets; 90 u64 bytes; 91 u64 rl_drop; 92 u64 tx_busy; 93 u64 off_errs; 94 u64 cpy_pkts; 95 u64 burst_pkts; 96 u64 sge_len0; 97 u64 mbuf_null; 98 }; 99 100 struct hinic_tx_info { 101 struct rte_mbuf *mbuf; 102 int wqebb_cnt; 103 struct rte_mbuf *cpy_mbuf; 104 }; 105 106 struct hinic_txq { 107 /* cacheline0 */ 108 struct hinic_nic_dev *nic_dev; 109 struct hinic_wq *wq; 110 struct hinic_sq *sq; 111 volatile u16 *cons_idx_addr; 112 struct hinic_tx_info *tx_info; 113 114 u16 tx_free_thresh; 115 u16 port_id; 116 u16 q_id; 117 u16 q_depth; 118 u32 cos; 119 u32 socket_id; 120 121 /* cacheline1 */ 122 struct hinic_txq_stats txq_stats; 123 u64 sq_head_addr; 124 u64 sq_bot_sge_addr; 125 }; 126 127 int hinic_setup_tx_resources(struct hinic_txq *txq); 128 129 void hinic_free_all_tx_resources(struct rte_eth_dev *eth_dev); 130 131 void hinic_free_all_tx_mbuf(struct rte_eth_dev *eth_dev); 132 133 void hinic_free_tx_resources(struct hinic_txq *txq); 134 135 u16 hinic_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, u16 nb_pkts); 136 137 void hinic_free_all_tx_mbufs(struct hinic_txq *txq); 138 139 void hinic_txq_get_stats(struct hinic_txq *txq, struct hinic_txq_stats *stats); 140 141 void hinic_txq_stats_reset(struct hinic_txq *txq); 142 143 int hinic_create_sq(struct hinic_hwdev *hwdev, u16 q_id, 144 u16 sq_depth, unsigned int socket_id); 145 146 void hinic_destroy_sq(struct hinic_hwdev *hwdev, u16 q_id); 147 148 #endif /* _HINIC_PMD_TX_H_ */ 149