xref: /dpdk/drivers/net/hinic/hinic_pmd_rx.h (revision 68a03efeed657e6e05f281479b33b51102797e15)
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2017 Huawei Technologies Co., Ltd
3  */
4 
5 #ifndef _HINIC_PMD_RX_H_
6 #define _HINIC_PMD_RX_H_
7 
8 #define HINIC_DEFAULT_RX_FREE_THRESH	32
9 
10 #define HINIC_RSS_OFFLOAD_ALL ( \
11 	ETH_RSS_IPV4 | \
12 	ETH_RSS_FRAG_IPV4 |\
13 	ETH_RSS_NONFRAG_IPV4_TCP | \
14 	ETH_RSS_NONFRAG_IPV4_UDP | \
15 	ETH_RSS_IPV6 | \
16 	ETH_RSS_FRAG_IPV6 | \
17 	ETH_RSS_NONFRAG_IPV6_TCP | \
18 	ETH_RSS_NONFRAG_IPV6_UDP | \
19 	ETH_RSS_IPV6_EX | \
20 	ETH_RSS_IPV6_TCP_EX | \
21 	ETH_RSS_IPV6_UDP_EX)
22 
23 enum rq_completion_fmt {
24 	RQ_COMPLETE_SGE = 1
25 };
26 
27 struct hinic_rq_ctrl {
28 	u32	ctrl_fmt;
29 };
30 
31 struct hinic_rq_cqe {
32 	u32 status;
33 	u32 vlan_len;
34 	u32 offload_type;
35 	u32 rss_hash;
36 
37 	u32 rsvd[4];
38 #if defined(RTE_ARCH_ARM64)
39 } __rte_cache_aligned;
40 #else
41 };
42 #endif
43 
44 struct hinic_rq_cqe_sect {
45 	struct hinic_sge	sge;
46 	u32			rsvd;
47 };
48 
49 struct hinic_rq_bufdesc {
50 	u32	addr_high;
51 	u32	addr_low;
52 };
53 
54 struct hinic_rq_wqe {
55 	struct hinic_rq_ctrl		ctrl;
56 	u32				rsvd;
57 	struct hinic_rq_cqe_sect	cqe_sect;
58 	struct hinic_rq_bufdesc		buf_desc;
59 };
60 
61 struct hinic_rxq_stats {
62 	u64 packets;
63 	u64 bytes;
64 	u64 rx_nombuf;
65 	u64 errors;
66 	u64 rx_discards;
67 	u64 burst_pkts;
68 };
69 
70 /* Attention, Do not add any member in hinic_rx_info
71  * as rxq bulk rearm mode will write mbuf in rx_info
72  */
73 struct hinic_rx_info {
74 	struct rte_mbuf *mbuf;
75 };
76 
77 struct hinic_rxq {
78 	struct hinic_wq *wq;
79 	volatile u16 *pi_virt_addr;
80 
81 	u16 port_id;
82 	u16 q_id;
83 	u16 q_depth;
84 	u16 buf_len;
85 
86 	u16 rx_free_thresh;
87 	u16 rxinfo_align_end;
88 
89 	u32 socket_id;
90 
91 	unsigned long status;
92 	struct hinic_rxq_stats rxq_stats;
93 
94 	struct hinic_nic_dev *nic_dev;
95 
96 	struct hinic_rx_info	*rx_info;
97 	volatile struct hinic_rq_cqe *rx_cqe;
98 
99 	dma_addr_t cqe_start_paddr;
100 	void *cqe_start_vaddr;
101 	struct rte_mempool *mb_pool;
102 };
103 
104 int hinic_setup_rx_resources(struct hinic_rxq *rxq);
105 
106 void hinic_free_all_rx_resources(struct rte_eth_dev *eth_dev);
107 
108 void hinic_free_all_rx_mbuf(struct rte_eth_dev *eth_dev);
109 
110 void hinic_free_rx_resources(struct hinic_rxq *rxq);
111 
112 u16 hinic_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, u16 nb_pkts);
113 
114 void hinic_free_all_rx_mbufs(struct hinic_rxq *rxq);
115 
116 void hinic_rx_alloc_pkts(struct hinic_rxq *rxq);
117 
118 void hinic_rxq_get_stats(struct hinic_rxq *rxq, struct hinic_rxq_stats *stats);
119 
120 void hinic_rxq_stats_reset(struct hinic_rxq *rxq);
121 
122 int hinic_config_mq_mode(struct rte_eth_dev *dev, bool on);
123 
124 int hinic_rx_configure(struct rte_eth_dev *dev);
125 
126 void hinic_rx_remove_configure(struct rte_eth_dev *dev);
127 
128 void hinic_get_func_rx_buf_size(struct hinic_nic_dev *nic_dev);
129 
130 int hinic_create_rq(struct hinic_hwdev *hwdev, u16 q_id,
131 			u16 rq_depth, unsigned int socket_id);
132 
133 void hinic_destroy_rq(struct hinic_hwdev *hwdev, u16 q_id);
134 
135 #endif /* _HINIC_PMD_RX_H_ */
136