xref: /dpdk/drivers/net/hinic/hinic_pmd_ethdev.h (revision 68a03efeed657e6e05f281479b33b51102797e15)
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2017 Huawei Technologies Co., Ltd
3  */
4 
5 #ifndef _HINIC_PMD_ETHDEV_H_
6 #define _HINIC_PMD_ETHDEV_H_
7 
8 #include <rte_ethdev.h>
9 #include <rte_ethdev_core.h>
10 #include <ethdev_driver.h>
11 
12 #include "base/hinic_compat.h"
13 #include "base/hinic_pmd_cfg.h"
14 
15 #define HINIC_DEV_NAME_LEN	32
16 #define HINIC_MAX_RX_QUEUES	64
17 
18 /* mbuf pool for copy invalid mbuf segs */
19 #define HINIC_COPY_MEMPOOL_DEPTH	128
20 #define HINIC_COPY_MBUF_SIZE		4096
21 
22 #define SIZE_8BYTES(size)	(ALIGN((u32)(size), 8) >> 3)
23 
24 #define HINIC_ETH_DEV_TO_PRIVATE_NIC_DEV(dev) \
25 	((struct hinic_nic_dev *)(dev)->data->dev_private)
26 
27 #define HINIC_MAX_QUEUE_DEPTH		4096
28 #define HINIC_MIN_QUEUE_DEPTH		128
29 #define HINIC_TXD_ALIGN                 1
30 #define HINIC_RXD_ALIGN                 1
31 
32 #define HINIC_UINT32_BIT_SIZE      (CHAR_BIT * sizeof(uint32_t))
33 #define HINIC_VFTA_SIZE            (4096 / HINIC_UINT32_BIT_SIZE)
34 
35 enum hinic_dev_status {
36 	HINIC_DEV_INIT,
37 	HINIC_DEV_CLOSE,
38 	HINIC_DEV_START,
39 	HINIC_DEV_INTR_EN,
40 };
41 
42 #define HINIC_MAX_Q_FILTERS	64 /* hinic just support 64 filter types */
43 #define HINIC_PKT_TYPE_FIND_ID(pkt_type) ((pkt_type) - HINIC_MAX_Q_FILTERS)
44 
45 /* 5tuple filter info */
46 struct hinic_5tuple_filter_info {
47 	uint32_t dst_ip;
48 	uint32_t src_ip;
49 	uint16_t dst_port;
50 	uint16_t src_port;
51 	uint8_t proto; /* l4 protocol. */
52 	/*
53 	 * seven levels (001b-111b), 111b is highest,
54 	 * used when more than one filter matches.
55 	 */
56 	uint8_t priority;
57 
58 	/* if mask is 1b, do not compare the response bit domain */
59 	uint8_t dst_ip_mask:1,
60 		src_ip_mask:1,
61 		dst_port_mask:1,
62 		src_port_mask:1,
63 		proto_mask:1;
64 };
65 
66 /* 5tuple filter structure */
67 struct hinic_5tuple_filter {
68 	TAILQ_ENTRY(hinic_5tuple_filter) entries;
69 	uint16_t index;       /* the index of 5tuple filter */
70 	struct hinic_5tuple_filter_info filter_info;
71 	uint16_t queue;       /* rx queue assigned to */
72 };
73 
74 TAILQ_HEAD(hinic_5tuple_filter_list, hinic_5tuple_filter);
75 
76 /*
77  * If this filter is added by configuration,
78  * it should not be removed.
79  */
80 struct hinic_pkt_filter {
81 	uint16_t pkt_proto;
82 	uint8_t qid;
83 	bool	enable;
84 };
85 
86 /* Structure to store filters' info. */
87 struct hinic_filter_info {
88 	uint8_t pkt_type;
89 	uint8_t qid;
90 	uint64_t type_mask;  /* Bit mask for every used filter */
91 	struct hinic_5tuple_filter_list fivetuple_list;
92 	struct hinic_pkt_filter pkt_filters[HINIC_MAX_Q_FILTERS];
93 };
94 
95 /* Information about the fdir mode. */
96 struct hinic_hw_fdir_mask {
97 	uint32_t src_ipv4_mask;
98 	uint32_t dst_ipv4_mask;
99 	uint16_t src_port_mask;
100 	uint16_t dst_port_mask;
101 	uint16_t proto_mask;
102 	uint16_t tunnel_flag;
103 	uint16_t tunnel_inner_src_port_mask;
104 	uint16_t tunnel_inner_dst_port_mask;
105 	uint16_t dst_ipv6_mask;
106 };
107 
108 /* Flow Director attribute */
109 struct hinic_atr_input {
110 	uint32_t dst_ip;
111 	uint32_t src_ip;
112 	uint16_t src_port;
113 	uint16_t dst_port;
114 	uint16_t proto;
115 	uint16_t tunnel_flag;
116 	uint16_t tunnel_inner_src_port;
117 	uint16_t tunnel_inner_dst_port;
118 	uint8_t  dst_ipv6[16];
119 };
120 
121 enum hinic_fdir_mode {
122 	HINIC_FDIR_MODE_NORMAL      = 0,
123 	HINIC_FDIR_MODE_TCAM        = 1,
124 };
125 
126 #define HINIC_PF_MAX_TCAM_FILTERS	1024
127 #define HINIC_VF_MAX_TCAM_FILTERS	128
128 #define HINIC_SUPPORT_PF_MAX_NUM	4
129 #define HINIC_TOTAL_PF_MAX_NUM		16
130 #define HINIC_SUPPORT_VF_MAX_NUM	32
131 #define HINIC_TCAM_BLOCK_TYPE_PF	0 /* 1024 tcam index of a block */
132 #define HINIC_TCAM_BLOCK_TYPE_VF	1 /* 128 tcam index of a block */
133 
134 #define HINIC_PKT_VF_TCAM_INDEX_START(block_index)  \
135 		(HINIC_PF_MAX_TCAM_FILTERS * HINIC_SUPPORT_PF_MAX_NUM + \
136 		HINIC_VF_MAX_TCAM_FILTERS * (block_index))
137 
138 TAILQ_HEAD(hinic_tcam_filter_list, hinic_tcam_filter);
139 
140 struct hinic_tcam_info {
141 	struct hinic_tcam_filter_list tcam_list;
142 	u8 tcam_index_array[HINIC_PF_MAX_TCAM_FILTERS];
143 	u16 tcam_block_index;
144 	u16 tcam_rule_nums;
145 };
146 
147 struct tag_tcam_key_mem {
148 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN)
149 
150 		u32 rsvd0:16;
151 		u32 function_id:16;
152 
153 		u32 protocol:8;
154 		/*
155 		 * tunnel packet, mask must be 0xff, spec value is 1;
156 		 * normal packet, mask must be 0, spec value is 0;
157 		 * if tunnal packet, ucode use
158 		 * sip/dip/protocol/src_port/dst_dport from inner packet
159 		 */
160 		u32 tunnel_flag:8;
161 		u32 sip_h:16;
162 
163 		u32 sip_l:16;
164 		u32 dip_h:16;
165 
166 		u32 dip_l:16;
167 		u32 src_port:16;
168 
169 		u32 dst_port:16;
170 		/*
171 		 * tunnel packet and normal packet,
172 		 * ext_dip mask must be 0xffffffff
173 		 */
174 		u32 ext_dip_h:16;
175 		u32 ext_dip_l:16;
176 		u32 rsvd2:16;
177 #else
178 		u32 function_id:16;
179 		u32 rsvd0:16;
180 
181 		u32 sip_h:16;
182 		u32 tunnel_flag:8;
183 		u32 protocol:8;
184 
185 		u32 dip_h:16;
186 		u32 sip_l:16;
187 
188 		u32 src_port:16;
189 		u32 dip_l:16;
190 
191 		u32 ext_dip_h:16;
192 		u32 dst_port:16;
193 
194 		u32 rsvd2:16;
195 		u32 ext_dip_l:16;
196 #endif
197 };
198 
199 struct tag_tcam_key_ipv6_mem {
200 #if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN)
201 		u32 rsvd0:16;
202 		u32 ipv6_flag:1;
203 		u32 protocol:7;
204 		u32 function_id:8;
205 
206 		u32 dst_port:16;
207 		u32 ipv6_key0:16;
208 
209 		u32 ipv6_key1:16;
210 		u32 ipv6_key2:16;
211 
212 		u32 ipv6_key3:16;
213 		u32 ipv6_key4:16;
214 
215 		u32 ipv6_key5:16;
216 		u32 ipv6_key6:16;
217 
218 		u32 ipv6_key7:16;
219 		u32 rsvd2:16;
220 #else
221 		u32 function_id:8;
222 		u32 protocol:7;
223 		u32 ipv6_flag:1;
224 		u32 rsvd0:16;
225 
226 		u32 ipv6_key0:16;
227 		u32 dst_port:16;
228 
229 		u32 ipv6_key2:16;
230 		u32 ipv6_key1:16;
231 
232 		u32 ipv6_key4:16;
233 		u32 ipv6_key3:16;
234 
235 		u32 ipv6_key6:16;
236 		u32 ipv6_key5:16;
237 
238 		u32 rsvd2:16;
239 		u32 ipv6_key7:16;
240 #endif
241 };
242 
243 struct tag_tcam_key {
244 	union {
245 		struct tag_tcam_key_mem key_info;
246 		struct tag_tcam_key_ipv6_mem key_info_ipv6;
247 	};
248 
249 	union {
250 		struct tag_tcam_key_mem key_mask;
251 		struct tag_tcam_key_ipv6_mem key_mask_ipv6;
252 	};
253 };
254 
255 struct hinic_fdir_rule {
256 	struct hinic_hw_fdir_mask mask;
257 	struct hinic_atr_input hinic_fdir; /* key of fdir filter */
258 	uint8_t queue; /* queue assigned when matched */
259 	enum hinic_fdir_mode mode; /* fdir type */
260 	u16 tcam_index;
261 };
262 
263 /* ntuple filter list structure */
264 struct hinic_ntuple_filter_ele {
265 	TAILQ_ENTRY(hinic_ntuple_filter_ele) entries;
266 	struct rte_eth_ntuple_filter filter_info;
267 };
268 
269 /* ethertype filter list structure */
270 struct hinic_ethertype_filter_ele {
271 	TAILQ_ENTRY(hinic_ethertype_filter_ele) entries;
272 	struct rte_eth_ethertype_filter filter_info;
273 };
274 
275 /* fdir filter list structure */
276 struct hinic_fdir_rule_ele {
277 	TAILQ_ENTRY(hinic_fdir_rule_ele) entries;
278 	struct hinic_fdir_rule filter_info;
279 };
280 
281 struct hinic_tcam_filter {
282 	TAILQ_ENTRY(hinic_tcam_filter) entries;
283 	uint16_t index; /* tcam index */
284 	struct tag_tcam_key tcam_key;
285 	uint16_t queue; /* rx queue assigned to */
286 };
287 
288 struct rte_flow {
289 	enum rte_filter_type filter_type;
290 	void *rule;
291 };
292 
293 /* hinic_flow memory list structure */
294 struct hinic_flow_mem {
295 	TAILQ_ENTRY(hinic_flow_mem) entries;
296 	struct rte_flow *flow;
297 };
298 
299 TAILQ_HEAD(hinic_ntuple_filter_list, hinic_ntuple_filter_ele);
300 TAILQ_HEAD(hinic_ethertype_filter_list, hinic_ethertype_filter_ele);
301 TAILQ_HEAD(hinic_fdir_rule_filter_list, hinic_fdir_rule_ele);
302 TAILQ_HEAD(hinic_flow_mem_list, hinic_flow_mem);
303 
304 extern const struct rte_flow_ops hinic_flow_ops;
305 
306 /* hinic nic_device */
307 struct hinic_nic_dev {
308 	/* hardware device */
309 	struct hinic_hwdev *hwdev;
310 	struct hinic_txq **txqs;
311 	struct hinic_rxq **rxqs;
312 	struct rte_mempool *cpy_mpool;
313 	u16 num_qps;
314 	u16 num_sq;
315 	u16 num_rq;
316 	u16 mtu_size;
317 	u8 rss_tmpl_idx;
318 	u8 rss_indir_flag;
319 	u8 num_rss;
320 	u8 rx_queue_list[HINIC_MAX_RX_QUEUES];
321 
322 	bool pause_set;
323 	struct nic_pause_config nic_pause;
324 
325 	u32 vfta[HINIC_VFTA_SIZE];	/* VLAN bitmap */
326 
327 	struct rte_ether_addr default_addr;
328 	struct rte_ether_addr *mc_list;
329 	/* info */
330 	unsigned int flags;
331 	struct nic_service_cap nic_cap;
332 	u32 rx_mode_status;	/* promisc or allmulticast */
333 	pthread_mutex_t rx_mode_mutex;
334 	u32 dev_status;
335 
336 	char proc_dev_name[HINIC_DEV_NAME_LEN];
337 	/* PF0->COS4, PF1->COS5, PF2->COS6, PF3->COS7,
338 	 * vf: the same with associate pf
339 	 */
340 	u32 default_cos;
341 	u32 rx_csum_en;
342 
343 	struct hinic_filter_info    filter;
344 	struct hinic_tcam_info      tcam;
345 	struct hinic_ntuple_filter_list filter_ntuple_list;
346 	struct hinic_ethertype_filter_list filter_ethertype_list;
347 	struct hinic_fdir_rule_filter_list filter_fdir_rule_list;
348 	struct hinic_flow_mem_list hinic_flow_list;
349 };
350 
351 void hinic_free_fdir_filter(struct hinic_nic_dev *nic_dev);
352 
353 void hinic_destroy_fdir_filter(struct rte_eth_dev *dev);
354 #endif /* _HINIC_PMD_ETHDEV_H_ */
355