xref: /dpdk/drivers/net/enic/enic_res.h (revision 22572e84fbda2c195707ffbb0dd6af4433d7a219)
12e99ea80SHyong Youb Kim /* SPDX-License-Identifier: BSD-3-Clause
22e99ea80SHyong Youb Kim  * Copyright 2008-2017 Cisco Systems, Inc.  All rights reserved.
372f3de30SBruce Richardson  * Copyright 2007 Nuova Systems, Inc.  All rights reserved.
472f3de30SBruce Richardson  */
572f3de30SBruce Richardson 
672f3de30SBruce Richardson #ifndef _ENIC_RES_H_
772f3de30SBruce Richardson #define _ENIC_RES_H_
872f3de30SBruce Richardson 
972f3de30SBruce Richardson #include "wq_enet_desc.h"
1072f3de30SBruce Richardson #include "rq_enet_desc.h"
1172f3de30SBruce Richardson #include "vnic_wq.h"
1272f3de30SBruce Richardson #include "vnic_rq.h"
1372f3de30SBruce Richardson 
1472f3de30SBruce Richardson #define ENIC_MIN_WQ_DESCS		64
1572f3de30SBruce Richardson #define ENIC_MIN_RQ_DESCS		64
16*22572e84SJohn Daley 
17*22572e84SJohn Daley /* 1400 series VICs and prior all have 4K max, after that it's in the config */
18*22572e84SJohn Daley #define ENIC_LEGACY_MAX_WQ_DESCS        4096
19*22572e84SJohn Daley #define ENIC_LEGACY_MAX_RQ_DESCS        4096
2072f3de30SBruce Richardson 
219466a38dSHyong Youb Kim /* A descriptor ring has a multiple of 32 descriptors */
229466a38dSHyong Youb Kim #define ENIC_ALIGN_DESCS		32
239466a38dSHyong Youb Kim #define ENIC_ALIGN_DESCS_MASK		~(ENIC_ALIGN_DESCS - 1)
249466a38dSHyong Youb Kim 
25c55614d1SHyong Youb Kim /* Request a completion index every 32 buffers (roughly packets) */
26c55614d1SHyong Youb Kim #define ENIC_WQ_CQ_THRESH		32
27c55614d1SHyong Youb Kim 
2872f3de30SBruce Richardson #define ENIC_MIN_MTU			68
29bb34ffb8SJohn Daley 
30bb34ffb8SJohn Daley /* Does not include (possible) inserted VLAN tag and FCS */
31ed6e564cSJohn Daley #define ENIC_DEFAULT_RX_MAX_PKT_SIZE	9022
32ed6e564cSJohn Daley 
33ed6e564cSJohn Daley /* Does not include (possible) inserted VLAN tag and FCS */
34ed6e564cSJohn Daley #define ENIC_TX_MAX_PKT_SIZE		9208
3572f3de30SBruce Richardson 
3672f3de30SBruce Richardson #define ENIC_MULTICAST_PERFECT_FILTERS	32
3772f3de30SBruce Richardson #define ENIC_UNICAST_PERFECT_FILTERS	32
3872f3de30SBruce Richardson 
3972f3de30SBruce Richardson #define ENIC_NON_TSO_MAX_DESC		16
40947d860cSJohn Daley #define ENIC_DEFAULT_RX_FREE_THRESH	32
4178f90329SJohn Daley #define ENIC_TX_XMIT_MAX		64
4235e2cb6aSJohn Daley #define ENIC_RX_BURST_MAX		64
4372f3de30SBruce Richardson 
449466a38dSHyong Youb Kim /* Defaults for dev_info.default_{rx,tx}portconf */
459466a38dSHyong Youb Kim #define ENIC_DEFAULT_RX_BURST		32
469466a38dSHyong Youb Kim #define ENIC_DEFAULT_RX_RINGS		1
479466a38dSHyong Youb Kim #define ENIC_DEFAULT_RX_RING_SIZE	512
489466a38dSHyong Youb Kim #define ENIC_DEFAULT_TX_BURST		32
499466a38dSHyong Youb Kim #define ENIC_DEFAULT_TX_RINGS		1
509466a38dSHyong Youb Kim #define ENIC_DEFAULT_TX_RING_SIZE	512
519466a38dSHyong Youb Kim 
52c2fec27bSHyong Youb Kim #define ENIC_RSS_DEFAULT_CPU    0
53c2fec27bSHyong Youb Kim #define ENIC_RSS_BASE_CPU       0
54c2fec27bSHyong Youb Kim #define ENIC_RSS_HASH_BITS      7
55c2fec27bSHyong Youb Kim #define ENIC_RSS_RETA_SIZE      (1 << ENIC_RSS_HASH_BITS)
56c2fec27bSHyong Youb Kim #define ENIC_RSS_HASH_KEY_SIZE  40
57c2fec27bSHyong Youb Kim 
5872f3de30SBruce Richardson #define ENIC_SETTING(enic, f) ((enic->config.flags & VENETF_##f) ? 1 : 0)
5972f3de30SBruce Richardson 
6072f3de30SBruce Richardson struct enic;
6172f3de30SBruce Richardson 
6272f3de30SBruce Richardson int enic_get_vnic_config(struct enic *);
6304e8ec74SJohn Daley int enic_set_nic_cfg(struct enic *enic, uint8_t rss_default_cpu,
6404e8ec74SJohn Daley 		     uint8_t rss_hash_type, uint8_t rss_hash_bits,
6504e8ec74SJohn Daley 		     uint8_t rss_base_cpu, uint8_t rss_enable,
6604e8ec74SJohn Daley 		     uint8_t tso_ipid_split_en, uint8_t ig_vlan_strip_en);
6704e8ec74SJohn Daley int enic_set_rss_key(struct enic *enic, dma_addr_t key_pa, uint64_t len);
6804e8ec74SJohn Daley int enic_set_rss_cpu(struct enic *enic, dma_addr_t cpu_pa, uint64_t len);
6972f3de30SBruce Richardson void enic_get_res_counts(struct enic *enic);
7072f3de30SBruce Richardson void enic_init_vnic_resources(struct enic *enic);
7172f3de30SBruce Richardson int enic_alloc_vnic_resources(struct enic *);
7272f3de30SBruce Richardson void enic_free_vnic_resources(struct enic *);
7372f3de30SBruce Richardson 
7472f3de30SBruce Richardson #endif /* _ENIC_RES_H_ */
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