1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018 NXP 3 */ 4 5 #include <stdbool.h> 6 #include <rte_ethdev_pci.h> 7 8 #include "enetc_logs.h" 9 #include "enetc.h" 10 11 int enetc_logtype_pmd; 12 13 /* Functions Prototypes */ 14 static int enetc_dev_configure(struct rte_eth_dev *dev); 15 static int enetc_dev_start(struct rte_eth_dev *dev); 16 static void enetc_dev_stop(struct rte_eth_dev *dev); 17 static void enetc_dev_close(struct rte_eth_dev *dev); 18 static void enetc_dev_infos_get(struct rte_eth_dev *dev, 19 struct rte_eth_dev_info *dev_info); 20 static int enetc_link_update(struct rte_eth_dev *dev, int wait_to_complete); 21 static int enetc_hardware_init(struct enetc_eth_hw *hw); 22 static int enetc_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id, 23 uint16_t nb_rx_desc, unsigned int socket_id, 24 const struct rte_eth_rxconf *rx_conf, 25 struct rte_mempool *mb_pool); 26 static void enetc_rx_queue_release(void *rxq); 27 static int enetc_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id, 28 uint16_t nb_tx_desc, unsigned int socket_id, 29 const struct rte_eth_txconf *tx_conf); 30 static void enetc_tx_queue_release(void *txq); 31 static const uint32_t *enetc_supported_ptypes_get(struct rte_eth_dev *dev); 32 33 /* 34 * The set of PCI devices this driver supports 35 */ 36 static const struct rte_pci_id pci_id_enetc_map[] = { 37 { RTE_PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID) }, 38 { RTE_PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID_VF) }, 39 { .vendor_id = 0, /* sentinel */ }, 40 }; 41 42 /* Features supported by this driver */ 43 static const struct eth_dev_ops enetc_ops = { 44 .dev_configure = enetc_dev_configure, 45 .dev_start = enetc_dev_start, 46 .dev_stop = enetc_dev_stop, 47 .dev_close = enetc_dev_close, 48 .link_update = enetc_link_update, 49 .dev_infos_get = enetc_dev_infos_get, 50 .rx_queue_setup = enetc_rx_queue_setup, 51 .rx_queue_release = enetc_rx_queue_release, 52 .tx_queue_setup = enetc_tx_queue_setup, 53 .tx_queue_release = enetc_tx_queue_release, 54 .dev_supported_ptypes_get = enetc_supported_ptypes_get, 55 }; 56 57 /** 58 * Initialisation of the enetc device 59 * 60 * @param eth_dev 61 * - Pointer to the structure rte_eth_dev 62 * 63 * @return 64 * - On success, zero. 65 * - On failure, negative value. 66 */ 67 static int 68 enetc_dev_init(struct rte_eth_dev *eth_dev) 69 { 70 int error = 0; 71 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 72 struct enetc_eth_hw *hw = 73 ENETC_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 74 75 PMD_INIT_FUNC_TRACE(); 76 eth_dev->dev_ops = &enetc_ops; 77 eth_dev->rx_pkt_burst = &enetc_recv_pkts; 78 eth_dev->tx_pkt_burst = &enetc_xmit_pkts; 79 80 /* Retrieving and storing the HW base address of device */ 81 hw->hw.reg = (void *)pci_dev->mem_resource[0].addr; 82 hw->device_id = pci_dev->id.device_id; 83 84 error = enetc_hardware_init(hw); 85 if (error != 0) { 86 ENETC_PMD_ERR("Hardware initialization failed"); 87 return -1; 88 } 89 90 /* Allocate memory for storing MAC addresses */ 91 eth_dev->data->mac_addrs = rte_zmalloc("enetc_eth", ETHER_ADDR_LEN, 0); 92 if (!eth_dev->data->mac_addrs) { 93 ENETC_PMD_ERR("Failed to allocate %d bytes needed to " 94 "store MAC addresses", 95 ETHER_ADDR_LEN * 1); 96 error = -ENOMEM; 97 return -1; 98 } 99 100 /* Copy the permanent MAC address */ 101 ether_addr_copy((struct ether_addr *)hw->mac.addr, 102 ð_dev->data->mac_addrs[0]); 103 104 ENETC_PMD_DEBUG("port_id %d vendorID=0x%x deviceID=0x%x", 105 eth_dev->data->port_id, pci_dev->id.vendor_id, 106 pci_dev->id.device_id); 107 return 0; 108 } 109 110 static int 111 enetc_dev_uninit(struct rte_eth_dev *eth_dev __rte_unused) 112 { 113 PMD_INIT_FUNC_TRACE(); 114 return 0; 115 } 116 117 static int 118 enetc_dev_configure(struct rte_eth_dev *dev __rte_unused) 119 { 120 PMD_INIT_FUNC_TRACE(); 121 return 0; 122 } 123 124 static int 125 enetc_dev_start(struct rte_eth_dev *dev) 126 { 127 struct enetc_eth_hw *hw = 128 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private); 129 uint32_t val; 130 131 PMD_INIT_FUNC_TRACE(); 132 val = ENETC_REG_READ(ENETC_GET_HW_ADDR(hw->hw.port, 133 ENETC_PM0_CMD_CFG)); 134 ENETC_REG_WRITE(ENETC_GET_HW_ADDR(hw->hw.port, ENETC_PM0_CMD_CFG), 135 val | ENETC_PM0_TX_EN | ENETC_PM0_RX_EN); 136 137 /* Enable port */ 138 val = ENETC_REG_READ(ENETC_GET_HW_ADDR(hw->hw.port, ENETC_PMR)); 139 ENETC_REG_WRITE(ENETC_GET_HW_ADDR(hw->hw.port, ENETC_PMR), 140 val | ENETC_PMR_EN); 141 142 return 0; 143 } 144 145 static void 146 enetc_dev_stop(struct rte_eth_dev *dev) 147 { 148 struct enetc_eth_hw *hw = 149 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private); 150 uint32_t val; 151 152 PMD_INIT_FUNC_TRACE(); 153 /* Disable port */ 154 val = ENETC_REG_READ(ENETC_GET_HW_ADDR(hw->hw.port, ENETC_PMR)); 155 ENETC_REG_WRITE(ENETC_GET_HW_ADDR(hw->hw.port, ENETC_PMR), 156 val & (~ENETC_PMR_EN)); 157 158 val = ENETC_REG_READ(ENETC_GET_HW_ADDR(hw->hw.port, 159 ENETC_PM0_CMD_CFG)); 160 ENETC_REG_WRITE(ENETC_GET_HW_ADDR(hw->hw.port, ENETC_PM0_CMD_CFG), 161 val & (~(ENETC_PM0_TX_EN | ENETC_PM0_RX_EN))); 162 } 163 164 static void 165 enetc_dev_close(struct rte_eth_dev *dev) 166 { 167 uint16_t i; 168 169 PMD_INIT_FUNC_TRACE(); 170 enetc_dev_stop(dev); 171 172 for (i = 0; i < dev->data->nb_rx_queues; i++) { 173 enetc_rx_queue_release(dev->data->rx_queues[i]); 174 dev->data->rx_queues[i] = NULL; 175 } 176 dev->data->nb_rx_queues = 0; 177 178 for (i = 0; i < dev->data->nb_tx_queues; i++) { 179 enetc_tx_queue_release(dev->data->tx_queues[i]); 180 dev->data->tx_queues[i] = NULL; 181 } 182 dev->data->nb_tx_queues = 0; 183 } 184 185 static const uint32_t * 186 enetc_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused) 187 { 188 static const uint32_t ptypes[] = { 189 RTE_PTYPE_L2_ETHER, 190 RTE_PTYPE_L3_IPV4, 191 RTE_PTYPE_L3_IPV6, 192 RTE_PTYPE_L4_TCP, 193 RTE_PTYPE_L4_UDP, 194 RTE_PTYPE_L4_SCTP, 195 RTE_PTYPE_L4_ICMP, 196 RTE_PTYPE_UNKNOWN 197 }; 198 199 return ptypes; 200 } 201 202 /* return 0 means link status changed, -1 means not changed */ 203 static int 204 enetc_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused) 205 { 206 struct enetc_eth_hw *hw = 207 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private); 208 struct rte_eth_link link; 209 uint32_t status; 210 211 PMD_INIT_FUNC_TRACE(); 212 213 memset(&link, 0, sizeof(link)); 214 215 status = ENETC_REG_READ(ENETC_GET_HW_ADDR(hw->hw.port, 216 ENETC_PM0_STATUS)); 217 218 if (status & ENETC_LINK_MODE) 219 link.link_duplex = ETH_LINK_FULL_DUPLEX; 220 else 221 link.link_duplex = ETH_LINK_HALF_DUPLEX; 222 223 if (status & ENETC_LINK_STATUS) 224 link.link_status = ETH_LINK_UP; 225 else 226 link.link_status = ETH_LINK_DOWN; 227 228 switch (status & ENETC_LINK_SPEED_MASK) { 229 case ENETC_LINK_SPEED_1G: 230 link.link_speed = ETH_SPEED_NUM_1G; 231 break; 232 233 case ENETC_LINK_SPEED_100M: 234 link.link_speed = ETH_SPEED_NUM_100M; 235 break; 236 237 default: 238 case ENETC_LINK_SPEED_10M: 239 link.link_speed = ETH_SPEED_NUM_10M; 240 } 241 242 return rte_eth_linkstatus_set(dev, &link); 243 } 244 245 static int 246 enetc_hardware_init(struct enetc_eth_hw *hw) 247 { 248 uint32_t psipmr = 0; 249 250 PMD_INIT_FUNC_TRACE(); 251 /* Calculating and storing the base HW addresses */ 252 hw->hw.port = (void *)((size_t)hw->hw.reg + ENETC_PORT_BASE); 253 hw->hw.global = (void *)((size_t)hw->hw.reg + ENETC_GLOBAL_BASE); 254 255 /* Enabling Station Interface */ 256 ENETC_REG_WRITE(ENETC_GET_HW_ADDR(hw->hw.reg, ENETC_SIMR), 257 ENETC_SIMR_EN); 258 259 /* Setting to accept broadcast packets for each inetrface */ 260 psipmr |= ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0) | 261 ENETC_PSIPMR_SET_VLAN_MP(0); 262 psipmr |= ENETC_PSIPMR_SET_UP(1) | ENETC_PSIPMR_SET_MP(1) | 263 ENETC_PSIPMR_SET_VLAN_MP(1); 264 psipmr |= ENETC_PSIPMR_SET_UP(2) | ENETC_PSIPMR_SET_MP(2) | 265 ENETC_PSIPMR_SET_VLAN_MP(2); 266 267 ENETC_REG_WRITE(ENETC_GET_HW_ADDR(hw->hw.port, ENETC_PSIPMR), 268 psipmr); 269 270 /* Enabling broadcast address */ 271 ENETC_REG_WRITE(ENETC_GET_HW_ADDR(hw->hw.port, ENETC_PSIPMAR0(0)), 272 0xFFFFFFFF); 273 ENETC_REG_WRITE(ENETC_GET_HW_ADDR(hw->hw.port, ENETC_PSIPMAR1(0)), 274 0xFFFF << 16); 275 276 return 0; 277 } 278 279 static void 280 enetc_dev_infos_get(struct rte_eth_dev *dev __rte_unused, 281 struct rte_eth_dev_info *dev_info) 282 { 283 PMD_INIT_FUNC_TRACE(); 284 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) { 285 .nb_max = MAX_BD_COUNT, 286 .nb_min = MIN_BD_COUNT, 287 .nb_align = BD_ALIGN, 288 }; 289 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) { 290 .nb_max = MAX_BD_COUNT, 291 .nb_min = MIN_BD_COUNT, 292 .nb_align = BD_ALIGN, 293 }; 294 dev_info->max_rx_queues = MAX_RX_RINGS; 295 dev_info->max_tx_queues = MAX_TX_RINGS; 296 dev_info->max_rx_pktlen = 1500; 297 } 298 299 static int 300 enetc_alloc_txbdr(struct enetc_bdr *txr, uint16_t nb_desc) 301 { 302 int size; 303 304 size = nb_desc * sizeof(struct enetc_swbd); 305 txr->q_swbd = rte_malloc(NULL, size, RTE_CACHE_LINE_SIZE); 306 if (txr->q_swbd == NULL) 307 return -ENOMEM; 308 309 size = nb_desc * sizeof(struct enetc_tx_bd); 310 txr->bd_base = rte_malloc(NULL, size, RTE_CACHE_LINE_SIZE); 311 if (txr->bd_base == NULL) { 312 rte_free(txr->q_swbd); 313 txr->q_swbd = NULL; 314 return -ENOMEM; 315 } 316 317 txr->bd_count = nb_desc; 318 txr->next_to_clean = 0; 319 txr->next_to_use = 0; 320 321 return 0; 322 } 323 324 static void 325 enetc_free_bdr(struct enetc_bdr *rxr) 326 { 327 rte_free(rxr->q_swbd); 328 rte_free(rxr->bd_base); 329 rxr->q_swbd = NULL; 330 rxr->bd_base = NULL; 331 } 332 333 static void 334 enetc_setup_txbdr(struct enetc_hw *hw, struct enetc_bdr *tx_ring) 335 { 336 int idx = tx_ring->index; 337 uintptr_t base_addr; 338 uint32_t tbmr; 339 340 base_addr = (uintptr_t)tx_ring->bd_base; 341 enetc_txbdr_wr(hw, idx, ENETC_TBBAR0, 342 lower_32_bits((uint64_t)base_addr)); 343 enetc_txbdr_wr(hw, idx, ENETC_TBBAR1, 344 upper_32_bits((uint64_t)base_addr)); 345 enetc_txbdr_wr(hw, idx, ENETC_TBLENR, 346 ENETC_RTBLENR_LEN(tx_ring->bd_count)); 347 348 tbmr = ENETC_TBMR_EN; 349 /* enable ring */ 350 enetc_txbdr_wr(hw, idx, ENETC_TBMR, tbmr); 351 enetc_txbdr_wr(hw, idx, ENETC_TBCIR, 0); 352 enetc_txbdr_wr(hw, idx, ENETC_TBCISR, 0); 353 tx_ring->tcir = (void *)((size_t)hw->reg + 354 ENETC_BDR(TX, idx, ENETC_TBCIR)); 355 tx_ring->tcisr = (void *)((size_t)hw->reg + 356 ENETC_BDR(TX, idx, ENETC_TBCISR)); 357 } 358 359 static int 360 enetc_alloc_tx_resources(struct rte_eth_dev *dev, 361 uint16_t queue_idx, 362 uint16_t nb_desc) 363 { 364 int err; 365 struct enetc_bdr *tx_ring; 366 struct rte_eth_dev_data *data = dev->data; 367 struct enetc_eth_adapter *priv = 368 ENETC_DEV_PRIVATE(data->dev_private); 369 370 tx_ring = rte_zmalloc(NULL, sizeof(struct enetc_bdr), 0); 371 if (tx_ring == NULL) { 372 ENETC_PMD_ERR("Failed to allocate TX ring memory"); 373 err = -ENOMEM; 374 return -1; 375 } 376 377 err = enetc_alloc_txbdr(tx_ring, nb_desc); 378 if (err) 379 goto fail; 380 381 tx_ring->index = queue_idx; 382 tx_ring->ndev = dev; 383 enetc_setup_txbdr(&priv->hw.hw, tx_ring); 384 data->tx_queues[queue_idx] = tx_ring; 385 386 return 0; 387 fail: 388 rte_free(tx_ring); 389 390 return err; 391 } 392 393 static int 394 enetc_tx_queue_setup(struct rte_eth_dev *dev, 395 uint16_t queue_idx, 396 uint16_t nb_desc, 397 unsigned int socket_id __rte_unused, 398 const struct rte_eth_txconf *tx_conf __rte_unused) 399 { 400 int err = 0; 401 402 PMD_INIT_FUNC_TRACE(); 403 if (nb_desc > MAX_BD_COUNT) 404 return -1; 405 406 err = enetc_alloc_tx_resources(dev, queue_idx, nb_desc); 407 408 return err; 409 } 410 411 static void 412 enetc_tx_queue_release(void *txq) 413 { 414 if (txq == NULL) 415 return; 416 417 struct enetc_bdr *tx_ring = (struct enetc_bdr *)txq; 418 struct enetc_eth_hw *eth_hw = 419 ENETC_DEV_PRIVATE_TO_HW(tx_ring->ndev->data->dev_private); 420 struct enetc_hw *hw; 421 struct enetc_swbd *tx_swbd; 422 int i; 423 uint32_t val; 424 425 /* Disable the ring */ 426 hw = ð_hw->hw; 427 val = enetc_txbdr_rd(hw, tx_ring->index, ENETC_TBMR); 428 val &= (~ENETC_TBMR_EN); 429 enetc_txbdr_wr(hw, tx_ring->index, ENETC_TBMR, val); 430 431 /* clean the ring*/ 432 i = tx_ring->next_to_clean; 433 tx_swbd = &tx_ring->q_swbd[i]; 434 while (tx_swbd->buffer_addr != NULL) { 435 rte_pktmbuf_free(tx_swbd->buffer_addr); 436 tx_swbd->buffer_addr = NULL; 437 tx_swbd++; 438 i++; 439 if (unlikely(i == tx_ring->bd_count)) { 440 i = 0; 441 tx_swbd = &tx_ring->q_swbd[i]; 442 } 443 } 444 445 enetc_free_bdr(tx_ring); 446 rte_free(tx_ring); 447 } 448 449 static int 450 enetc_alloc_rxbdr(struct enetc_bdr *rxr, 451 uint16_t nb_rx_desc) 452 { 453 int size; 454 455 size = nb_rx_desc * sizeof(struct enetc_swbd); 456 rxr->q_swbd = rte_malloc(NULL, size, RTE_CACHE_LINE_SIZE); 457 if (rxr->q_swbd == NULL) 458 return -ENOMEM; 459 460 size = nb_rx_desc * sizeof(union enetc_rx_bd); 461 rxr->bd_base = rte_malloc(NULL, size, RTE_CACHE_LINE_SIZE); 462 if (rxr->bd_base == NULL) { 463 rte_free(rxr->q_swbd); 464 rxr->q_swbd = NULL; 465 return -ENOMEM; 466 } 467 468 rxr->bd_count = nb_rx_desc; 469 rxr->next_to_clean = 0; 470 rxr->next_to_use = 0; 471 rxr->next_to_alloc = 0; 472 473 return 0; 474 } 475 476 static void 477 enetc_setup_rxbdr(struct enetc_hw *hw, struct enetc_bdr *rx_ring, 478 struct rte_mempool *mb_pool) 479 { 480 int idx = rx_ring->index; 481 uintptr_t base_addr; 482 uint16_t buf_size; 483 484 base_addr = (uintptr_t)rx_ring->bd_base; 485 enetc_rxbdr_wr(hw, idx, ENETC_RBBAR0, 486 lower_32_bits((uint64_t)base_addr)); 487 enetc_rxbdr_wr(hw, idx, ENETC_RBBAR1, 488 upper_32_bits((uint64_t)base_addr)); 489 enetc_rxbdr_wr(hw, idx, ENETC_RBLENR, 490 ENETC_RTBLENR_LEN(rx_ring->bd_count)); 491 492 rx_ring->mb_pool = mb_pool; 493 /* enable ring */ 494 enetc_rxbdr_wr(hw, idx, ENETC_RBMR, ENETC_RBMR_EN); 495 enetc_rxbdr_wr(hw, idx, ENETC_RBPIR, 0); 496 rx_ring->rcir = (void *)((size_t)hw->reg + 497 ENETC_BDR(RX, idx, ENETC_RBCIR)); 498 enetc_refill_rx_ring(rx_ring, (enetc_bd_unused(rx_ring))); 499 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rx_ring->mb_pool) - 500 RTE_PKTMBUF_HEADROOM); 501 enetc_rxbdr_wr(hw, idx, ENETC_RBBSR, buf_size); 502 } 503 504 static int 505 enetc_alloc_rx_resources(struct rte_eth_dev *dev, 506 uint16_t rx_queue_id, 507 uint16_t nb_rx_desc, 508 struct rte_mempool *mb_pool) 509 { 510 int err; 511 struct enetc_bdr *rx_ring; 512 struct rte_eth_dev_data *data = dev->data; 513 struct enetc_eth_adapter *adapter = 514 ENETC_DEV_PRIVATE(data->dev_private); 515 516 rx_ring = rte_zmalloc(NULL, sizeof(struct enetc_bdr), 0); 517 if (rx_ring == NULL) { 518 ENETC_PMD_ERR("Failed to allocate RX ring memory"); 519 err = -ENOMEM; 520 return err; 521 } 522 523 err = enetc_alloc_rxbdr(rx_ring, nb_rx_desc); 524 if (err) 525 goto fail; 526 527 rx_ring->index = rx_queue_id; 528 rx_ring->ndev = dev; 529 enetc_setup_rxbdr(&adapter->hw.hw, rx_ring, mb_pool); 530 data->rx_queues[rx_queue_id] = rx_ring; 531 532 return 0; 533 fail: 534 rte_free(rx_ring); 535 536 return err; 537 } 538 539 static int 540 enetc_rx_queue_setup(struct rte_eth_dev *dev, 541 uint16_t rx_queue_id, 542 uint16_t nb_rx_desc, 543 unsigned int socket_id __rte_unused, 544 const struct rte_eth_rxconf *rx_conf __rte_unused, 545 struct rte_mempool *mb_pool) 546 { 547 int err = 0; 548 549 PMD_INIT_FUNC_TRACE(); 550 if (nb_rx_desc > MAX_BD_COUNT) 551 return -1; 552 553 err = enetc_alloc_rx_resources(dev, rx_queue_id, 554 nb_rx_desc, 555 mb_pool); 556 557 return err; 558 } 559 560 static void 561 enetc_rx_queue_release(void *rxq) 562 { 563 if (rxq == NULL) 564 return; 565 566 struct enetc_bdr *rx_ring = (struct enetc_bdr *)rxq; 567 struct enetc_eth_hw *eth_hw = 568 ENETC_DEV_PRIVATE_TO_HW(rx_ring->ndev->data->dev_private); 569 struct enetc_swbd *q_swbd; 570 struct enetc_hw *hw; 571 uint32_t val; 572 int i; 573 574 /* Disable the ring */ 575 hw = ð_hw->hw; 576 val = enetc_rxbdr_rd(hw, rx_ring->index, ENETC_RBMR); 577 val &= (~ENETC_RBMR_EN); 578 enetc_rxbdr_wr(hw, rx_ring->index, ENETC_RBMR, val); 579 580 /* Clean the ring */ 581 i = rx_ring->next_to_clean; 582 q_swbd = &rx_ring->q_swbd[i]; 583 while (i != rx_ring->next_to_use) { 584 rte_pktmbuf_free(q_swbd->buffer_addr); 585 q_swbd->buffer_addr = NULL; 586 q_swbd++; 587 i++; 588 if (unlikely(i == rx_ring->bd_count)) { 589 i = 0; 590 q_swbd = &rx_ring->q_swbd[i]; 591 } 592 } 593 594 enetc_free_bdr(rx_ring); 595 rte_free(rx_ring); 596 } 597 598 static int 599 enetc_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 600 struct rte_pci_device *pci_dev) 601 { 602 return rte_eth_dev_pci_generic_probe(pci_dev, 603 sizeof(struct enetc_eth_adapter), 604 enetc_dev_init); 605 } 606 607 static int 608 enetc_pci_remove(struct rte_pci_device *pci_dev) 609 { 610 return rte_eth_dev_pci_generic_remove(pci_dev, enetc_dev_uninit); 611 } 612 613 static struct rte_pci_driver rte_enetc_pmd = { 614 .id_table = pci_id_enetc_map, 615 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA, 616 .probe = enetc_pci_probe, 617 .remove = enetc_pci_remove, 618 }; 619 620 RTE_PMD_REGISTER_PCI(net_enetc, rte_enetc_pmd); 621 RTE_PMD_REGISTER_PCI_TABLE(net_enetc, pci_id_enetc_map); 622 RTE_PMD_REGISTER_KMOD_DEP(net_enetc, "* vfio-pci"); 623 624 RTE_INIT(enetc_pmd_init_log) 625 { 626 enetc_logtype_pmd = rte_log_register("pmd.net.enetc"); 627 if (enetc_logtype_pmd >= 0) 628 rte_log_set_level(enetc_logtype_pmd, RTE_LOG_NOTICE); 629 } 630