1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2018-2020 NXP 3 */ 4 5 #include <stdbool.h> 6 #include <rte_ethdev_pci.h> 7 #include <rte_random.h> 8 #include <dpaax_iova_table.h> 9 10 #include "enetc_logs.h" 11 #include "enetc.h" 12 13 static int 14 enetc_dev_start(struct rte_eth_dev *dev) 15 { 16 struct enetc_eth_hw *hw = 17 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private); 18 struct enetc_hw *enetc_hw = &hw->hw; 19 uint32_t val; 20 21 PMD_INIT_FUNC_TRACE(); 22 val = enetc_port_rd(enetc_hw, ENETC_PM0_CMD_CFG); 23 enetc_port_wr(enetc_hw, ENETC_PM0_CMD_CFG, 24 val | ENETC_PM0_TX_EN | ENETC_PM0_RX_EN); 25 26 /* Enable port */ 27 val = enetc_port_rd(enetc_hw, ENETC_PMR); 28 enetc_port_wr(enetc_hw, ENETC_PMR, val | ENETC_PMR_EN); 29 30 /* set auto-speed for RGMII */ 31 if (enetc_port_rd(enetc_hw, ENETC_PM0_IF_MODE) & ENETC_PMO_IFM_RG) { 32 enetc_port_wr(enetc_hw, ENETC_PM0_IF_MODE, 33 ENETC_PM0_IFM_RGAUTO); 34 enetc_port_wr(enetc_hw, ENETC_PM1_IF_MODE, 35 ENETC_PM0_IFM_RGAUTO); 36 } 37 if (enetc_global_rd(enetc_hw, 38 ENETC_G_EPFBLPR(1)) == ENETC_G_EPFBLPR1_XGMII) { 39 enetc_port_wr(enetc_hw, ENETC_PM0_IF_MODE, 40 ENETC_PM0_IFM_XGMII); 41 enetc_port_wr(enetc_hw, ENETC_PM1_IF_MODE, 42 ENETC_PM0_IFM_XGMII); 43 } 44 45 return 0; 46 } 47 48 static void 49 enetc_dev_stop(struct rte_eth_dev *dev) 50 { 51 struct enetc_eth_hw *hw = 52 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private); 53 struct enetc_hw *enetc_hw = &hw->hw; 54 uint32_t val; 55 56 PMD_INIT_FUNC_TRACE(); 57 /* Disable port */ 58 val = enetc_port_rd(enetc_hw, ENETC_PMR); 59 enetc_port_wr(enetc_hw, ENETC_PMR, val & (~ENETC_PMR_EN)); 60 61 val = enetc_port_rd(enetc_hw, ENETC_PM0_CMD_CFG); 62 enetc_port_wr(enetc_hw, ENETC_PM0_CMD_CFG, 63 val & (~(ENETC_PM0_TX_EN | ENETC_PM0_RX_EN))); 64 } 65 66 static const uint32_t * 67 enetc_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused) 68 { 69 static const uint32_t ptypes[] = { 70 RTE_PTYPE_L2_ETHER, 71 RTE_PTYPE_L3_IPV4, 72 RTE_PTYPE_L3_IPV6, 73 RTE_PTYPE_L4_TCP, 74 RTE_PTYPE_L4_UDP, 75 RTE_PTYPE_L4_SCTP, 76 RTE_PTYPE_L4_ICMP, 77 RTE_PTYPE_UNKNOWN 78 }; 79 80 return ptypes; 81 } 82 83 /* return 0 means link status changed, -1 means not changed */ 84 static int 85 enetc_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused) 86 { 87 struct enetc_eth_hw *hw = 88 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private); 89 struct enetc_hw *enetc_hw = &hw->hw; 90 struct rte_eth_link link; 91 uint32_t status; 92 93 PMD_INIT_FUNC_TRACE(); 94 95 memset(&link, 0, sizeof(link)); 96 97 status = enetc_port_rd(enetc_hw, ENETC_PM0_STATUS); 98 99 if (status & ENETC_LINK_MODE) 100 link.link_duplex = ETH_LINK_FULL_DUPLEX; 101 else 102 link.link_duplex = ETH_LINK_HALF_DUPLEX; 103 104 if (status & ENETC_LINK_STATUS) 105 link.link_status = ETH_LINK_UP; 106 else 107 link.link_status = ETH_LINK_DOWN; 108 109 switch (status & ENETC_LINK_SPEED_MASK) { 110 case ENETC_LINK_SPEED_1G: 111 link.link_speed = ETH_SPEED_NUM_1G; 112 break; 113 114 case ENETC_LINK_SPEED_100M: 115 link.link_speed = ETH_SPEED_NUM_100M; 116 break; 117 118 default: 119 case ENETC_LINK_SPEED_10M: 120 link.link_speed = ETH_SPEED_NUM_10M; 121 } 122 123 return rte_eth_linkstatus_set(dev, &link); 124 } 125 126 static void 127 print_ethaddr(const char *name, const struct rte_ether_addr *eth_addr) 128 { 129 char buf[RTE_ETHER_ADDR_FMT_SIZE]; 130 131 rte_ether_format_addr(buf, RTE_ETHER_ADDR_FMT_SIZE, eth_addr); 132 ENETC_PMD_NOTICE("%s%s\n", name, buf); 133 } 134 135 static int 136 enetc_hardware_init(struct enetc_eth_hw *hw) 137 { 138 struct enetc_hw *enetc_hw = &hw->hw; 139 uint32_t *mac = (uint32_t *)hw->mac.addr; 140 uint32_t high_mac = 0; 141 uint16_t low_mac = 0; 142 143 PMD_INIT_FUNC_TRACE(); 144 /* Calculating and storing the base HW addresses */ 145 hw->hw.port = (void *)((size_t)hw->hw.reg + ENETC_PORT_BASE); 146 hw->hw.global = (void *)((size_t)hw->hw.reg + ENETC_GLOBAL_BASE); 147 148 /* WA for Rx lock-up HW erratum */ 149 enetc_port_wr(enetc_hw, ENETC_PM0_RX_FIFO, 1); 150 151 /* set ENETC transaction flags to coherent, don't allocate. 152 * BD writes merge with surrounding cache line data, frame data writes 153 * overwrite cache line. 154 */ 155 enetc_wr(enetc_hw, ENETC_SICAR0, ENETC_SICAR0_COHERENT); 156 157 /* Enabling Station Interface */ 158 enetc_wr(enetc_hw, ENETC_SIMR, ENETC_SIMR_EN); 159 160 *mac = (uint32_t)enetc_port_rd(enetc_hw, ENETC_PSIPMAR0(0)); 161 high_mac = (uint32_t)*mac; 162 mac++; 163 *mac = (uint16_t)enetc_port_rd(enetc_hw, ENETC_PSIPMAR1(0)); 164 low_mac = (uint16_t)*mac; 165 166 if ((high_mac | low_mac) == 0) { 167 char *first_byte; 168 169 ENETC_PMD_NOTICE("MAC is not available for this SI, " 170 "set random MAC\n"); 171 mac = (uint32_t *)hw->mac.addr; 172 *mac = (uint32_t)rte_rand(); 173 first_byte = (char *)mac; 174 *first_byte &= 0xfe; /* clear multicast bit */ 175 *first_byte |= 0x02; /* set local assignment bit (IEEE802) */ 176 177 enetc_port_wr(enetc_hw, ENETC_PSIPMAR0(0), *mac); 178 mac++; 179 *mac = (uint16_t)rte_rand(); 180 enetc_port_wr(enetc_hw, ENETC_PSIPMAR1(0), *mac); 181 print_ethaddr("New address: ", 182 (const struct rte_ether_addr *)hw->mac.addr); 183 } 184 185 return 0; 186 } 187 188 static int 189 enetc_dev_infos_get(struct rte_eth_dev *dev __rte_unused, 190 struct rte_eth_dev_info *dev_info) 191 { 192 PMD_INIT_FUNC_TRACE(); 193 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) { 194 .nb_max = MAX_BD_COUNT, 195 .nb_min = MIN_BD_COUNT, 196 .nb_align = BD_ALIGN, 197 }; 198 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) { 199 .nb_max = MAX_BD_COUNT, 200 .nb_min = MIN_BD_COUNT, 201 .nb_align = BD_ALIGN, 202 }; 203 dev_info->max_rx_queues = MAX_RX_RINGS; 204 dev_info->max_tx_queues = MAX_TX_RINGS; 205 dev_info->max_rx_pktlen = ENETC_MAC_MAXFRM_SIZE; 206 dev_info->rx_offload_capa = 207 (DEV_RX_OFFLOAD_IPV4_CKSUM | 208 DEV_RX_OFFLOAD_UDP_CKSUM | 209 DEV_RX_OFFLOAD_TCP_CKSUM | 210 DEV_RX_OFFLOAD_KEEP_CRC | 211 DEV_RX_OFFLOAD_JUMBO_FRAME); 212 213 return 0; 214 } 215 216 static int 217 enetc_alloc_txbdr(struct enetc_bdr *txr, uint16_t nb_desc) 218 { 219 int size; 220 221 size = nb_desc * sizeof(struct enetc_swbd); 222 txr->q_swbd = rte_malloc(NULL, size, ENETC_BD_RING_ALIGN); 223 if (txr->q_swbd == NULL) 224 return -ENOMEM; 225 226 size = nb_desc * sizeof(struct enetc_tx_bd); 227 txr->bd_base = rte_malloc(NULL, size, ENETC_BD_RING_ALIGN); 228 if (txr->bd_base == NULL) { 229 rte_free(txr->q_swbd); 230 txr->q_swbd = NULL; 231 return -ENOMEM; 232 } 233 234 txr->bd_count = nb_desc; 235 txr->next_to_clean = 0; 236 txr->next_to_use = 0; 237 238 return 0; 239 } 240 241 static void 242 enetc_free_bdr(struct enetc_bdr *rxr) 243 { 244 rte_free(rxr->q_swbd); 245 rte_free(rxr->bd_base); 246 rxr->q_swbd = NULL; 247 rxr->bd_base = NULL; 248 } 249 250 static void 251 enetc_setup_txbdr(struct enetc_hw *hw, struct enetc_bdr *tx_ring) 252 { 253 int idx = tx_ring->index; 254 phys_addr_t bd_address; 255 256 bd_address = (phys_addr_t) 257 rte_mem_virt2iova((const void *)tx_ring->bd_base); 258 enetc_txbdr_wr(hw, idx, ENETC_TBBAR0, 259 lower_32_bits((uint64_t)bd_address)); 260 enetc_txbdr_wr(hw, idx, ENETC_TBBAR1, 261 upper_32_bits((uint64_t)bd_address)); 262 enetc_txbdr_wr(hw, idx, ENETC_TBLENR, 263 ENETC_RTBLENR_LEN(tx_ring->bd_count)); 264 265 enetc_txbdr_wr(hw, idx, ENETC_TBCIR, 0); 266 enetc_txbdr_wr(hw, idx, ENETC_TBCISR, 0); 267 tx_ring->tcir = (void *)((size_t)hw->reg + 268 ENETC_BDR(TX, idx, ENETC_TBCIR)); 269 tx_ring->tcisr = (void *)((size_t)hw->reg + 270 ENETC_BDR(TX, idx, ENETC_TBCISR)); 271 } 272 273 static int 274 enetc_tx_queue_setup(struct rte_eth_dev *dev, 275 uint16_t queue_idx, 276 uint16_t nb_desc, 277 unsigned int socket_id __rte_unused, 278 const struct rte_eth_txconf *tx_conf) 279 { 280 int err = 0; 281 struct enetc_bdr *tx_ring; 282 struct rte_eth_dev_data *data = dev->data; 283 struct enetc_eth_adapter *priv = 284 ENETC_DEV_PRIVATE(data->dev_private); 285 286 PMD_INIT_FUNC_TRACE(); 287 if (nb_desc > MAX_BD_COUNT) 288 return -1; 289 290 tx_ring = rte_zmalloc(NULL, sizeof(struct enetc_bdr), 0); 291 if (tx_ring == NULL) { 292 ENETC_PMD_ERR("Failed to allocate TX ring memory"); 293 err = -ENOMEM; 294 return -1; 295 } 296 297 err = enetc_alloc_txbdr(tx_ring, nb_desc); 298 if (err) 299 goto fail; 300 301 tx_ring->index = queue_idx; 302 tx_ring->ndev = dev; 303 enetc_setup_txbdr(&priv->hw.hw, tx_ring); 304 data->tx_queues[queue_idx] = tx_ring; 305 306 if (!tx_conf->tx_deferred_start) { 307 /* enable ring */ 308 enetc_txbdr_wr(&priv->hw.hw, tx_ring->index, 309 ENETC_TBMR, ENETC_TBMR_EN); 310 dev->data->tx_queue_state[tx_ring->index] = 311 RTE_ETH_QUEUE_STATE_STARTED; 312 } else { 313 dev->data->tx_queue_state[tx_ring->index] = 314 RTE_ETH_QUEUE_STATE_STOPPED; 315 } 316 317 return 0; 318 fail: 319 rte_free(tx_ring); 320 321 return err; 322 } 323 324 static void 325 enetc_tx_queue_release(void *txq) 326 { 327 if (txq == NULL) 328 return; 329 330 struct enetc_bdr *tx_ring = (struct enetc_bdr *)txq; 331 struct enetc_eth_hw *eth_hw = 332 ENETC_DEV_PRIVATE_TO_HW(tx_ring->ndev->data->dev_private); 333 struct enetc_hw *hw; 334 struct enetc_swbd *tx_swbd; 335 int i; 336 uint32_t val; 337 338 /* Disable the ring */ 339 hw = ð_hw->hw; 340 val = enetc_txbdr_rd(hw, tx_ring->index, ENETC_TBMR); 341 val &= (~ENETC_TBMR_EN); 342 enetc_txbdr_wr(hw, tx_ring->index, ENETC_TBMR, val); 343 344 /* clean the ring*/ 345 i = tx_ring->next_to_clean; 346 tx_swbd = &tx_ring->q_swbd[i]; 347 while (tx_swbd->buffer_addr != NULL) { 348 rte_pktmbuf_free(tx_swbd->buffer_addr); 349 tx_swbd->buffer_addr = NULL; 350 tx_swbd++; 351 i++; 352 if (unlikely(i == tx_ring->bd_count)) { 353 i = 0; 354 tx_swbd = &tx_ring->q_swbd[i]; 355 } 356 } 357 358 enetc_free_bdr(tx_ring); 359 rte_free(tx_ring); 360 } 361 362 static int 363 enetc_alloc_rxbdr(struct enetc_bdr *rxr, 364 uint16_t nb_rx_desc) 365 { 366 int size; 367 368 size = nb_rx_desc * sizeof(struct enetc_swbd); 369 rxr->q_swbd = rte_malloc(NULL, size, ENETC_BD_RING_ALIGN); 370 if (rxr->q_swbd == NULL) 371 return -ENOMEM; 372 373 size = nb_rx_desc * sizeof(union enetc_rx_bd); 374 rxr->bd_base = rte_malloc(NULL, size, ENETC_BD_RING_ALIGN); 375 if (rxr->bd_base == NULL) { 376 rte_free(rxr->q_swbd); 377 rxr->q_swbd = NULL; 378 return -ENOMEM; 379 } 380 381 rxr->bd_count = nb_rx_desc; 382 rxr->next_to_clean = 0; 383 rxr->next_to_use = 0; 384 rxr->next_to_alloc = 0; 385 386 return 0; 387 } 388 389 static void 390 enetc_setup_rxbdr(struct enetc_hw *hw, struct enetc_bdr *rx_ring, 391 struct rte_mempool *mb_pool) 392 { 393 int idx = rx_ring->index; 394 uint16_t buf_size; 395 phys_addr_t bd_address; 396 397 bd_address = (phys_addr_t) 398 rte_mem_virt2iova((const void *)rx_ring->bd_base); 399 enetc_rxbdr_wr(hw, idx, ENETC_RBBAR0, 400 lower_32_bits((uint64_t)bd_address)); 401 enetc_rxbdr_wr(hw, idx, ENETC_RBBAR1, 402 upper_32_bits((uint64_t)bd_address)); 403 enetc_rxbdr_wr(hw, idx, ENETC_RBLENR, 404 ENETC_RTBLENR_LEN(rx_ring->bd_count)); 405 406 rx_ring->mb_pool = mb_pool; 407 rx_ring->rcir = (void *)((size_t)hw->reg + 408 ENETC_BDR(RX, idx, ENETC_RBCIR)); 409 enetc_refill_rx_ring(rx_ring, (enetc_bd_unused(rx_ring))); 410 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rx_ring->mb_pool) - 411 RTE_PKTMBUF_HEADROOM); 412 enetc_rxbdr_wr(hw, idx, ENETC_RBBSR, buf_size); 413 enetc_rxbdr_wr(hw, idx, ENETC_RBPIR, 0); 414 } 415 416 static int 417 enetc_rx_queue_setup(struct rte_eth_dev *dev, 418 uint16_t rx_queue_id, 419 uint16_t nb_rx_desc, 420 unsigned int socket_id __rte_unused, 421 const struct rte_eth_rxconf *rx_conf, 422 struct rte_mempool *mb_pool) 423 { 424 int err = 0; 425 struct enetc_bdr *rx_ring; 426 struct rte_eth_dev_data *data = dev->data; 427 struct enetc_eth_adapter *adapter = 428 ENETC_DEV_PRIVATE(data->dev_private); 429 uint64_t rx_offloads = data->dev_conf.rxmode.offloads; 430 431 PMD_INIT_FUNC_TRACE(); 432 if (nb_rx_desc > MAX_BD_COUNT) 433 return -1; 434 435 rx_ring = rte_zmalloc(NULL, sizeof(struct enetc_bdr), 0); 436 if (rx_ring == NULL) { 437 ENETC_PMD_ERR("Failed to allocate RX ring memory"); 438 err = -ENOMEM; 439 return err; 440 } 441 442 err = enetc_alloc_rxbdr(rx_ring, nb_rx_desc); 443 if (err) 444 goto fail; 445 446 rx_ring->index = rx_queue_id; 447 rx_ring->ndev = dev; 448 enetc_setup_rxbdr(&adapter->hw.hw, rx_ring, mb_pool); 449 data->rx_queues[rx_queue_id] = rx_ring; 450 451 if (!rx_conf->rx_deferred_start) { 452 /* enable ring */ 453 enetc_rxbdr_wr(&adapter->hw.hw, rx_ring->index, ENETC_RBMR, 454 ENETC_RBMR_EN); 455 dev->data->rx_queue_state[rx_ring->index] = 456 RTE_ETH_QUEUE_STATE_STARTED; 457 } else { 458 dev->data->rx_queue_state[rx_ring->index] = 459 RTE_ETH_QUEUE_STATE_STOPPED; 460 } 461 462 rx_ring->crc_len = (uint8_t)((rx_offloads & DEV_RX_OFFLOAD_KEEP_CRC) ? 463 RTE_ETHER_CRC_LEN : 0); 464 465 return 0; 466 fail: 467 rte_free(rx_ring); 468 469 return err; 470 } 471 472 static void 473 enetc_rx_queue_release(void *rxq) 474 { 475 if (rxq == NULL) 476 return; 477 478 struct enetc_bdr *rx_ring = (struct enetc_bdr *)rxq; 479 struct enetc_eth_hw *eth_hw = 480 ENETC_DEV_PRIVATE_TO_HW(rx_ring->ndev->data->dev_private); 481 struct enetc_swbd *q_swbd; 482 struct enetc_hw *hw; 483 uint32_t val; 484 int i; 485 486 /* Disable the ring */ 487 hw = ð_hw->hw; 488 val = enetc_rxbdr_rd(hw, rx_ring->index, ENETC_RBMR); 489 val &= (~ENETC_RBMR_EN); 490 enetc_rxbdr_wr(hw, rx_ring->index, ENETC_RBMR, val); 491 492 /* Clean the ring */ 493 i = rx_ring->next_to_clean; 494 q_swbd = &rx_ring->q_swbd[i]; 495 while (i != rx_ring->next_to_use) { 496 rte_pktmbuf_free(q_swbd->buffer_addr); 497 q_swbd->buffer_addr = NULL; 498 q_swbd++; 499 i++; 500 if (unlikely(i == rx_ring->bd_count)) { 501 i = 0; 502 q_swbd = &rx_ring->q_swbd[i]; 503 } 504 } 505 506 enetc_free_bdr(rx_ring); 507 rte_free(rx_ring); 508 } 509 510 static 511 int enetc_stats_get(struct rte_eth_dev *dev, 512 struct rte_eth_stats *stats) 513 { 514 struct enetc_eth_hw *hw = 515 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private); 516 struct enetc_hw *enetc_hw = &hw->hw; 517 518 /* Total received packets, bad + good, if we want to get counters of 519 * only good received packets then use ENETC_PM0_RFRM, 520 * ENETC_PM0_TFRM registers. 521 */ 522 stats->ipackets = enetc_port_rd(enetc_hw, ENETC_PM0_RPKT); 523 stats->opackets = enetc_port_rd(enetc_hw, ENETC_PM0_TPKT); 524 stats->ibytes = enetc_port_rd(enetc_hw, ENETC_PM0_REOCT); 525 stats->obytes = enetc_port_rd(enetc_hw, ENETC_PM0_TEOCT); 526 /* Dropped + Truncated packets, use ENETC_PM0_RDRNTP for without 527 * truncated packets 528 */ 529 stats->imissed = enetc_port_rd(enetc_hw, ENETC_PM0_RDRP); 530 stats->ierrors = enetc_port_rd(enetc_hw, ENETC_PM0_RERR); 531 stats->oerrors = enetc_port_rd(enetc_hw, ENETC_PM0_TERR); 532 533 return 0; 534 } 535 536 static int 537 enetc_stats_reset(struct rte_eth_dev *dev) 538 { 539 struct enetc_eth_hw *hw = 540 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private); 541 struct enetc_hw *enetc_hw = &hw->hw; 542 543 enetc_port_wr(enetc_hw, ENETC_PM0_STAT_CONFIG, ENETC_CLEAR_STATS); 544 545 return 0; 546 } 547 548 static void 549 enetc_dev_close(struct rte_eth_dev *dev) 550 { 551 uint16_t i; 552 553 PMD_INIT_FUNC_TRACE(); 554 enetc_dev_stop(dev); 555 556 for (i = 0; i < dev->data->nb_rx_queues; i++) { 557 enetc_rx_queue_release(dev->data->rx_queues[i]); 558 dev->data->rx_queues[i] = NULL; 559 } 560 dev->data->nb_rx_queues = 0; 561 562 for (i = 0; i < dev->data->nb_tx_queues; i++) { 563 enetc_tx_queue_release(dev->data->tx_queues[i]); 564 dev->data->tx_queues[i] = NULL; 565 } 566 dev->data->nb_tx_queues = 0; 567 } 568 569 static int 570 enetc_promiscuous_enable(struct rte_eth_dev *dev) 571 { 572 struct enetc_eth_hw *hw = 573 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private); 574 struct enetc_hw *enetc_hw = &hw->hw; 575 uint32_t psipmr = 0; 576 577 psipmr = enetc_port_rd(enetc_hw, ENETC_PSIPMR); 578 579 /* Setting to enable promiscuous mode*/ 580 psipmr |= ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0); 581 582 enetc_port_wr(enetc_hw, ENETC_PSIPMR, psipmr); 583 584 return 0; 585 } 586 587 static int 588 enetc_promiscuous_disable(struct rte_eth_dev *dev) 589 { 590 struct enetc_eth_hw *hw = 591 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private); 592 struct enetc_hw *enetc_hw = &hw->hw; 593 uint32_t psipmr = 0; 594 595 /* Setting to disable promiscuous mode for SI0*/ 596 psipmr = enetc_port_rd(enetc_hw, ENETC_PSIPMR); 597 psipmr &= (~ENETC_PSIPMR_SET_UP(0)); 598 599 if (dev->data->all_multicast == 0) 600 psipmr &= (~ENETC_PSIPMR_SET_MP(0)); 601 602 enetc_port_wr(enetc_hw, ENETC_PSIPMR, psipmr); 603 604 return 0; 605 } 606 607 static int 608 enetc_allmulticast_enable(struct rte_eth_dev *dev) 609 { 610 struct enetc_eth_hw *hw = 611 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private); 612 struct enetc_hw *enetc_hw = &hw->hw; 613 uint32_t psipmr = 0; 614 615 psipmr = enetc_port_rd(enetc_hw, ENETC_PSIPMR); 616 617 /* Setting to enable allmulticast mode for SI0*/ 618 psipmr |= ENETC_PSIPMR_SET_MP(0); 619 620 enetc_port_wr(enetc_hw, ENETC_PSIPMR, psipmr); 621 622 return 0; 623 } 624 625 static int 626 enetc_allmulticast_disable(struct rte_eth_dev *dev) 627 { 628 struct enetc_eth_hw *hw = 629 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private); 630 struct enetc_hw *enetc_hw = &hw->hw; 631 uint32_t psipmr = 0; 632 633 if (dev->data->promiscuous == 1) 634 return 0; /* must remain in all_multicast mode */ 635 636 /* Setting to disable all multicast mode for SI0*/ 637 psipmr = enetc_port_rd(enetc_hw, ENETC_PSIPMR) & 638 ~(ENETC_PSIPMR_SET_MP(0)); 639 640 enetc_port_wr(enetc_hw, ENETC_PSIPMR, psipmr); 641 642 return 0; 643 } 644 645 static int 646 enetc_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 647 { 648 struct enetc_eth_hw *hw = 649 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private); 650 struct enetc_hw *enetc_hw = &hw->hw; 651 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN; 652 653 /* check that mtu is within the allowed range */ 654 if (mtu < ENETC_MAC_MINFRM_SIZE || frame_size > ENETC_MAC_MAXFRM_SIZE) 655 return -EINVAL; 656 657 /* 658 * Refuse mtu that requires the support of scattered packets 659 * when this feature has not been enabled before. 660 */ 661 if (dev->data->min_rx_buf_size && 662 !dev->data->scattered_rx && frame_size > 663 dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) { 664 ENETC_PMD_ERR("SG not enabled, will not fit in one buffer"); 665 return -EINVAL; 666 } 667 668 if (frame_size > RTE_ETHER_MAX_LEN) 669 dev->data->dev_conf.rxmode.offloads &= 670 DEV_RX_OFFLOAD_JUMBO_FRAME; 671 else 672 dev->data->dev_conf.rxmode.offloads &= 673 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 674 675 enetc_port_wr(enetc_hw, ENETC_PTCMSDUR(0), ENETC_MAC_MAXFRM_SIZE); 676 enetc_port_wr(enetc_hw, ENETC_PTXMBAR, 2 * ENETC_MAC_MAXFRM_SIZE); 677 678 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 679 680 /*setting the MTU*/ 681 enetc_port_wr(enetc_hw, ENETC_PM0_MAXFRM, ENETC_SET_MAXFRM(frame_size) | 682 ENETC_SET_TX_MTU(ENETC_MAC_MAXFRM_SIZE)); 683 684 return 0; 685 } 686 687 static int 688 enetc_dev_configure(struct rte_eth_dev *dev) 689 { 690 struct enetc_eth_hw *hw = 691 ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private); 692 struct enetc_hw *enetc_hw = &hw->hw; 693 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 694 uint64_t rx_offloads = eth_conf->rxmode.offloads; 695 uint32_t checksum = L3_CKSUM | L4_CKSUM; 696 697 PMD_INIT_FUNC_TRACE(); 698 699 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 700 uint32_t max_len; 701 702 max_len = dev->data->dev_conf.rxmode.max_rx_pkt_len; 703 704 enetc_port_wr(enetc_hw, ENETC_PM0_MAXFRM, 705 ENETC_SET_MAXFRM(max_len)); 706 enetc_port_wr(enetc_hw, ENETC_PTCMSDUR(0), 707 ENETC_MAC_MAXFRM_SIZE); 708 enetc_port_wr(enetc_hw, ENETC_PTXMBAR, 709 2 * ENETC_MAC_MAXFRM_SIZE); 710 dev->data->mtu = RTE_ETHER_MAX_LEN - RTE_ETHER_HDR_LEN - 711 RTE_ETHER_CRC_LEN; 712 } 713 714 if (rx_offloads & DEV_RX_OFFLOAD_KEEP_CRC) { 715 int config; 716 717 config = enetc_port_rd(enetc_hw, ENETC_PM0_CMD_CFG); 718 config |= ENETC_PM0_CRC; 719 enetc_port_wr(enetc_hw, ENETC_PM0_CMD_CFG, config); 720 } 721 722 if (rx_offloads & DEV_RX_OFFLOAD_IPV4_CKSUM) 723 checksum &= ~L3_CKSUM; 724 725 if (rx_offloads & (DEV_RX_OFFLOAD_UDP_CKSUM | DEV_RX_OFFLOAD_TCP_CKSUM)) 726 checksum &= ~L4_CKSUM; 727 728 enetc_port_wr(enetc_hw, ENETC_PAR_PORT_CFG, checksum); 729 730 731 return 0; 732 } 733 734 static int 735 enetc_rx_queue_start(struct rte_eth_dev *dev, uint16_t qidx) 736 { 737 struct enetc_eth_adapter *priv = 738 ENETC_DEV_PRIVATE(dev->data->dev_private); 739 struct enetc_bdr *rx_ring; 740 uint32_t rx_data; 741 742 rx_ring = dev->data->rx_queues[qidx]; 743 if (dev->data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED) { 744 rx_data = enetc_rxbdr_rd(&priv->hw.hw, rx_ring->index, 745 ENETC_RBMR); 746 rx_data = rx_data | ENETC_RBMR_EN; 747 enetc_rxbdr_wr(&priv->hw.hw, rx_ring->index, ENETC_RBMR, 748 rx_data); 749 dev->data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED; 750 } 751 752 return 0; 753 } 754 755 static int 756 enetc_rx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx) 757 { 758 struct enetc_eth_adapter *priv = 759 ENETC_DEV_PRIVATE(dev->data->dev_private); 760 struct enetc_bdr *rx_ring; 761 uint32_t rx_data; 762 763 rx_ring = dev->data->rx_queues[qidx]; 764 if (dev->data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED) { 765 rx_data = enetc_rxbdr_rd(&priv->hw.hw, rx_ring->index, 766 ENETC_RBMR); 767 rx_data = rx_data & (~ENETC_RBMR_EN); 768 enetc_rxbdr_wr(&priv->hw.hw, rx_ring->index, ENETC_RBMR, 769 rx_data); 770 dev->data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED; 771 } 772 773 return 0; 774 } 775 776 static int 777 enetc_tx_queue_start(struct rte_eth_dev *dev, uint16_t qidx) 778 { 779 struct enetc_eth_adapter *priv = 780 ENETC_DEV_PRIVATE(dev->data->dev_private); 781 struct enetc_bdr *tx_ring; 782 uint32_t tx_data; 783 784 tx_ring = dev->data->tx_queues[qidx]; 785 if (dev->data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED) { 786 tx_data = enetc_txbdr_rd(&priv->hw.hw, tx_ring->index, 787 ENETC_TBMR); 788 tx_data = tx_data | ENETC_TBMR_EN; 789 enetc_txbdr_wr(&priv->hw.hw, tx_ring->index, ENETC_TBMR, 790 tx_data); 791 dev->data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED; 792 } 793 794 return 0; 795 } 796 797 static int 798 enetc_tx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx) 799 { 800 struct enetc_eth_adapter *priv = 801 ENETC_DEV_PRIVATE(dev->data->dev_private); 802 struct enetc_bdr *tx_ring; 803 uint32_t tx_data; 804 805 tx_ring = dev->data->tx_queues[qidx]; 806 if (dev->data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED) { 807 tx_data = enetc_txbdr_rd(&priv->hw.hw, tx_ring->index, 808 ENETC_TBMR); 809 tx_data = tx_data & (~ENETC_TBMR_EN); 810 enetc_txbdr_wr(&priv->hw.hw, tx_ring->index, ENETC_TBMR, 811 tx_data); 812 dev->data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED; 813 } 814 815 return 0; 816 } 817 818 /* 819 * The set of PCI devices this driver supports 820 */ 821 static const struct rte_pci_id pci_id_enetc_map[] = { 822 { RTE_PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID) }, 823 { RTE_PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID_VF) }, 824 { .vendor_id = 0, /* sentinel */ }, 825 }; 826 827 /* Features supported by this driver */ 828 static const struct eth_dev_ops enetc_ops = { 829 .dev_configure = enetc_dev_configure, 830 .dev_start = enetc_dev_start, 831 .dev_stop = enetc_dev_stop, 832 .dev_close = enetc_dev_close, 833 .link_update = enetc_link_update, 834 .stats_get = enetc_stats_get, 835 .stats_reset = enetc_stats_reset, 836 .promiscuous_enable = enetc_promiscuous_enable, 837 .promiscuous_disable = enetc_promiscuous_disable, 838 .allmulticast_enable = enetc_allmulticast_enable, 839 .allmulticast_disable = enetc_allmulticast_disable, 840 .dev_infos_get = enetc_dev_infos_get, 841 .mtu_set = enetc_mtu_set, 842 .rx_queue_setup = enetc_rx_queue_setup, 843 .rx_queue_start = enetc_rx_queue_start, 844 .rx_queue_stop = enetc_rx_queue_stop, 845 .rx_queue_release = enetc_rx_queue_release, 846 .tx_queue_setup = enetc_tx_queue_setup, 847 .tx_queue_start = enetc_tx_queue_start, 848 .tx_queue_stop = enetc_tx_queue_stop, 849 .tx_queue_release = enetc_tx_queue_release, 850 .dev_supported_ptypes_get = enetc_supported_ptypes_get, 851 }; 852 853 /** 854 * Initialisation of the enetc device 855 * 856 * @param eth_dev 857 * - Pointer to the structure rte_eth_dev 858 * 859 * @return 860 * - On success, zero. 861 * - On failure, negative value. 862 */ 863 static int 864 enetc_dev_init(struct rte_eth_dev *eth_dev) 865 { 866 int error = 0; 867 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 868 struct enetc_eth_hw *hw = 869 ENETC_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); 870 871 PMD_INIT_FUNC_TRACE(); 872 eth_dev->dev_ops = &enetc_ops; 873 eth_dev->rx_pkt_burst = &enetc_recv_pkts; 874 eth_dev->tx_pkt_burst = &enetc_xmit_pkts; 875 876 /* Retrieving and storing the HW base address of device */ 877 hw->hw.reg = (void *)pci_dev->mem_resource[0].addr; 878 hw->device_id = pci_dev->id.device_id; 879 880 error = enetc_hardware_init(hw); 881 if (error != 0) { 882 ENETC_PMD_ERR("Hardware initialization failed"); 883 return -1; 884 } 885 886 /* Allocate memory for storing MAC addresses */ 887 eth_dev->data->mac_addrs = rte_zmalloc("enetc_eth", 888 RTE_ETHER_ADDR_LEN, 0); 889 if (!eth_dev->data->mac_addrs) { 890 ENETC_PMD_ERR("Failed to allocate %d bytes needed to " 891 "store MAC addresses", 892 RTE_ETHER_ADDR_LEN * 1); 893 error = -ENOMEM; 894 return -1; 895 } 896 897 /* Copy the permanent MAC address */ 898 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr, 899 ð_dev->data->mac_addrs[0]); 900 901 /* Set MTU */ 902 enetc_port_wr(&hw->hw, ENETC_PM0_MAXFRM, 903 ENETC_SET_MAXFRM(RTE_ETHER_MAX_LEN)); 904 eth_dev->data->mtu = RTE_ETHER_MAX_LEN - RTE_ETHER_HDR_LEN - 905 RTE_ETHER_CRC_LEN; 906 907 if (rte_eal_iova_mode() == RTE_IOVA_PA) 908 dpaax_iova_table_populate(); 909 910 ENETC_PMD_DEBUG("port_id %d vendorID=0x%x deviceID=0x%x", 911 eth_dev->data->port_id, pci_dev->id.vendor_id, 912 pci_dev->id.device_id); 913 return 0; 914 } 915 916 static int 917 enetc_dev_uninit(struct rte_eth_dev *eth_dev __rte_unused) 918 { 919 PMD_INIT_FUNC_TRACE(); 920 921 if (rte_eal_iova_mode() == RTE_IOVA_PA) 922 dpaax_iova_table_depopulate(); 923 924 return 0; 925 } 926 927 static int 928 enetc_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 929 struct rte_pci_device *pci_dev) 930 { 931 return rte_eth_dev_pci_generic_probe(pci_dev, 932 sizeof(struct enetc_eth_adapter), 933 enetc_dev_init); 934 } 935 936 static int 937 enetc_pci_remove(struct rte_pci_device *pci_dev) 938 { 939 return rte_eth_dev_pci_generic_remove(pci_dev, enetc_dev_uninit); 940 } 941 942 static struct rte_pci_driver rte_enetc_pmd = { 943 .id_table = pci_id_enetc_map, 944 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 945 .probe = enetc_pci_probe, 946 .remove = enetc_pci_remove, 947 }; 948 949 RTE_PMD_REGISTER_PCI(net_enetc, rte_enetc_pmd); 950 RTE_PMD_REGISTER_PCI_TABLE(net_enetc, pci_id_enetc_map); 951 RTE_PMD_REGISTER_KMOD_DEP(net_enetc, "* vfio-pci"); 952 RTE_LOG_REGISTER(enetc_logtype_pmd, pmd.net.enetc, NOTICE); 953