1 /*- 2 * BSD LICENSE 3 * 4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of copyright holder nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _ENA_ETHDEV_H_ 35 #define _ENA_ETHDEV_H_ 36 37 #include <rte_cycles.h> 38 #include <rte_pci.h> 39 #include <rte_bus_pci.h> 40 #include <rte_timer.h> 41 42 #include "ena_com.h" 43 44 #define ENA_REGS_BAR 0 45 #define ENA_MEM_BAR 2 46 47 #define ENA_MAX_NUM_QUEUES 128 48 #define ENA_MIN_FRAME_LEN 64 49 #define ENA_NAME_MAX_LEN 20 50 #define ENA_PKT_MAX_BUFS 17 51 52 #define ENA_MIN_MTU 128 53 54 #define ENA_MMIO_DISABLE_REG_READ BIT(0) 55 56 #define ENA_WD_TIMEOUT_SEC 3 57 #define ENA_DEVICE_KALIVE_TIMEOUT (ENA_WD_TIMEOUT_SEC * rte_get_timer_hz()) 58 59 struct ena_adapter; 60 61 enum ena_ring_type { 62 ENA_RING_TYPE_RX = 1, 63 ENA_RING_TYPE_TX = 2, 64 }; 65 66 struct ena_tx_buffer { 67 struct rte_mbuf *mbuf; 68 unsigned int tx_descs; 69 unsigned int num_of_bufs; 70 struct ena_com_buf bufs[ENA_PKT_MAX_BUFS]; 71 }; 72 73 struct ena_calc_queue_size_ctx { 74 struct ena_com_dev_get_features_ctx *get_feat_ctx; 75 struct ena_com_dev *ena_dev; 76 u16 rx_queue_size; 77 u16 tx_queue_size; 78 u16 max_tx_sgl_size; 79 u16 max_rx_sgl_size; 80 }; 81 82 struct ena_stats_tx { 83 u64 cnt; 84 u64 bytes; 85 u64 prepare_ctx_err; 86 u64 linearize; 87 u64 linearize_failed; 88 u64 tx_poll; 89 u64 doorbells; 90 u64 bad_req_id; 91 u64 available_desc; 92 }; 93 94 struct ena_stats_rx { 95 u64 cnt; 96 u64 bytes; 97 u64 refill_partial; 98 u64 bad_csum; 99 u64 mbuf_alloc_fail; 100 u64 bad_desc_num; 101 u64 bad_req_id; 102 }; 103 104 struct ena_ring { 105 u16 next_to_use; 106 u16 next_to_clean; 107 108 enum ena_ring_type type; 109 enum ena_admin_placement_policy_type tx_mem_queue_type; 110 /* Holds the empty requests for TX/RX OOO completions */ 111 union { 112 uint16_t *empty_tx_reqs; 113 uint16_t *empty_rx_reqs; 114 }; 115 116 union { 117 struct ena_tx_buffer *tx_buffer_info; /* contex of tx packet */ 118 struct rte_mbuf **rx_buffer_info; /* contex of rx packet */ 119 }; 120 struct rte_mbuf **rx_refill_buffer; 121 unsigned int ring_size; /* number of tx/rx_buffer_info's entries */ 122 123 struct ena_com_io_cq *ena_com_io_cq; 124 struct ena_com_io_sq *ena_com_io_sq; 125 126 struct ena_com_rx_buf_info ena_bufs[ENA_PKT_MAX_BUFS] 127 __rte_cache_aligned; 128 129 struct rte_mempool *mb_pool; 130 unsigned int port_id; 131 unsigned int id; 132 /* Max length PMD can push to device for LLQ */ 133 uint8_t tx_max_header_size; 134 int configured; 135 136 uint8_t *push_buf_intermediate_buf; 137 138 struct ena_adapter *adapter; 139 uint64_t offloads; 140 u16 sgl_size; 141 142 union { 143 struct ena_stats_rx rx_stats; 144 struct ena_stats_tx tx_stats; 145 }; 146 } __rte_cache_aligned; 147 148 enum ena_adapter_state { 149 ENA_ADAPTER_STATE_FREE = 0, 150 ENA_ADAPTER_STATE_INIT = 1, 151 ENA_ADAPTER_STATE_RUNNING = 2, 152 ENA_ADAPTER_STATE_STOPPED = 3, 153 ENA_ADAPTER_STATE_CONFIG = 4, 154 ENA_ADAPTER_STATE_CLOSED = 5, 155 }; 156 157 struct ena_driver_stats { 158 rte_atomic64_t ierrors; 159 rte_atomic64_t oerrors; 160 rte_atomic64_t rx_nombuf; 161 rte_atomic64_t rx_drops; 162 }; 163 164 struct ena_stats_dev { 165 u64 wd_expired; 166 u64 dev_start; 167 u64 dev_stop; 168 }; 169 170 struct ena_offloads { 171 bool tso4_supported; 172 bool tx_csum_supported; 173 bool rx_csum_supported; 174 }; 175 176 /* board specific private data structure */ 177 struct ena_adapter { 178 /* OS defined structs */ 179 struct rte_pci_device *pdev; 180 struct rte_eth_dev_data *rte_eth_dev_data; 181 struct rte_eth_dev *rte_dev; 182 183 struct ena_com_dev ena_dev __rte_cache_aligned; 184 185 /* TX */ 186 struct ena_ring tx_ring[ENA_MAX_NUM_QUEUES] __rte_cache_aligned; 187 int tx_ring_size; 188 u16 max_tx_sgl_size; 189 190 /* RX */ 191 struct ena_ring rx_ring[ENA_MAX_NUM_QUEUES] __rte_cache_aligned; 192 int rx_ring_size; 193 u16 max_rx_sgl_size; 194 195 u16 num_queues; 196 u16 max_mtu; 197 struct ena_offloads offloads; 198 199 int id_number; 200 char name[ENA_NAME_MAX_LEN]; 201 u8 mac_addr[RTE_ETHER_ADDR_LEN]; 202 203 void *regs; 204 void *dev_mem_base; 205 206 struct ena_driver_stats *drv_stats; 207 enum ena_adapter_state state; 208 209 uint64_t tx_supported_offloads; 210 uint64_t tx_selected_offloads; 211 uint64_t rx_supported_offloads; 212 uint64_t rx_selected_offloads; 213 214 bool link_status; 215 216 enum ena_regs_reset_reason_types reset_reason; 217 218 struct rte_timer timer_wd; 219 uint64_t timestamp_wd; 220 uint64_t keep_alive_timeout; 221 222 struct ena_stats_dev dev_stats; 223 224 bool trigger_reset; 225 226 bool wd_state; 227 }; 228 229 #endif /* _ENA_ETHDEV_H_ */ 230