1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates. 3 * All rights reserved. 4 */ 5 6 #ifndef ENA_COM 7 #define ENA_COM 8 9 #include "ena_plat.h" 10 11 #define ENA_MAX_NUM_IO_QUEUES 128U 12 /* We need to queues for each IO (on for Tx and one for Rx) */ 13 #define ENA_TOTAL_NUM_QUEUES (2 * (ENA_MAX_NUM_IO_QUEUES)) 14 15 #define ENA_MAX_HANDLERS 256 16 17 #define ENA_MAX_PHYS_ADDR_SIZE_BITS 48 18 19 /* Unit in usec */ 20 #define ENA_REG_READ_TIMEOUT 200000 21 22 #define ADMIN_SQ_SIZE(depth) ((depth) * sizeof(struct ena_admin_aq_entry)) 23 #define ADMIN_CQ_SIZE(depth) ((depth) * sizeof(struct ena_admin_acq_entry)) 24 #define ADMIN_AENQ_SIZE(depth) ((depth) * sizeof(struct ena_admin_aenq_entry)) 25 26 #define ENA_CDESC_RING_SIZE_ALIGNMENT (1 << 12) /* 4K */ 27 28 /*****************************************************************************/ 29 /*****************************************************************************/ 30 /* ENA adaptive interrupt moderation settings */ 31 32 #define ENA_INTR_INITIAL_TX_INTERVAL_USECS ENA_INTR_INITIAL_TX_INTERVAL_USECS_PLAT 33 #define ENA_INTR_INITIAL_RX_INTERVAL_USECS 0 34 #define ENA_DEFAULT_INTR_DELAY_RESOLUTION 1 35 36 #define ENA_HASH_KEY_SIZE 40 37 38 #define ENA_HW_HINTS_NO_TIMEOUT 0xFFFF 39 40 #define ENA_FEATURE_MAX_QUEUE_EXT_VER 1 41 42 struct ena_llq_configurations { 43 enum ena_admin_llq_header_location llq_header_location; 44 enum ena_admin_llq_ring_entry_size llq_ring_entry_size; 45 enum ena_admin_llq_stride_ctrl llq_stride_ctrl; 46 enum ena_admin_llq_num_descs_before_header llq_num_decs_before_header; 47 u16 llq_ring_entry_size_value; 48 }; 49 50 enum queue_direction { 51 ENA_COM_IO_QUEUE_DIRECTION_TX, 52 ENA_COM_IO_QUEUE_DIRECTION_RX 53 }; 54 55 struct ena_com_buf { 56 dma_addr_t paddr; /**< Buffer physical address */ 57 u16 len; /**< Buffer length in bytes */ 58 }; 59 60 struct ena_com_rx_buf_info { 61 u16 len; 62 u16 req_id; 63 }; 64 65 struct ena_com_io_desc_addr { 66 u8 __iomem *pbuf_dev_addr; /* LLQ address */ 67 u8 *virt_addr; 68 dma_addr_t phys_addr; 69 ena_mem_handle_t mem_handle; 70 }; 71 72 struct ena_com_tx_meta { 73 u16 mss; 74 u16 l3_hdr_len; 75 u16 l3_hdr_offset; 76 u16 l4_hdr_len; /* In words */ 77 }; 78 79 struct ena_com_llq_info { 80 u16 header_location_ctrl; 81 u16 desc_stride_ctrl; 82 u16 desc_list_entry_size_ctrl; 83 u16 desc_list_entry_size; 84 u16 descs_num_before_header; 85 u16 descs_per_entry; 86 u16 max_entries_in_tx_burst; 87 bool disable_meta_caching; 88 }; 89 90 struct ena_com_io_cq { 91 struct ena_com_io_desc_addr cdesc_addr; 92 void *bus; 93 94 /* Interrupt unmask register */ 95 u32 __iomem *unmask_reg; 96 97 /* The completion queue head doorbell register */ 98 u32 __iomem *cq_head_db_reg; 99 100 /* numa configuration register (for TPH) */ 101 u32 __iomem *numa_node_cfg_reg; 102 103 /* The value to write to the above register to unmask 104 * the interrupt of this queue 105 */ 106 u32 msix_vector; 107 108 enum queue_direction direction; 109 110 /* holds the number of cdesc of the current packet */ 111 u16 cur_rx_pkt_cdesc_count; 112 /* save the firt cdesc idx of the current packet */ 113 u16 cur_rx_pkt_cdesc_start_idx; 114 115 u16 q_depth; 116 /* Caller qid */ 117 u16 qid; 118 119 /* Device queue index */ 120 u16 idx; 121 u16 head; 122 u16 last_head_update; 123 u8 phase; 124 u8 cdesc_entry_size_in_bytes; 125 126 } ____cacheline_aligned; 127 128 struct ena_com_io_bounce_buffer_control { 129 u8 *base_buffer; 130 u16 next_to_use; 131 u16 buffer_size; 132 u16 buffers_num; /* Must be a power of 2 */ 133 }; 134 135 /* This struct is to keep tracking the current location of the next llq entry */ 136 struct ena_com_llq_pkt_ctrl { 137 u8 *curr_bounce_buf; 138 u16 idx; 139 u16 descs_left_in_line; 140 }; 141 142 struct ena_com_io_sq { 143 struct ena_com_io_desc_addr desc_addr; 144 void *bus; 145 146 u32 __iomem *db_addr; 147 u8 __iomem *header_addr; 148 149 enum queue_direction direction; 150 enum ena_admin_placement_policy_type mem_queue_type; 151 152 bool disable_meta_caching; 153 154 u32 msix_vector; 155 struct ena_com_tx_meta cached_tx_meta; 156 struct ena_com_llq_info llq_info; 157 struct ena_com_llq_pkt_ctrl llq_buf_ctrl; 158 struct ena_com_io_bounce_buffer_control bounce_buf_ctrl; 159 160 u16 q_depth; 161 u16 qid; 162 163 u16 idx; 164 u16 tail; 165 u16 next_to_comp; 166 u16 llq_last_copy_tail; 167 u32 tx_max_header_size; 168 u8 phase; 169 u8 desc_entry_size; 170 u8 dma_addr_bits; 171 u16 entries_in_tx_burst_left; 172 } ____cacheline_aligned; 173 174 struct ena_com_admin_cq { 175 struct ena_admin_acq_entry *entries; 176 ena_mem_handle_t mem_handle; 177 dma_addr_t dma_addr; 178 179 u16 head; 180 u8 phase; 181 }; 182 183 struct ena_com_admin_sq { 184 struct ena_admin_aq_entry *entries; 185 ena_mem_handle_t mem_handle; 186 dma_addr_t dma_addr; 187 188 u32 __iomem *db_addr; 189 190 u16 head; 191 u16 tail; 192 u8 phase; 193 194 }; 195 196 struct ena_com_stats_admin { 197 u64 aborted_cmd; 198 u64 submitted_cmd; 199 u64 completed_cmd; 200 u64 out_of_space; 201 u64 no_completion; 202 }; 203 204 struct ena_com_admin_queue { 205 void *q_dmadev; 206 void *bus; 207 struct ena_com_dev *ena_dev; 208 ena_spinlock_t q_lock; /* spinlock for the admin queue */ 209 210 struct ena_comp_ctx *comp_ctx; 211 u32 completion_timeout; 212 u16 q_depth; 213 struct ena_com_admin_cq cq; 214 struct ena_com_admin_sq sq; 215 216 /* Indicate if the admin queue should poll for completion */ 217 bool polling; 218 219 /* Define if fallback to polling mode should occur */ 220 bool auto_polling; 221 222 u16 curr_cmd_id; 223 224 /* Indicate that the ena was initialized and can 225 * process new admin commands 226 */ 227 bool running_state; 228 229 /* Count the number of outstanding admin commands */ 230 ena_atomic32_t outstanding_cmds; 231 232 struct ena_com_stats_admin stats; 233 }; 234 235 struct ena_aenq_handlers; 236 237 struct ena_com_aenq { 238 u16 head; 239 u8 phase; 240 struct ena_admin_aenq_entry *entries; 241 dma_addr_t dma_addr; 242 ena_mem_handle_t mem_handle; 243 u16 q_depth; 244 struct ena_aenq_handlers *aenq_handlers; 245 }; 246 247 struct ena_com_mmio_read { 248 struct ena_admin_ena_mmio_req_read_less_resp *read_resp; 249 dma_addr_t read_resp_dma_addr; 250 ena_mem_handle_t read_resp_mem_handle; 251 u32 reg_read_to; /* in us */ 252 u16 seq_num; 253 bool readless_supported; 254 /* spin lock to ensure a single outstanding read */ 255 ena_spinlock_t lock; 256 }; 257 258 struct ena_rss { 259 /* Indirect table */ 260 u16 *host_rss_ind_tbl; 261 struct ena_admin_rss_ind_table_entry *rss_ind_tbl; 262 dma_addr_t rss_ind_tbl_dma_addr; 263 ena_mem_handle_t rss_ind_tbl_mem_handle; 264 u16 tbl_log_size; 265 266 /* Hash key */ 267 enum ena_admin_hash_functions hash_func; 268 struct ena_admin_feature_rss_flow_hash_control *hash_key; 269 dma_addr_t hash_key_dma_addr; 270 ena_mem_handle_t hash_key_mem_handle; 271 u32 hash_init_val; 272 273 /* Flow Control */ 274 struct ena_admin_feature_rss_hash_control *hash_ctrl; 275 dma_addr_t hash_ctrl_dma_addr; 276 ena_mem_handle_t hash_ctrl_mem_handle; 277 278 }; 279 280 struct ena_host_attribute { 281 /* Debug area */ 282 u8 *debug_area_virt_addr; 283 dma_addr_t debug_area_dma_addr; 284 ena_mem_handle_t debug_area_dma_handle; 285 u32 debug_area_size; 286 287 /* Host information */ 288 struct ena_admin_host_info *host_info; 289 dma_addr_t host_info_dma_addr; 290 ena_mem_handle_t host_info_dma_handle; 291 }; 292 293 /* Each ena_dev is a PCI function. */ 294 struct ena_com_dev { 295 struct ena_com_admin_queue admin_queue; 296 struct ena_com_aenq aenq; 297 struct ena_com_io_cq io_cq_queues[ENA_TOTAL_NUM_QUEUES]; 298 struct ena_com_io_sq io_sq_queues[ENA_TOTAL_NUM_QUEUES]; 299 u8 __iomem *reg_bar; 300 void __iomem *mem_bar; 301 void *dmadev; 302 void *bus; 303 304 enum ena_admin_placement_policy_type tx_mem_queue_type; 305 u32 tx_max_header_size; 306 u16 stats_func; /* Selected function for extended statistic dump */ 307 u16 stats_queue; /* Selected queue for extended statistic dump */ 308 309 struct ena_com_mmio_read mmio_read; 310 311 struct ena_rss rss; 312 u32 supported_features; 313 u32 dma_addr_bits; 314 315 struct ena_host_attribute host_attr; 316 bool adaptive_coalescing; 317 u16 intr_delay_resolution; 318 319 /* interrupt moderation intervals are in usec divided by 320 * intr_delay_resolution, which is supplied by the device. 321 */ 322 u32 intr_moder_tx_interval; 323 u32 intr_moder_rx_interval; 324 325 struct ena_intr_moder_entry *intr_moder_tbl; 326 327 struct ena_com_llq_info llq_info; 328 329 u32 ena_min_poll_delay_us; 330 }; 331 332 struct ena_com_dev_get_features_ctx { 333 struct ena_admin_queue_feature_desc max_queues; 334 struct ena_admin_queue_ext_feature_desc max_queue_ext; 335 struct ena_admin_device_attr_feature_desc dev_attr; 336 struct ena_admin_feature_aenq_desc aenq; 337 struct ena_admin_feature_offload_desc offload; 338 struct ena_admin_ena_hw_hints hw_hints; 339 struct ena_admin_feature_llq_desc llq; 340 struct ena_admin_feature_rss_ind_table ind_table; 341 }; 342 343 struct ena_com_create_io_ctx { 344 enum ena_admin_placement_policy_type mem_queue_type; 345 enum queue_direction direction; 346 int numa_node; 347 u32 msix_vector; 348 u16 queue_size; 349 u16 qid; 350 }; 351 352 typedef void (*ena_aenq_handler)(void *data, 353 struct ena_admin_aenq_entry *aenq_e); 354 355 /* Holds aenq handlers. Indexed by AENQ event group */ 356 struct ena_aenq_handlers { 357 ena_aenq_handler handlers[ENA_MAX_HANDLERS]; 358 ena_aenq_handler unimplemented_handler; 359 }; 360 361 /*****************************************************************************/ 362 /*****************************************************************************/ 363 #if defined(__cplusplus) 364 extern "C" { 365 #endif 366 367 /* ena_com_mmio_reg_read_request_init - Init the mmio reg read mechanism 368 * @ena_dev: ENA communication layer struct 369 * 370 * Initialize the register read mechanism. 371 * 372 * @note: This method must be the first stage in the initialization sequence. 373 * 374 * @return - 0 on success, negative value on failure. 375 */ 376 int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev); 377 378 /* ena_com_set_mmio_read_mode - Enable/disable the indirect mmio reg read mechanism 379 * @ena_dev: ENA communication layer struct 380 * @readless_supported: readless mode (enable/disable) 381 */ 382 void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev, 383 bool readless_supported); 384 385 /* ena_com_mmio_reg_read_request_write_dev_addr - Write the mmio reg read return 386 * value physical address. 387 * @ena_dev: ENA communication layer struct 388 */ 389 void ena_com_mmio_reg_read_request_write_dev_addr(struct ena_com_dev *ena_dev); 390 391 /* ena_com_mmio_reg_read_request_destroy - Destroy the mmio reg read mechanism 392 * @ena_dev: ENA communication layer struct 393 */ 394 void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev); 395 396 /* ena_com_admin_init - Init the admin and the async queues 397 * @ena_dev: ENA communication layer struct 398 * @aenq_handlers: Those handlers to be called upon event. 399 * 400 * Initialize the admin submission and completion queues. 401 * Initialize the asynchronous events notification queues. 402 * 403 * @return - 0 on success, negative value on failure. 404 */ 405 int ena_com_admin_init(struct ena_com_dev *ena_dev, 406 struct ena_aenq_handlers *aenq_handlers); 407 408 /* ena_com_admin_destroy - Destroy the admin and the async events queues. 409 * @ena_dev: ENA communication layer struct 410 * 411 * @note: Before calling this method, the caller must validate that the device 412 * won't send any additional admin completions/aenq. 413 * To achieve that, a FLR is recommended. 414 */ 415 void ena_com_admin_destroy(struct ena_com_dev *ena_dev); 416 417 /* ena_com_dev_reset - Perform device FLR to the device. 418 * @ena_dev: ENA communication layer struct 419 * @reset_reason: Specify what is the trigger for the reset in case of an error. 420 * 421 * @return - 0 on success, negative value on failure. 422 */ 423 int ena_com_dev_reset(struct ena_com_dev *ena_dev, 424 enum ena_regs_reset_reason_types reset_reason); 425 426 /* ena_com_create_io_queue - Create io queue. 427 * @ena_dev: ENA communication layer struct 428 * @ctx - create context structure 429 * 430 * Create the submission and the completion queues. 431 * 432 * @return - 0 on success, negative value on failure. 433 */ 434 int ena_com_create_io_queue(struct ena_com_dev *ena_dev, 435 struct ena_com_create_io_ctx *ctx); 436 437 /* ena_com_destroy_io_queue - Destroy IO queue with the queue id - qid. 438 * @ena_dev: ENA communication layer struct 439 * @qid - the caller virtual queue id. 440 */ 441 void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid); 442 443 /* ena_com_get_io_handlers - Return the io queue handlers 444 * @ena_dev: ENA communication layer struct 445 * @qid - the caller virtual queue id. 446 * @io_sq - IO submission queue handler 447 * @io_cq - IO completion queue handler. 448 * 449 * @return - 0 on success, negative value on failure. 450 */ 451 int ena_com_get_io_handlers(struct ena_com_dev *ena_dev, u16 qid, 452 struct ena_com_io_sq **io_sq, 453 struct ena_com_io_cq **io_cq); 454 455 /* ena_com_admin_aenq_enable - ENAble asynchronous event notifications 456 * @ena_dev: ENA communication layer struct 457 * 458 * After this method, aenq event can be received via AENQ. 459 */ 460 void ena_com_admin_aenq_enable(struct ena_com_dev *ena_dev); 461 462 /* ena_com_set_admin_running_state - Set the state of the admin queue 463 * @ena_dev: ENA communication layer struct 464 * 465 * Change the state of the admin queue (enable/disable) 466 */ 467 void ena_com_set_admin_running_state(struct ena_com_dev *ena_dev, bool state); 468 469 /* ena_com_get_admin_running_state - Get the admin queue state 470 * @ena_dev: ENA communication layer struct 471 * 472 * Retrieve the state of the admin queue (enable/disable) 473 * 474 * @return - current polling mode (enable/disable) 475 */ 476 bool ena_com_get_admin_running_state(struct ena_com_dev *ena_dev); 477 478 /* ena_com_set_admin_polling_mode - Set the admin completion queue polling mode 479 * @ena_dev: ENA communication layer struct 480 * @polling: ENAble/Disable polling mode 481 * 482 * Set the admin completion mode. 483 */ 484 void ena_com_set_admin_polling_mode(struct ena_com_dev *ena_dev, bool polling); 485 486 /* ena_com_get_admin_polling_mode - Get the admin completion queue polling mode 487 * @ena_dev: ENA communication layer struct 488 * 489 * Get the admin completion mode. 490 * If polling mode is on, ena_com_execute_admin_command will perform a 491 * polling on the admin completion queue for the commands completion, 492 * otherwise it will wait on wait event. 493 * 494 * @return state 495 */ 496 bool ena_com_get_admin_polling_mode(struct ena_com_dev *ena_dev); 497 498 /* ena_com_set_admin_auto_polling_mode - Enable autoswitch to polling mode 499 * @ena_dev: ENA communication layer struct 500 * @polling: Enable/Disable polling mode 501 * 502 * Set the autopolling mode. 503 * If autopolling is on: 504 * In case of missing interrupt when data is available switch to polling. 505 */ 506 void ena_com_set_admin_auto_polling_mode(struct ena_com_dev *ena_dev, 507 bool polling); 508 509 /* ena_com_admin_q_comp_intr_handler - admin queue interrupt handler 510 * @ena_dev: ENA communication layer struct 511 * 512 * This method goes over the admin completion queue and wakes up all the pending 513 * threads that wait on the commands wait event. 514 * 515 * @note: Should be called after MSI-X interrupt. 516 */ 517 void ena_com_admin_q_comp_intr_handler(struct ena_com_dev *ena_dev); 518 519 /* ena_com_aenq_intr_handler - AENQ interrupt handler 520 * @ena_dev: ENA communication layer struct 521 * 522 * This method goes over the async event notification queue and calls the proper 523 * aenq handler. 524 */ 525 void ena_com_aenq_intr_handler(struct ena_com_dev *dev, void *data); 526 527 /* ena_com_abort_admin_commands - Abort all the outstanding admin commands. 528 * @ena_dev: ENA communication layer struct 529 * 530 * This method aborts all the outstanding admin commands. 531 * The caller should then call ena_com_wait_for_abort_completion to make sure 532 * all the commands were completed. 533 */ 534 void ena_com_abort_admin_commands(struct ena_com_dev *ena_dev); 535 536 /* ena_com_wait_for_abort_completion - Wait for admin commands abort. 537 * @ena_dev: ENA communication layer struct 538 * 539 * This method waits until all the outstanding admin commands are completed. 540 */ 541 void ena_com_wait_for_abort_completion(struct ena_com_dev *ena_dev); 542 543 /* ena_com_validate_version - Validate the device parameters 544 * @ena_dev: ENA communication layer struct 545 * 546 * This method verifies the device parameters are the same as the saved 547 * parameters in ena_dev. 548 * This method is useful after device reset, to validate the device mac address 549 * and the device offloads are the same as before the reset. 550 * 551 * @return - 0 on success negative value otherwise. 552 */ 553 int ena_com_validate_version(struct ena_com_dev *ena_dev); 554 555 /* ena_com_get_link_params - Retrieve physical link parameters. 556 * @ena_dev: ENA communication layer struct 557 * @resp: Link parameters 558 * 559 * Retrieve the physical link parameters, 560 * like speed, auto-negotiation and full duplex support. 561 * 562 * @return - 0 on Success negative value otherwise. 563 */ 564 int ena_com_get_link_params(struct ena_com_dev *ena_dev, 565 struct ena_admin_get_feat_resp *resp); 566 567 /* ena_com_get_dma_width - Retrieve physical dma address width the device 568 * supports. 569 * @ena_dev: ENA communication layer struct 570 * 571 * Retrieve the maximum physical address bits the device can handle. 572 * 573 * @return: > 0 on Success and negative value otherwise. 574 */ 575 int ena_com_get_dma_width(struct ena_com_dev *ena_dev); 576 577 /* ena_com_set_aenq_config - Set aenq groups configurations 578 * @ena_dev: ENA communication layer struct 579 * @groups flag: bit fields flags of enum ena_admin_aenq_group. 580 * 581 * Configure which aenq event group the driver would like to receive. 582 * 583 * @return: 0 on Success and negative value otherwise. 584 */ 585 int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag); 586 587 /* ena_com_get_dev_attr_feat - Get device features 588 * @ena_dev: ENA communication layer struct 589 * @get_feat_ctx: returned context that contain the get features. 590 * 591 * @return: 0 on Success and negative value otherwise. 592 */ 593 int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev, 594 struct ena_com_dev_get_features_ctx *get_feat_ctx); 595 596 /* ena_com_get_dev_basic_stats - Get device basic statistics 597 * @ena_dev: ENA communication layer struct 598 * @stats: stats return value 599 * 600 * @return: 0 on Success and negative value otherwise. 601 */ 602 int ena_com_get_dev_basic_stats(struct ena_com_dev *ena_dev, 603 struct ena_admin_basic_stats *stats); 604 605 /* ena_com_get_eni_stats - Get extended network interface statistics 606 * @ena_dev: ENA communication layer struct 607 * @stats: stats return value 608 * 609 * @return: 0 on Success and negative value otherwise. 610 */ 611 int ena_com_get_eni_stats(struct ena_com_dev *ena_dev, 612 struct ena_admin_eni_stats *stats); 613 614 /* ena_com_set_dev_mtu - Configure the device mtu. 615 * @ena_dev: ENA communication layer struct 616 * @mtu: mtu value 617 * 618 * @return: 0 on Success and negative value otherwise. 619 */ 620 int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu); 621 622 /* ena_com_get_offload_settings - Retrieve the device offloads capabilities 623 * @ena_dev: ENA communication layer struct 624 * @offlad: offload return value 625 * 626 * @return: 0 on Success and negative value otherwise. 627 */ 628 int ena_com_get_offload_settings(struct ena_com_dev *ena_dev, 629 struct ena_admin_feature_offload_desc *offload); 630 631 /* ena_com_rss_init - Init RSS 632 * @ena_dev: ENA communication layer struct 633 * @log_size: indirection log size 634 * 635 * Allocate RSS/RFS resources. 636 * The caller then can configure rss using ena_com_set_hash_function, 637 * ena_com_set_hash_ctrl and ena_com_indirect_table_set. 638 * 639 * @return: 0 on Success and negative value otherwise. 640 */ 641 int ena_com_rss_init(struct ena_com_dev *ena_dev, u16 log_size); 642 643 /* ena_com_rss_destroy - Destroy rss 644 * @ena_dev: ENA communication layer struct 645 * 646 * Free all the RSS/RFS resources. 647 */ 648 void ena_com_rss_destroy(struct ena_com_dev *ena_dev); 649 650 /* ena_com_get_current_hash_function - Get RSS hash function 651 * @ena_dev: ENA communication layer struct 652 * 653 * Return the current hash function. 654 * @return: 0 or one of the ena_admin_hash_functions values. 655 */ 656 int ena_com_get_current_hash_function(struct ena_com_dev *ena_dev); 657 658 /* ena_com_fill_hash_function - Fill RSS hash function 659 * @ena_dev: ENA communication layer struct 660 * @func: The hash function (Toeplitz or crc) 661 * @key: Hash key (for toeplitz hash) 662 * @key_len: key length (max length 10 DW) 663 * @init_val: initial value for the hash function 664 * 665 * Fill the ena_dev resources with the desire hash function, hash key, key_len 666 * and key initial value (if needed by the hash function). 667 * To flush the key into the device the caller should call 668 * ena_com_set_hash_function. 669 * 670 * @return: 0 on Success and negative value otherwise. 671 */ 672 int ena_com_fill_hash_function(struct ena_com_dev *ena_dev, 673 enum ena_admin_hash_functions func, 674 const u8 *key, u16 key_len, u32 init_val); 675 676 /* ena_com_set_hash_function - Flush the hash function and it dependencies to 677 * the device. 678 * @ena_dev: ENA communication layer struct 679 * 680 * Flush the hash function and it dependencies (key, key length and 681 * initial value) if needed. 682 * 683 * @note: Prior to this method the caller should call ena_com_fill_hash_function 684 * 685 * @return: 0 on Success and negative value otherwise. 686 */ 687 int ena_com_set_hash_function(struct ena_com_dev *ena_dev); 688 689 /* ena_com_get_hash_function - Retrieve the hash function from the device. 690 * @ena_dev: ENA communication layer struct 691 * @func: hash function 692 * 693 * Retrieve the hash function from the device. 694 * 695 * @note: If the caller called ena_com_fill_hash_function but didn't flush 696 * it to the device, the new configuration will be lost. 697 * 698 * @return: 0 on Success and negative value otherwise. 699 */ 700 int ena_com_get_hash_function(struct ena_com_dev *ena_dev, 701 enum ena_admin_hash_functions *func); 702 703 /* ena_com_get_hash_key - Retrieve the hash key 704 * @ena_dev: ENA communication layer struct 705 * @key: hash key 706 * 707 * Retrieve the hash key. 708 * 709 * @note: If the caller called ena_com_fill_hash_key but didn't flush 710 * it to the device, the new configuration will be lost. 711 * 712 * @return: 0 on Success and negative value otherwise. 713 */ 714 int ena_com_get_hash_key(struct ena_com_dev *ena_dev, u8 *key); 715 /* ena_com_fill_hash_ctrl - Fill RSS hash control 716 * @ena_dev: ENA communication layer struct. 717 * @proto: The protocol to configure. 718 * @hash_fields: bit mask of ena_admin_flow_hash_fields 719 * 720 * Fill the ena_dev resources with the desire hash control (the ethernet 721 * fields that take part of the hash) for a specific protocol. 722 * To flush the hash control to the device, the caller should call 723 * ena_com_set_hash_ctrl. 724 * 725 * @return: 0 on Success and negative value otherwise. 726 */ 727 int ena_com_fill_hash_ctrl(struct ena_com_dev *ena_dev, 728 enum ena_admin_flow_hash_proto proto, 729 u16 hash_fields); 730 731 /* ena_com_set_hash_ctrl - Flush the hash control resources to the device. 732 * @ena_dev: ENA communication layer struct 733 * 734 * Flush the hash control (the ethernet fields that take part of the hash) 735 * 736 * @note: Prior to this method the caller should call ena_com_fill_hash_ctrl. 737 * 738 * @return: 0 on Success and negative value otherwise. 739 */ 740 int ena_com_set_hash_ctrl(struct ena_com_dev *ena_dev); 741 742 /* ena_com_get_hash_ctrl - Retrieve the hash control from the device. 743 * @ena_dev: ENA communication layer struct 744 * @proto: The protocol to retrieve. 745 * @fields: bit mask of ena_admin_flow_hash_fields. 746 * 747 * Retrieve the hash control from the device. 748 * 749 * @note: If the caller called ena_com_fill_hash_ctrl but didn't flush 750 * it to the device, the new configuration will be lost. 751 * 752 * @return: 0 on Success and negative value otherwise. 753 */ 754 int ena_com_get_hash_ctrl(struct ena_com_dev *ena_dev, 755 enum ena_admin_flow_hash_proto proto, 756 u16 *fields); 757 758 /* ena_com_set_default_hash_ctrl - Set the hash control to a default 759 * configuration. 760 * @ena_dev: ENA communication layer struct 761 * 762 * Fill the ena_dev resources with the default hash control configuration. 763 * To flush the hash control to the device, the caller should call 764 * ena_com_set_hash_ctrl. 765 * 766 * @return: 0 on Success and negative value otherwise. 767 */ 768 int ena_com_set_default_hash_ctrl(struct ena_com_dev *ena_dev); 769 770 /* ena_com_indirect_table_fill_entry - Fill a single entry in the RSS 771 * indirection table 772 * @ena_dev: ENA communication layer struct. 773 * @entry_idx - indirection table entry. 774 * @entry_value - redirection value 775 * 776 * Fill a single entry of the RSS indirection table in the ena_dev resources. 777 * To flush the indirection table to the device, the called should call 778 * ena_com_indirect_table_set. 779 * 780 * @return: 0 on Success and negative value otherwise. 781 */ 782 int ena_com_indirect_table_fill_entry(struct ena_com_dev *ena_dev, 783 u16 entry_idx, u16 entry_value); 784 785 /* ena_com_indirect_table_set - Flush the indirection table to the device. 786 * @ena_dev: ENA communication layer struct 787 * 788 * Flush the indirection hash control to the device. 789 * Prior to this method the caller should call ena_com_indirect_table_fill_entry 790 * 791 * @return: 0 on Success and negative value otherwise. 792 */ 793 int ena_com_indirect_table_set(struct ena_com_dev *ena_dev); 794 795 /* ena_com_indirect_table_get - Retrieve the indirection table from the device. 796 * @ena_dev: ENA communication layer struct 797 * @ind_tbl: indirection table 798 * 799 * Retrieve the RSS indirection table from the device. 800 * 801 * @note: If the caller called ena_com_indirect_table_fill_entry but didn't flush 802 * it to the device, the new configuration will be lost. 803 * 804 * @return: 0 on Success and negative value otherwise. 805 */ 806 int ena_com_indirect_table_get(struct ena_com_dev *ena_dev, u32 *ind_tbl); 807 808 /* ena_com_allocate_host_info - Allocate host info resources. 809 * @ena_dev: ENA communication layer struct 810 * 811 * @return: 0 on Success and negative value otherwise. 812 */ 813 int ena_com_allocate_host_info(struct ena_com_dev *ena_dev); 814 815 /* ena_com_allocate_debug_area - Allocate debug area. 816 * @ena_dev: ENA communication layer struct 817 * @debug_area_size - debug area size. 818 * 819 * @return: 0 on Success and negative value otherwise. 820 */ 821 int ena_com_allocate_debug_area(struct ena_com_dev *ena_dev, 822 u32 debug_area_size); 823 824 /* ena_com_delete_debug_area - Free the debug area resources. 825 * @ena_dev: ENA communication layer struct 826 * 827 * Free the allocated debug area. 828 */ 829 void ena_com_delete_debug_area(struct ena_com_dev *ena_dev); 830 831 /* ena_com_delete_host_info - Free the host info resources. 832 * @ena_dev: ENA communication layer struct 833 * 834 * Free the allocated host info. 835 */ 836 void ena_com_delete_host_info(struct ena_com_dev *ena_dev); 837 838 /* ena_com_set_host_attributes - Update the device with the host 839 * attributes (debug area and host info) base address. 840 * @ena_dev: ENA communication layer struct 841 * 842 * @return: 0 on Success and negative value otherwise. 843 */ 844 int ena_com_set_host_attributes(struct ena_com_dev *ena_dev); 845 846 /* ena_com_create_io_cq - Create io completion queue. 847 * @ena_dev: ENA communication layer struct 848 * @io_cq - io completion queue handler 849 850 * Create IO completion queue. 851 * 852 * @return - 0 on success, negative value on failure. 853 */ 854 int ena_com_create_io_cq(struct ena_com_dev *ena_dev, 855 struct ena_com_io_cq *io_cq); 856 857 /* ena_com_destroy_io_cq - Destroy io completion queue. 858 * @ena_dev: ENA communication layer struct 859 * @io_cq - io completion queue handler 860 861 * Destroy IO completion queue. 862 * 863 * @return - 0 on success, negative value on failure. 864 */ 865 int ena_com_destroy_io_cq(struct ena_com_dev *ena_dev, 866 struct ena_com_io_cq *io_cq); 867 868 /* ena_com_execute_admin_command - Execute admin command 869 * @admin_queue: admin queue. 870 * @cmd: the admin command to execute. 871 * @cmd_size: the command size. 872 * @cmd_completion: command completion return value. 873 * @cmd_comp_size: command completion size. 874 875 * Submit an admin command and then wait until the device returns a 876 * completion. 877 * The completion will be copied into cmd_comp. 878 * 879 * @return - 0 on success, negative value on failure. 880 */ 881 int ena_com_execute_admin_command(struct ena_com_admin_queue *admin_queue, 882 struct ena_admin_aq_entry *cmd, 883 size_t cmd_size, 884 struct ena_admin_acq_entry *cmd_comp, 885 size_t cmd_comp_size); 886 887 /* ena_com_init_interrupt_moderation - Init interrupt moderation 888 * @ena_dev: ENA communication layer struct 889 * 890 * @return - 0 on success, negative value on failure. 891 */ 892 int ena_com_init_interrupt_moderation(struct ena_com_dev *ena_dev); 893 894 /* ena_com_interrupt_moderation_supported - Return if interrupt moderation 895 * capability is supported by the device. 896 * 897 * @return - supported or not. 898 */ 899 bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev); 900 901 /* ena_com_update_nonadaptive_moderation_interval_tx - Update the 902 * non-adaptive interval in Tx direction. 903 * @ena_dev: ENA communication layer struct 904 * @tx_coalesce_usecs: Interval in usec. 905 * 906 * @return - 0 on success, negative value on failure. 907 */ 908 int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev, 909 u32 tx_coalesce_usecs); 910 911 /* ena_com_update_nonadaptive_moderation_interval_rx - Update the 912 * non-adaptive interval in Rx direction. 913 * @ena_dev: ENA communication layer struct 914 * @rx_coalesce_usecs: Interval in usec. 915 * 916 * @return - 0 on success, negative value on failure. 917 */ 918 int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev, 919 u32 rx_coalesce_usecs); 920 921 /* ena_com_get_nonadaptive_moderation_interval_tx - Retrieve the 922 * non-adaptive interval in Tx direction. 923 * @ena_dev: ENA communication layer struct 924 * 925 * @return - interval in usec 926 */ 927 unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev); 928 929 /* ena_com_get_nonadaptive_moderation_interval_rx - Retrieve the 930 * non-adaptive interval in Rx direction. 931 * @ena_dev: ENA communication layer struct 932 * 933 * @return - interval in usec 934 */ 935 unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev); 936 937 /* ena_com_config_dev_mode - Configure the placement policy of the device. 938 * @ena_dev: ENA communication layer struct 939 * @llq_features: LLQ feature descriptor, retrieve via 940 * ena_com_get_dev_attr_feat. 941 * @ena_llq_config: The default driver LLQ parameters configurations 942 */ 943 int ena_com_config_dev_mode(struct ena_com_dev *ena_dev, 944 struct ena_admin_feature_llq_desc *llq_features, 945 struct ena_llq_configurations *llq_default_config); 946 947 static inline bool ena_com_get_adaptive_moderation_enabled(struct ena_com_dev *ena_dev) 948 { 949 return ena_dev->adaptive_coalescing; 950 } 951 952 static inline void ena_com_enable_adaptive_moderation(struct ena_com_dev *ena_dev) 953 { 954 ena_dev->adaptive_coalescing = true; 955 } 956 957 static inline void ena_com_disable_adaptive_moderation(struct ena_com_dev *ena_dev) 958 { 959 ena_dev->adaptive_coalescing = false; 960 } 961 962 /* ena_com_update_intr_reg - Prepare interrupt register 963 * @intr_reg: interrupt register to update. 964 * @rx_delay_interval: Rx interval in usecs 965 * @tx_delay_interval: Tx interval in usecs 966 * @unmask: unmask enable/disable 967 * 968 * Prepare interrupt update register with the supplied parameters. 969 */ 970 static inline void ena_com_update_intr_reg(struct ena_eth_io_intr_reg *intr_reg, 971 u32 rx_delay_interval, 972 u32 tx_delay_interval, 973 bool unmask) 974 { 975 intr_reg->intr_control = 0; 976 intr_reg->intr_control |= rx_delay_interval & 977 ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK; 978 979 intr_reg->intr_control |= 980 (tx_delay_interval << ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT) 981 & ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK; 982 983 if (unmask) 984 intr_reg->intr_control |= ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK; 985 } 986 987 static inline u8 *ena_com_get_next_bounce_buffer(struct ena_com_io_bounce_buffer_control *bounce_buf_ctrl) 988 { 989 u16 size, buffers_num; 990 u8 *buf; 991 992 size = bounce_buf_ctrl->buffer_size; 993 buffers_num = bounce_buf_ctrl->buffers_num; 994 995 buf = bounce_buf_ctrl->base_buffer + 996 (bounce_buf_ctrl->next_to_use++ & (buffers_num - 1)) * size; 997 998 prefetchw(bounce_buf_ctrl->base_buffer + 999 (bounce_buf_ctrl->next_to_use & (buffers_num - 1)) * size); 1000 1001 return buf; 1002 } 1003 1004 #if defined(__cplusplus) 1005 } 1006 #endif /* __cplusplus */ 1007 #endif /* !(ENA_COM) */ 1008