1 /*- 2 * BSD LICENSE 3 * 4 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved. 5 * Copyright (c) 2016 NXP. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of Freescale Semiconductor, Inc nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <time.h> 35 #include <net/if.h> 36 37 #include <rte_mbuf.h> 38 #include <rte_ethdev.h> 39 #include <rte_malloc.h> 40 #include <rte_memcpy.h> 41 #include <rte_string_fns.h> 42 #include <rte_dev.h> 43 #include <rte_ethdev.h> 44 45 #include <fslmc_logs.h> 46 #include <fslmc_vfio.h> 47 #include <dpaa2_hw_pvt.h> 48 #include <dpaa2_hw_dpio.h> 49 #include <dpaa2_hw_mempool.h> 50 51 #include "dpaa2_ethdev.h" 52 #include "base/dpaa2_hw_dpni_annot.h" 53 54 static inline uint32_t __attribute__((hot)) 55 dpaa2_dev_rx_parse(uint64_t hw_annot_addr) 56 { 57 uint32_t pkt_type = RTE_PTYPE_UNKNOWN; 58 struct dpaa2_annot_hdr *annotation = 59 (struct dpaa2_annot_hdr *)hw_annot_addr; 60 61 PMD_RX_LOG(DEBUG, "annotation = 0x%lx ", annotation->word4); 62 63 if (BIT_ISSET_AT_POS(annotation->word3, L2_ARP_PRESENT)) { 64 pkt_type = RTE_PTYPE_L2_ETHER_ARP; 65 goto parse_done; 66 } else if (BIT_ISSET_AT_POS(annotation->word3, L2_ETH_MAC_PRESENT)) { 67 pkt_type = RTE_PTYPE_L2_ETHER; 68 } else { 69 goto parse_done; 70 } 71 72 if (BIT_ISSET_AT_POS(annotation->word4, L3_IPV4_1_PRESENT | 73 L3_IPV4_N_PRESENT)) { 74 pkt_type |= RTE_PTYPE_L3_IPV4; 75 if (BIT_ISSET_AT_POS(annotation->word4, L3_IP_1_OPT_PRESENT | 76 L3_IP_N_OPT_PRESENT)) 77 pkt_type |= RTE_PTYPE_L3_IPV4_EXT; 78 79 } else if (BIT_ISSET_AT_POS(annotation->word4, L3_IPV6_1_PRESENT | 80 L3_IPV6_N_PRESENT)) { 81 pkt_type |= RTE_PTYPE_L3_IPV6; 82 if (BIT_ISSET_AT_POS(annotation->word4, L3_IP_1_OPT_PRESENT | 83 L3_IP_N_OPT_PRESENT)) 84 pkt_type |= RTE_PTYPE_L3_IPV6_EXT; 85 } else { 86 goto parse_done; 87 } 88 89 if (BIT_ISSET_AT_POS(annotation->word4, L3_IP_1_FIRST_FRAGMENT | 90 L3_IP_1_MORE_FRAGMENT | 91 L3_IP_N_FIRST_FRAGMENT | 92 L3_IP_N_MORE_FRAGMENT)) { 93 pkt_type |= RTE_PTYPE_L4_FRAG; 94 goto parse_done; 95 } else { 96 pkt_type |= RTE_PTYPE_L4_NONFRAG; 97 } 98 99 if (BIT_ISSET_AT_POS(annotation->word4, L3_PROTO_UDP_PRESENT)) 100 pkt_type |= RTE_PTYPE_L4_UDP; 101 102 else if (BIT_ISSET_AT_POS(annotation->word4, L3_PROTO_TCP_PRESENT)) 103 pkt_type |= RTE_PTYPE_L4_TCP; 104 105 else if (BIT_ISSET_AT_POS(annotation->word4, L3_PROTO_SCTP_PRESENT)) 106 pkt_type |= RTE_PTYPE_L4_SCTP; 107 108 else if (BIT_ISSET_AT_POS(annotation->word4, L3_PROTO_ICMP_PRESENT)) 109 pkt_type |= RTE_PTYPE_L4_ICMP; 110 111 else if (BIT_ISSET_AT_POS(annotation->word4, L3_IP_UNKNOWN_PROTOCOL)) 112 pkt_type |= RTE_PTYPE_UNKNOWN; 113 114 parse_done: 115 return pkt_type; 116 } 117 118 static inline void __attribute__((hot)) 119 dpaa2_dev_rx_offload(uint64_t hw_annot_addr, struct rte_mbuf *mbuf) 120 { 121 struct dpaa2_annot_hdr *annotation = 122 (struct dpaa2_annot_hdr *)hw_annot_addr; 123 124 if (BIT_ISSET_AT_POS(annotation->word3, 125 L2_VLAN_1_PRESENT | L2_VLAN_N_PRESENT)) 126 mbuf->ol_flags |= PKT_RX_VLAN_PKT; 127 128 if (BIT_ISSET_AT_POS(annotation->word8, DPAA2_ETH_FAS_L3CE)) 129 mbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD; 130 131 if (BIT_ISSET_AT_POS(annotation->word8, DPAA2_ETH_FAS_L4CE)) 132 mbuf->ol_flags |= PKT_RX_L4_CKSUM_BAD; 133 } 134 135 static inline struct rte_mbuf *__attribute__((hot)) 136 eth_fd_to_mbuf(const struct qbman_fd *fd) 137 { 138 struct rte_mbuf *mbuf = DPAA2_INLINE_MBUF_FROM_BUF( 139 DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd)), 140 rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size); 141 142 /* need to repopulated some of the fields, 143 * as they may have changed in last transmission 144 */ 145 mbuf->nb_segs = 1; 146 mbuf->ol_flags = 0; 147 mbuf->data_off = DPAA2_GET_FD_OFFSET(fd); 148 mbuf->data_len = DPAA2_GET_FD_LEN(fd); 149 mbuf->pkt_len = mbuf->data_len; 150 151 /* Parse the packet */ 152 /* parse results are after the private - sw annotation area */ 153 mbuf->packet_type = dpaa2_dev_rx_parse( 154 (uint64_t)DPAA2_IOVA_TO_VADDR(DPAA2_GET_FD_ADDR(fd)) 155 + DPAA2_FD_PTA_SIZE); 156 157 dpaa2_dev_rx_offload((uint64_t)DPAA2_IOVA_TO_VADDR( 158 DPAA2_GET_FD_ADDR(fd)) + 159 DPAA2_FD_PTA_SIZE, mbuf); 160 161 mbuf->next = NULL; 162 rte_mbuf_refcnt_set(mbuf, 1); 163 164 PMD_RX_LOG(DEBUG, "to mbuf - mbuf =%p, mbuf->buf_addr =%p, off = %d," 165 "fd_off=%d fd =%lx, meta = %d bpid =%d, len=%d\n", 166 mbuf, mbuf->buf_addr, mbuf->data_off, 167 DPAA2_GET_FD_OFFSET(fd), DPAA2_GET_FD_ADDR(fd), 168 rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size, 169 DPAA2_GET_FD_BPID(fd), DPAA2_GET_FD_LEN(fd)); 170 171 return mbuf; 172 } 173 174 static void __attribute__ ((noinline)) __attribute__((hot)) 175 eth_mbuf_to_fd(struct rte_mbuf *mbuf, 176 struct qbman_fd *fd, uint16_t bpid) 177 { 178 /*Resetting the buffer pool id and offset field*/ 179 fd->simple.bpid_offset = 0; 180 181 DPAA2_SET_FD_ADDR(fd, DPAA2_MBUF_VADDR_TO_IOVA(mbuf)); 182 DPAA2_SET_FD_LEN(fd, mbuf->data_len); 183 DPAA2_SET_FD_BPID(fd, bpid); 184 DPAA2_SET_FD_OFFSET(fd, mbuf->data_off); 185 DPAA2_SET_FD_ASAL(fd, DPAA2_ASAL_VAL); 186 187 PMD_TX_LOG(DEBUG, "mbuf =%p, mbuf->buf_addr =%p, off = %d," 188 "fd_off=%d fd =%lx, meta = %d bpid =%d, len=%d\n", 189 mbuf, mbuf->buf_addr, mbuf->data_off, 190 DPAA2_GET_FD_OFFSET(fd), DPAA2_GET_FD_ADDR(fd), 191 rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size, 192 DPAA2_GET_FD_BPID(fd), DPAA2_GET_FD_LEN(fd)); 193 } 194 195 196 static inline int __attribute__((hot)) 197 eth_copy_mbuf_to_fd(struct rte_mbuf *mbuf, 198 struct qbman_fd *fd, uint16_t bpid) 199 { 200 struct rte_mbuf *m; 201 void *mb = NULL; 202 203 if (rte_dpaa2_mbuf_alloc_bulk( 204 rte_dpaa2_bpid_info[bpid].bp_list->mp, &mb, 1)) { 205 PMD_TX_LOG(WARNING, "Unable to allocated DPAA2 buffer"); 206 rte_pktmbuf_free(mbuf); 207 return -1; 208 } 209 m = (struct rte_mbuf *)mb; 210 memcpy((char *)m->buf_addr + mbuf->data_off, 211 (void *)((char *)mbuf->buf_addr + mbuf->data_off), 212 mbuf->pkt_len); 213 214 /* Copy required fields */ 215 m->data_off = mbuf->data_off; 216 m->ol_flags = mbuf->ol_flags; 217 m->packet_type = mbuf->packet_type; 218 m->tx_offload = mbuf->tx_offload; 219 220 /*Resetting the buffer pool id and offset field*/ 221 fd->simple.bpid_offset = 0; 222 223 DPAA2_SET_FD_ADDR(fd, DPAA2_MBUF_VADDR_TO_IOVA(m)); 224 DPAA2_SET_FD_LEN(fd, mbuf->data_len); 225 DPAA2_SET_FD_BPID(fd, bpid); 226 DPAA2_SET_FD_OFFSET(fd, mbuf->data_off); 227 DPAA2_SET_FD_ASAL(fd, DPAA2_ASAL_VAL); 228 229 PMD_TX_LOG(DEBUG, " mbuf %p BMAN buf addr %p", 230 (void *)mbuf, mbuf->buf_addr); 231 232 PMD_TX_LOG(DEBUG, " fdaddr =%lx bpid =%d meta =%d off =%d, len =%d", 233 DPAA2_GET_FD_ADDR(fd), 234 DPAA2_GET_FD_BPID(fd), 235 rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size, 236 DPAA2_GET_FD_OFFSET(fd), 237 DPAA2_GET_FD_LEN(fd)); 238 /*free the original packet */ 239 rte_pktmbuf_free(mbuf); 240 241 return 0; 242 } 243 244 uint16_t 245 dpaa2_dev_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts) 246 { 247 /* Function is responsible to receive frames for a given device and VQ*/ 248 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)queue; 249 struct qbman_result *dq_storage; 250 uint32_t fqid = dpaa2_q->fqid; 251 int ret, num_rx = 0; 252 uint8_t is_last = 0, status; 253 struct qbman_swp *swp; 254 const struct qbman_fd *fd; 255 struct qbman_pull_desc pulldesc; 256 struct rte_eth_dev *dev = dpaa2_q->dev; 257 258 if (unlikely(!DPAA2_PER_LCORE_DPIO)) { 259 ret = dpaa2_affine_qbman_swp(); 260 if (ret) { 261 RTE_LOG(ERR, PMD, "Failure in affining portal\n"); 262 return 0; 263 } 264 } 265 swp = DPAA2_PER_LCORE_PORTAL; 266 dq_storage = dpaa2_q->q_storage->dq_storage[0]; 267 268 qbman_pull_desc_clear(&pulldesc); 269 qbman_pull_desc_set_numframes(&pulldesc, 270 (nb_pkts > DPAA2_DQRR_RING_SIZE) ? 271 DPAA2_DQRR_RING_SIZE : nb_pkts); 272 qbman_pull_desc_set_fq(&pulldesc, fqid); 273 /* todo optimization - we can have dq_storage_phys available*/ 274 qbman_pull_desc_set_storage(&pulldesc, dq_storage, 275 (dma_addr_t)(DPAA2_VADDR_TO_IOVA(dq_storage)), 1); 276 277 /*Issue a volatile dequeue command. */ 278 while (1) { 279 if (qbman_swp_pull(swp, &pulldesc)) { 280 PMD_RX_LOG(ERR, "VDQ command is not issued." 281 "QBMAN is busy\n"); 282 /* Portal was busy, try again */ 283 continue; 284 } 285 break; 286 }; 287 288 /* Receive the packets till Last Dequeue entry is found with 289 * respect to the above issues PULL command. 290 */ 291 while (!is_last) { 292 struct rte_mbuf *mbuf; 293 /*Check if the previous issued command is completed. 294 * Also seems like the SWP is shared between the 295 * Ethernet Driver and the SEC driver. 296 */ 297 while (!qbman_check_command_complete(swp, dq_storage)) 298 ; 299 /* Loop until the dq_storage is updated with 300 * new token by QBMAN 301 */ 302 while (!qbman_result_has_new_result(swp, dq_storage)) 303 ; 304 /* Check whether Last Pull command is Expired and 305 * setting Condition for Loop termination 306 */ 307 if (qbman_result_DQ_is_pull_complete(dq_storage)) { 308 is_last = 1; 309 /* Check for valid frame. */ 310 status = (uint8_t)qbman_result_DQ_flags(dq_storage); 311 if (unlikely((status & QBMAN_DQ_STAT_VALIDFRAME) == 0)) 312 continue; 313 } 314 315 fd = qbman_result_DQ_fd(dq_storage); 316 mbuf = (struct rte_mbuf *)DPAA2_IOVA_TO_VADDR( 317 DPAA2_GET_FD_ADDR(fd) 318 - rte_dpaa2_bpid_info[DPAA2_GET_FD_BPID(fd)].meta_data_size); 319 /* Prefeth mbuf */ 320 rte_prefetch0(mbuf); 321 /* Prefetch Annotation address for the parse results */ 322 rte_prefetch0((void *)((uint64_t)DPAA2_GET_FD_ADDR(fd) 323 + DPAA2_FD_PTA_SIZE + 16)); 324 325 bufs[num_rx] = eth_fd_to_mbuf(fd); 326 bufs[num_rx]->port = dev->data->port_id; 327 328 num_rx++; 329 dq_storage++; 330 } /* End of Packet Rx loop */ 331 332 dpaa2_q->rx_pkts += num_rx; 333 334 /*Return the total number of packets received to DPAA2 app*/ 335 return num_rx; 336 } 337 338 /* 339 * Callback to handle sending packets through WRIOP based interface 340 */ 341 uint16_t 342 dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts) 343 { 344 /* Function to transmit the frames to given device and VQ*/ 345 uint32_t loop; 346 int32_t ret; 347 struct qbman_fd fd_arr[MAX_TX_RING_SLOTS]; 348 uint32_t frames_to_send; 349 struct rte_mempool *mp; 350 struct qbman_eq_desc eqdesc; 351 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)queue; 352 struct qbman_swp *swp; 353 uint16_t num_tx = 0; 354 uint16_t bpid; 355 struct rte_eth_dev *dev = dpaa2_q->dev; 356 struct dpaa2_dev_priv *priv = dev->data->dev_private; 357 358 if (unlikely(!DPAA2_PER_LCORE_DPIO)) { 359 ret = dpaa2_affine_qbman_swp(); 360 if (ret) { 361 RTE_LOG(ERR, PMD, "Failure in affining portal\n"); 362 return 0; 363 } 364 } 365 swp = DPAA2_PER_LCORE_PORTAL; 366 367 PMD_TX_LOG(DEBUG, "===> dev =%p, fqid =%d", dev, dpaa2_q->fqid); 368 369 /*Prepare enqueue descriptor*/ 370 qbman_eq_desc_clear(&eqdesc); 371 qbman_eq_desc_set_no_orp(&eqdesc, DPAA2_EQ_RESP_ERR_FQ); 372 qbman_eq_desc_set_response(&eqdesc, 0, 0); 373 qbman_eq_desc_set_qd(&eqdesc, priv->qdid, 374 dpaa2_q->flow_id, dpaa2_q->tc_index); 375 376 /*Clear the unused FD fields before sending*/ 377 while (nb_pkts) { 378 frames_to_send = (nb_pkts >> 3) ? MAX_TX_RING_SLOTS : nb_pkts; 379 380 for (loop = 0; loop < frames_to_send; loop++) { 381 fd_arr[loop].simple.frc = 0; 382 DPAA2_RESET_FD_CTRL((&fd_arr[loop])); 383 DPAA2_SET_FD_FLC((&fd_arr[loop]), NULL); 384 mp = (*bufs)->pool; 385 /* Not a hw_pkt pool allocated frame */ 386 if (mp->ops_index != priv->bp_list->dpaa2_ops_index) { 387 PMD_TX_LOG(ERR, "non hw offload bufffer "); 388 /* alloc should be from the default buffer pool 389 * attached to this interface 390 */ 391 if (priv->bp_list) { 392 bpid = priv->bp_list->buf_pool.bpid; 393 } else { 394 PMD_TX_LOG(ERR, "errr: why no bpool" 395 " attached"); 396 num_tx = 0; 397 goto skip_tx; 398 } 399 if (eth_copy_mbuf_to_fd(*bufs, 400 &fd_arr[loop], bpid)) { 401 bufs++; 402 continue; 403 } 404 } else { 405 bpid = mempool_to_bpid(mp); 406 eth_mbuf_to_fd(*bufs, &fd_arr[loop], bpid); 407 } 408 bufs++; 409 } 410 loop = 0; 411 while (loop < frames_to_send) { 412 loop += qbman_swp_send_multiple(swp, &eqdesc, 413 &fd_arr[loop], frames_to_send - loop); 414 } 415 416 num_tx += frames_to_send; 417 dpaa2_q->tx_pkts += frames_to_send; 418 nb_pkts -= frames_to_send; 419 } 420 skip_tx: 421 return num_tx; 422 } 423