1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright (c) 2015-2016 Freescale Semiconductor, Inc. All rights reserved. 4 * Copyright 2016-2021 NXP 5 * 6 */ 7 8 #ifndef _DPAA2_ETHDEV_H 9 #define _DPAA2_ETHDEV_H 10 11 #include <rte_event_eth_rx_adapter.h> 12 #include <rte_pmd_dpaa2.h> 13 14 #include <dpaa2_hw_pvt.h> 15 #include "dpaa2_tm.h" 16 17 #include <mc/fsl_dpni.h> 18 #include <mc/fsl_mc_sys.h> 19 20 #define DPAA2_MIN_RX_BUF_SIZE 512 21 #define DPAA2_MAX_RX_PKT_LEN 10240 /*WRIOP support*/ 22 #define NET_DPAA2_PMD_DRIVER_NAME net_dpaa2 23 24 #define MAX_TCS DPNI_MAX_TC 25 #define MAX_RX_QUEUES 128 26 #define MAX_TX_QUEUES 16 27 #define MAX_DPNI 8 28 29 #define DPAA2_RX_DEFAULT_NBDESC 512 30 31 #define DPAA2_ETH_MAX_LEN (RTE_ETHER_MTU + \ 32 RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + \ 33 VLAN_TAG_SIZE) 34 35 /*default tc to be used for ,congestion, distribution etc configuration. */ 36 #define DPAA2_DEF_TC 0 37 38 /* Threshold for a Tx queue to *Enter* Congestion state. 39 */ 40 #define CONG_ENTER_TX_THRESHOLD 512 41 42 /* Threshold for a queue to *Exit* Congestion state. 43 */ 44 #define CONG_EXIT_TX_THRESHOLD 480 45 46 #define CONG_RETRY_COUNT 18000 47 48 /* RX queue tail drop threshold 49 * currently considering 64 KB packets 50 */ 51 #define CONG_THRESHOLD_RX_BYTES_Q (64 * 1024) 52 #define CONG_RX_OAL 128 53 54 /* Size of the input SMMU mapped memory required by MC */ 55 #define DIST_PARAM_IOVA_SIZE 256 56 57 /* Enable TX Congestion control support 58 * default is disable 59 */ 60 #define DPAA2_TX_CGR_OFF 0x01 61 62 /* Disable RX tail drop, default is enable */ 63 #define DPAA2_RX_TAILDROP_OFF 0x04 64 /* Tx confirmation enabled */ 65 #define DPAA2_TX_CONF_ENABLE 0x08 66 67 #define DPAA2_RSS_OFFLOAD_ALL ( \ 68 RTE_ETH_RSS_L2_PAYLOAD | \ 69 RTE_ETH_RSS_IP | \ 70 RTE_ETH_RSS_UDP | \ 71 RTE_ETH_RSS_TCP | \ 72 RTE_ETH_RSS_SCTP | \ 73 RTE_ETH_RSS_MPLS | \ 74 RTE_ETH_RSS_C_VLAN | \ 75 RTE_ETH_RSS_S_VLAN | \ 76 RTE_ETH_RSS_ESP | \ 77 RTE_ETH_RSS_AH | \ 78 RTE_ETH_RSS_PPPOE) 79 80 /* LX2 FRC Parsed values (Little Endian) */ 81 #define DPAA2_PKT_TYPE_ETHER 0x0060 82 #define DPAA2_PKT_TYPE_IPV4 0x0000 83 #define DPAA2_PKT_TYPE_IPV6 0x0020 84 #define DPAA2_PKT_TYPE_IPV4_EXT \ 85 (0x0001 | DPAA2_PKT_TYPE_IPV4) 86 #define DPAA2_PKT_TYPE_IPV6_EXT \ 87 (0x0001 | DPAA2_PKT_TYPE_IPV6) 88 #define DPAA2_PKT_TYPE_IPV4_TCP \ 89 (0x000e | DPAA2_PKT_TYPE_IPV4) 90 #define DPAA2_PKT_TYPE_IPV6_TCP \ 91 (0x000e | DPAA2_PKT_TYPE_IPV6) 92 #define DPAA2_PKT_TYPE_IPV4_UDP \ 93 (0x0010 | DPAA2_PKT_TYPE_IPV4) 94 #define DPAA2_PKT_TYPE_IPV6_UDP \ 95 (0x0010 | DPAA2_PKT_TYPE_IPV6) 96 #define DPAA2_PKT_TYPE_IPV4_SCTP \ 97 (0x000f | DPAA2_PKT_TYPE_IPV4) 98 #define DPAA2_PKT_TYPE_IPV6_SCTP \ 99 (0x000f | DPAA2_PKT_TYPE_IPV6) 100 #define DPAA2_PKT_TYPE_IPV4_ICMP \ 101 (0x0003 | DPAA2_PKT_TYPE_IPV4_EXT) 102 #define DPAA2_PKT_TYPE_IPV6_ICMP \ 103 (0x0003 | DPAA2_PKT_TYPE_IPV6_EXT) 104 #define DPAA2_PKT_TYPE_VLAN_1 0x0160 105 #define DPAA2_PKT_TYPE_VLAN_2 0x0260 106 107 /* enable timestamp in mbuf*/ 108 extern bool dpaa2_enable_ts[]; 109 extern uint64_t dpaa2_timestamp_rx_dynflag; 110 extern int dpaa2_timestamp_dynfield_offset; 111 112 #define DPAA2_QOS_TABLE_RECONFIGURE 1 113 #define DPAA2_FS_TABLE_RECONFIGURE 2 114 115 #define DPAA2_QOS_TABLE_IPADDR_EXTRACT 4 116 #define DPAA2_FS_TABLE_IPADDR_EXTRACT 8 117 118 #define DPAA2_FLOW_MAX_KEY_SIZE 16 119 120 /*Externaly defined*/ 121 extern const struct rte_flow_ops dpaa2_flow_ops; 122 123 extern const struct rte_tm_ops dpaa2_tm_ops; 124 125 extern bool dpaa2_enable_err_queue; 126 127 #define IP_ADDRESS_OFFSET_INVALID (-1) 128 129 struct dpaa2_key_info { 130 uint8_t key_offset[DPKG_MAX_NUM_OF_EXTRACTS]; 131 uint8_t key_size[DPKG_MAX_NUM_OF_EXTRACTS]; 132 /* Special for IP address. */ 133 int ipv4_src_offset; 134 int ipv4_dst_offset; 135 int ipv6_src_offset; 136 int ipv6_dst_offset; 137 uint8_t key_total_size; 138 }; 139 140 struct dpaa2_key_extract { 141 struct dpkg_profile_cfg dpkg; 142 struct dpaa2_key_info key_info; 143 }; 144 145 struct extract_s { 146 struct dpaa2_key_extract qos_key_extract; 147 struct dpaa2_key_extract tc_key_extract[MAX_TCS]; 148 uint64_t qos_extract_param; 149 uint64_t tc_extract_param[MAX_TCS]; 150 }; 151 152 struct dpaa2_dev_priv { 153 void *hw; 154 int32_t hw_id; 155 int32_t qdid; 156 uint16_t token; 157 uint8_t nb_tx_queues; 158 uint8_t nb_rx_queues; 159 uint32_t options; 160 void *rx_vq[MAX_RX_QUEUES]; 161 void *tx_vq[MAX_TX_QUEUES]; 162 struct dpaa2_bp_list *bp_list; /**<Attached buffer pool list */ 163 void *tx_conf_vq[MAX_TX_QUEUES]; 164 void *rx_err_vq; 165 uint8_t flags; /*dpaa2 config flags */ 166 uint8_t max_mac_filters; 167 uint8_t max_vlan_filters; 168 uint8_t num_rx_tc; 169 uint16_t qos_entries; 170 uint16_t fs_entries; 171 uint8_t dist_queues; 172 uint8_t en_ordered; 173 uint8_t en_loose_ordered; 174 uint8_t max_cgs; 175 uint8_t cgid_in_use[MAX_RX_QUEUES]; 176 177 struct extract_s extract; 178 179 uint16_t ss_offset; 180 uint64_t ss_iova; 181 uint64_t ss_param_iova; 182 /*stores timestamp of last received packet on dev*/ 183 uint64_t rx_timestamp; 184 /*stores timestamp of last received tx confirmation packet on dev*/ 185 uint64_t tx_timestamp; 186 /* stores pointer to next tx_conf queue that should be processed, 187 * it corresponds to last packet transmitted 188 */ 189 struct dpaa2_queue *next_tx_conf_queue; 190 191 struct rte_eth_dev *eth_dev; /**< Pointer back to holding ethdev */ 192 193 LIST_HEAD(, rte_flow) flows; /**< Configured flow rule handles. */ 194 LIST_HEAD(nodes, dpaa2_tm_node) nodes; 195 LIST_HEAD(shaper_profiles, dpaa2_tm_shaper_profile) shaper_profiles; 196 }; 197 198 int dpaa2_distset_to_dpkg_profile_cfg(uint64_t req_dist_set, 199 struct dpkg_profile_cfg *kg_cfg); 200 201 int dpaa2_setup_flow_dist(struct rte_eth_dev *eth_dev, 202 uint64_t req_dist_set, int tc_index); 203 204 int dpaa2_remove_flow_dist(struct rte_eth_dev *eth_dev, 205 uint8_t tc_index); 206 207 int dpaa2_attach_bp_list(struct dpaa2_dev_priv *priv, void *blist); 208 209 __rte_internal 210 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev, 211 int eth_rx_queue_id, 212 struct dpaa2_dpcon_dev *dpcon, 213 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf); 214 215 __rte_internal 216 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev, 217 int eth_rx_queue_id); 218 219 uint16_t dpaa2_dev_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts); 220 221 uint16_t dpaa2_dev_loopback_rx(void *queue, struct rte_mbuf **bufs, 222 uint16_t nb_pkts); 223 224 uint16_t dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs, 225 uint16_t nb_pkts); 226 void dpaa2_dev_process_parallel_event(struct qbman_swp *swp, 227 const struct qbman_fd *fd, 228 const struct qbman_result *dq, 229 struct dpaa2_queue *rxq, 230 struct rte_event *ev); 231 void dpaa2_dev_process_atomic_event(struct qbman_swp *swp, 232 const struct qbman_fd *fd, 233 const struct qbman_result *dq, 234 struct dpaa2_queue *rxq, 235 struct rte_event *ev); 236 void dpaa2_dev_process_ordered_event(struct qbman_swp *swp, 237 const struct qbman_fd *fd, 238 const struct qbman_result *dq, 239 struct dpaa2_queue *rxq, 240 struct rte_event *ev); 241 uint16_t dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts); 242 uint16_t dpaa2_dev_tx_ordered(void *queue, struct rte_mbuf **bufs, 243 uint16_t nb_pkts); 244 uint16_t dummy_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts); 245 void dpaa2_dev_free_eqresp_buf(uint16_t eqresp_ci); 246 void dpaa2_flow_clean(struct rte_eth_dev *dev); 247 uint16_t dpaa2_dev_tx_conf(void *queue) __rte_unused; 248 int dpaa2_dev_is_dpaa2(struct rte_eth_dev *dev); 249 250 int dpaa2_timesync_enable(struct rte_eth_dev *dev); 251 int dpaa2_timesync_disable(struct rte_eth_dev *dev); 252 int dpaa2_timesync_read_time(struct rte_eth_dev *dev, 253 struct timespec *timestamp); 254 int dpaa2_timesync_write_time(struct rte_eth_dev *dev, 255 const struct timespec *timestamp); 256 int dpaa2_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta); 257 int dpaa2_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 258 struct timespec *timestamp, 259 uint32_t flags __rte_unused); 260 int dpaa2_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 261 struct timespec *timestamp); 262 #endif /* _DPAA2_ETHDEV_H */ 263