1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright (c) 2015-2016 Freescale Semiconductor, Inc. All rights reserved. 4 * Copyright 2016 NXP 5 * 6 */ 7 8 #ifndef _DPAA2_ETHDEV_H 9 #define _DPAA2_ETHDEV_H 10 11 #include <rte_event_eth_rx_adapter.h> 12 13 #include <mc/fsl_dpni.h> 14 #include <mc/fsl_mc_sys.h> 15 16 #define DPAA2_MIN_RX_BUF_SIZE 512 17 #define DPAA2_MAX_RX_PKT_LEN 10240 /*WRIOP support*/ 18 19 #define MAX_TCS DPNI_MAX_TC 20 #define MAX_RX_QUEUES 16 21 #define MAX_TX_QUEUES 16 22 23 /*default tc to be used for ,congestion, distribution etc configuration. */ 24 #define DPAA2_DEF_TC 0 25 26 /* Threshold for a Tx queue to *Enter* Congestion state. 27 */ 28 #define CONG_ENTER_TX_THRESHOLD 512 29 30 /* Threshold for a queue to *Exit* Congestion state. 31 */ 32 #define CONG_EXIT_TX_THRESHOLD 480 33 34 #define CONG_RETRY_COUNT 18000 35 36 /* RX queue tail drop threshold 37 * currently considering 32 KB packets 38 */ 39 #define CONG_THRESHOLD_RX_Q (64 * 1024) 40 #define CONG_RX_OAL 128 41 42 /* Size of the input SMMU mapped memory required by MC */ 43 #define DIST_PARAM_IOVA_SIZE 256 44 45 /* Enable TX Congestion control support 46 * default is disable 47 */ 48 #define DPAA2_TX_CGR_OFF 0x01 49 50 /* Disable RX tail drop, default is enable */ 51 #define DPAA2_RX_TAILDROP_OFF 0x04 52 53 /* LX2 FRC Parsed values (Little Endian) */ 54 #define DPAA2_PKT_TYPE_ETHER 0x0060 55 #define DPAA2_PKT_TYPE_IPV4 0x0000 56 #define DPAA2_PKT_TYPE_IPV6 0x0020 57 #define DPAA2_PKT_TYPE_IPV4_EXT \ 58 (0x0001 | DPAA2_PKT_TYPE_IPV4) 59 #define DPAA2_PKT_TYPE_IPV6_EXT \ 60 (0x0001 | DPAA2_PKT_TYPE_IPV6) 61 #define DPAA2_PKT_TYPE_IPV4_TCP \ 62 (0x000e | DPAA2_PKT_TYPE_IPV4) 63 #define DPAA2_PKT_TYPE_IPV6_TCP \ 64 (0x000e | DPAA2_PKT_TYPE_IPV6) 65 #define DPAA2_PKT_TYPE_IPV4_UDP \ 66 (0x0010 | DPAA2_PKT_TYPE_IPV4) 67 #define DPAA2_PKT_TYPE_IPV6_UDP \ 68 (0x0010 | DPAA2_PKT_TYPE_IPV6) 69 #define DPAA2_PKT_TYPE_IPV4_SCTP \ 70 (0x000f | DPAA2_PKT_TYPE_IPV4) 71 #define DPAA2_PKT_TYPE_IPV6_SCTP \ 72 (0x000f | DPAA2_PKT_TYPE_IPV6) 73 #define DPAA2_PKT_TYPE_IPV4_ICMP \ 74 (0x0003 | DPAA2_PKT_TYPE_IPV4_EXT) 75 #define DPAA2_PKT_TYPE_IPV6_ICMP \ 76 (0x0003 | DPAA2_PKT_TYPE_IPV6_EXT) 77 #define DPAA2_PKT_TYPE_VLAN_1 0x0160 78 #define DPAA2_PKT_TYPE_VLAN_2 0x0260 79 80 struct dpaa2_dev_priv { 81 void *hw; 82 int32_t hw_id; 83 int32_t qdid; 84 uint16_t token; 85 uint8_t nb_tx_queues; 86 uint8_t nb_rx_queues; 87 void *rx_vq[MAX_RX_QUEUES]; 88 void *tx_vq[MAX_TX_QUEUES]; 89 90 struct dpaa2_bp_list *bp_list; /**<Attached buffer pool list */ 91 uint32_t options; 92 uint8_t max_mac_filters; 93 uint8_t max_vlan_filters; 94 uint8_t num_rx_tc; 95 uint8_t flags; /*dpaa2 config flags */ 96 }; 97 98 int dpaa2_setup_flow_dist(struct rte_eth_dev *eth_dev, 99 uint64_t req_dist_set); 100 101 int dpaa2_remove_flow_dist(struct rte_eth_dev *eth_dev, 102 uint8_t tc_index); 103 104 int dpaa2_attach_bp_list(struct dpaa2_dev_priv *priv, void *blist); 105 106 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev, 107 int eth_rx_queue_id, 108 uint16_t dpcon_id, 109 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf); 110 111 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev, 112 int eth_rx_queue_id); 113 114 uint16_t dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs, 115 uint16_t nb_pkts); 116 void dpaa2_dev_process_parallel_event(struct qbman_swp *swp, 117 const struct qbman_fd *fd, 118 const struct qbman_result *dq, 119 struct dpaa2_queue *rxq, 120 struct rte_event *ev); 121 void dpaa2_dev_process_atomic_event(struct qbman_swp *swp, 122 const struct qbman_fd *fd, 123 const struct qbman_result *dq, 124 struct dpaa2_queue *rxq, 125 struct rte_event *ev); 126 uint16_t dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts); 127 uint16_t dummy_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts); 128 #endif /* _DPAA2_ETHDEV_H */ 129