1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright (c) 2015-2016 Freescale Semiconductor, Inc. All rights reserved. 4 * Copyright 2016-2020 NXP 5 * 6 */ 7 8 #ifndef _DPAA2_ETHDEV_H 9 #define _DPAA2_ETHDEV_H 10 11 #include <rte_event_eth_rx_adapter.h> 12 #include <rte_pmd_dpaa2.h> 13 14 #include <dpaa2_hw_pvt.h> 15 16 #include <mc/fsl_dpni.h> 17 #include <mc/fsl_mc_sys.h> 18 19 #define DPAA2_MIN_RX_BUF_SIZE 512 20 #define DPAA2_MAX_RX_PKT_LEN 10240 /*WRIOP support*/ 21 22 #define MAX_TCS DPNI_MAX_TC 23 #define MAX_RX_QUEUES 128 24 #define MAX_TX_QUEUES 16 25 #define MAX_DPNI 8 26 27 #define DPAA2_RX_DEFAULT_NBDESC 512 28 29 /*default tc to be used for ,congestion, distribution etc configuration. */ 30 #define DPAA2_DEF_TC 0 31 32 /* Threshold for a Tx queue to *Enter* Congestion state. 33 */ 34 #define CONG_ENTER_TX_THRESHOLD 512 35 36 /* Threshold for a queue to *Exit* Congestion state. 37 */ 38 #define CONG_EXIT_TX_THRESHOLD 480 39 40 #define CONG_RETRY_COUNT 18000 41 42 /* RX queue tail drop threshold 43 * currently considering 64 KB packets 44 */ 45 #define CONG_THRESHOLD_RX_BYTES_Q (64 * 1024) 46 #define CONG_RX_OAL 128 47 48 /* Size of the input SMMU mapped memory required by MC */ 49 #define DIST_PARAM_IOVA_SIZE 256 50 51 /* Enable TX Congestion control support 52 * default is disable 53 */ 54 #define DPAA2_TX_CGR_OFF 0x01 55 56 /* Disable RX tail drop, default is enable */ 57 #define DPAA2_RX_TAILDROP_OFF 0x04 58 59 #define DPAA2_RSS_OFFLOAD_ALL ( \ 60 ETH_RSS_L2_PAYLOAD | \ 61 ETH_RSS_IP | \ 62 ETH_RSS_UDP | \ 63 ETH_RSS_TCP | \ 64 ETH_RSS_SCTP) 65 66 /* LX2 FRC Parsed values (Little Endian) */ 67 #define DPAA2_PKT_TYPE_ETHER 0x0060 68 #define DPAA2_PKT_TYPE_IPV4 0x0000 69 #define DPAA2_PKT_TYPE_IPV6 0x0020 70 #define DPAA2_PKT_TYPE_IPV4_EXT \ 71 (0x0001 | DPAA2_PKT_TYPE_IPV4) 72 #define DPAA2_PKT_TYPE_IPV6_EXT \ 73 (0x0001 | DPAA2_PKT_TYPE_IPV6) 74 #define DPAA2_PKT_TYPE_IPV4_TCP \ 75 (0x000e | DPAA2_PKT_TYPE_IPV4) 76 #define DPAA2_PKT_TYPE_IPV6_TCP \ 77 (0x000e | DPAA2_PKT_TYPE_IPV6) 78 #define DPAA2_PKT_TYPE_IPV4_UDP \ 79 (0x0010 | DPAA2_PKT_TYPE_IPV4) 80 #define DPAA2_PKT_TYPE_IPV6_UDP \ 81 (0x0010 | DPAA2_PKT_TYPE_IPV6) 82 #define DPAA2_PKT_TYPE_IPV4_SCTP \ 83 (0x000f | DPAA2_PKT_TYPE_IPV4) 84 #define DPAA2_PKT_TYPE_IPV6_SCTP \ 85 (0x000f | DPAA2_PKT_TYPE_IPV6) 86 #define DPAA2_PKT_TYPE_IPV4_ICMP \ 87 (0x0003 | DPAA2_PKT_TYPE_IPV4_EXT) 88 #define DPAA2_PKT_TYPE_IPV6_ICMP \ 89 (0x0003 | DPAA2_PKT_TYPE_IPV6_EXT) 90 #define DPAA2_PKT_TYPE_VLAN_1 0x0160 91 #define DPAA2_PKT_TYPE_VLAN_2 0x0260 92 93 /* enable timestamp in mbuf*/ 94 extern bool dpaa2_enable_ts[]; 95 extern uint64_t dpaa2_timestamp_rx_dynflag; 96 extern int dpaa2_timestamp_dynfield_offset; 97 98 #define DPAA2_QOS_TABLE_RECONFIGURE 1 99 #define DPAA2_FS_TABLE_RECONFIGURE 2 100 101 #define DPAA2_QOS_TABLE_IPADDR_EXTRACT 4 102 #define DPAA2_FS_TABLE_IPADDR_EXTRACT 8 103 104 #define DPAA2_FLOW_MAX_KEY_SIZE 16 105 106 /*Externaly defined*/ 107 extern const struct rte_flow_ops dpaa2_flow_ops; 108 extern enum rte_filter_type dpaa2_filter_type; 109 110 #define IP_ADDRESS_OFFSET_INVALID (-1) 111 112 struct dpaa2_key_info { 113 uint8_t key_offset[DPKG_MAX_NUM_OF_EXTRACTS]; 114 uint8_t key_size[DPKG_MAX_NUM_OF_EXTRACTS]; 115 /* Special for IP address. */ 116 int ipv4_src_offset; 117 int ipv4_dst_offset; 118 int ipv6_src_offset; 119 int ipv6_dst_offset; 120 uint8_t key_total_size; 121 }; 122 123 struct dpaa2_key_extract { 124 struct dpkg_profile_cfg dpkg; 125 struct dpaa2_key_info key_info; 126 }; 127 128 struct extract_s { 129 struct dpaa2_key_extract qos_key_extract; 130 struct dpaa2_key_extract tc_key_extract[MAX_TCS]; 131 uint64_t qos_extract_param; 132 uint64_t tc_extract_param[MAX_TCS]; 133 }; 134 135 struct dpaa2_dev_priv { 136 void *hw; 137 int32_t hw_id; 138 int32_t qdid; 139 uint16_t token; 140 uint8_t nb_tx_queues; 141 uint8_t nb_rx_queues; 142 uint32_t options; 143 void *rx_vq[MAX_RX_QUEUES]; 144 void *tx_vq[MAX_TX_QUEUES]; 145 struct dpaa2_bp_list *bp_list; /**<Attached buffer pool list */ 146 void *tx_conf_vq[MAX_TX_QUEUES]; 147 uint8_t tx_conf_en; 148 uint8_t max_mac_filters; 149 uint8_t max_vlan_filters; 150 uint8_t num_rx_tc; 151 uint16_t qos_entries; 152 uint16_t fs_entries; 153 uint8_t dist_queues; 154 uint8_t flags; /*dpaa2 config flags */ 155 uint8_t en_ordered; 156 uint8_t en_loose_ordered; 157 uint8_t max_cgs; 158 uint8_t cgid_in_use[MAX_RX_QUEUES]; 159 160 struct extract_s extract; 161 162 uint16_t ss_offset; 163 uint64_t ss_iova; 164 uint64_t ss_param_iova; 165 /*stores timestamp of last received packet on dev*/ 166 uint64_t rx_timestamp; 167 /*stores timestamp of last received tx confirmation packet on dev*/ 168 uint64_t tx_timestamp; 169 /* stores pointer to next tx_conf queue that should be processed, 170 * it corresponds to last packet transmitted 171 */ 172 struct dpaa2_queue *next_tx_conf_queue; 173 174 struct rte_eth_dev *eth_dev; /**< Pointer back to holding ethdev */ 175 176 LIST_HEAD(, rte_flow) flows; /**< Configured flow rule handles. */ 177 }; 178 179 int dpaa2_distset_to_dpkg_profile_cfg(uint64_t req_dist_set, 180 struct dpkg_profile_cfg *kg_cfg); 181 182 int dpaa2_setup_flow_dist(struct rte_eth_dev *eth_dev, 183 uint64_t req_dist_set, int tc_index); 184 185 int dpaa2_remove_flow_dist(struct rte_eth_dev *eth_dev, 186 uint8_t tc_index); 187 188 int dpaa2_attach_bp_list(struct dpaa2_dev_priv *priv, void *blist); 189 190 __rte_internal 191 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev, 192 int eth_rx_queue_id, 193 struct dpaa2_dpcon_dev *dpcon, 194 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf); 195 196 __rte_internal 197 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev, 198 int eth_rx_queue_id); 199 200 uint16_t dpaa2_dev_rx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts); 201 202 uint16_t dpaa2_dev_loopback_rx(void *queue, struct rte_mbuf **bufs, 203 uint16_t nb_pkts); 204 205 uint16_t dpaa2_dev_prefetch_rx(void *queue, struct rte_mbuf **bufs, 206 uint16_t nb_pkts); 207 void dpaa2_dev_process_parallel_event(struct qbman_swp *swp, 208 const struct qbman_fd *fd, 209 const struct qbman_result *dq, 210 struct dpaa2_queue *rxq, 211 struct rte_event *ev); 212 void dpaa2_dev_process_atomic_event(struct qbman_swp *swp, 213 const struct qbman_fd *fd, 214 const struct qbman_result *dq, 215 struct dpaa2_queue *rxq, 216 struct rte_event *ev); 217 void dpaa2_dev_process_ordered_event(struct qbman_swp *swp, 218 const struct qbman_fd *fd, 219 const struct qbman_result *dq, 220 struct dpaa2_queue *rxq, 221 struct rte_event *ev); 222 uint16_t dpaa2_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts); 223 uint16_t dpaa2_dev_tx_ordered(void *queue, struct rte_mbuf **bufs, 224 uint16_t nb_pkts); 225 uint16_t dummy_dev_tx(void *queue, struct rte_mbuf **bufs, uint16_t nb_pkts); 226 void dpaa2_dev_free_eqresp_buf(uint16_t eqresp_ci); 227 void dpaa2_flow_clean(struct rte_eth_dev *dev); 228 uint16_t dpaa2_dev_tx_conf(void *queue) __rte_unused; 229 230 int dpaa2_timesync_enable(struct rte_eth_dev *dev); 231 int dpaa2_timesync_disable(struct rte_eth_dev *dev); 232 int dpaa2_timesync_read_time(struct rte_eth_dev *dev, 233 struct timespec *timestamp); 234 int dpaa2_timesync_write_time(struct rte_eth_dev *dev, 235 const struct timespec *timestamp); 236 int dpaa2_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta); 237 int dpaa2_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 238 struct timespec *timestamp, 239 uint32_t flags __rte_unused); 240 int dpaa2_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 241 struct timespec *timestamp); 242 #endif /* _DPAA2_ETHDEV_H */ 243