1 /* * SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved. 4 * Copyright 2016-2020 NXP 5 * 6 */ 7 8 #include <time.h> 9 #include <net/if.h> 10 11 #include <rte_mbuf.h> 12 #include <rte_ethdev_driver.h> 13 #include <rte_malloc.h> 14 #include <rte_memcpy.h> 15 #include <rte_string_fns.h> 16 #include <rte_cycles.h> 17 #include <rte_kvargs.h> 18 #include <rte_dev.h> 19 #include <rte_fslmc.h> 20 #include <rte_flow_driver.h> 21 22 #include "dpaa2_pmd_logs.h" 23 #include <fslmc_vfio.h> 24 #include <dpaa2_hw_pvt.h> 25 #include <dpaa2_hw_mempool.h> 26 #include <dpaa2_hw_dpio.h> 27 #include <mc/fsl_dpmng.h> 28 #include "dpaa2_ethdev.h" 29 #include "dpaa2_sparser.h" 30 #include <fsl_qbman_debug.h> 31 32 #define DRIVER_LOOPBACK_MODE "drv_loopback" 33 #define DRIVER_NO_PREFETCH_MODE "drv_no_prefetch" 34 35 /* Supported Rx offloads */ 36 static uint64_t dev_rx_offloads_sup = 37 DEV_RX_OFFLOAD_CHECKSUM | 38 DEV_RX_OFFLOAD_SCTP_CKSUM | 39 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 40 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | 41 DEV_RX_OFFLOAD_VLAN_STRIP | 42 DEV_RX_OFFLOAD_VLAN_FILTER | 43 DEV_RX_OFFLOAD_JUMBO_FRAME | 44 DEV_RX_OFFLOAD_TIMESTAMP; 45 46 /* Rx offloads which cannot be disabled */ 47 static uint64_t dev_rx_offloads_nodis = 48 DEV_RX_OFFLOAD_RSS_HASH | 49 DEV_RX_OFFLOAD_SCATTER; 50 51 /* Supported Tx offloads */ 52 static uint64_t dev_tx_offloads_sup = 53 DEV_TX_OFFLOAD_VLAN_INSERT | 54 DEV_TX_OFFLOAD_IPV4_CKSUM | 55 DEV_TX_OFFLOAD_UDP_CKSUM | 56 DEV_TX_OFFLOAD_TCP_CKSUM | 57 DEV_TX_OFFLOAD_SCTP_CKSUM | 58 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 59 DEV_TX_OFFLOAD_MT_LOCKFREE | 60 DEV_TX_OFFLOAD_MBUF_FAST_FREE; 61 62 /* Tx offloads which cannot be disabled */ 63 static uint64_t dev_tx_offloads_nodis = 64 DEV_TX_OFFLOAD_MULTI_SEGS; 65 66 /* enable timestamp in mbuf */ 67 bool dpaa2_enable_ts[RTE_MAX_ETHPORTS]; 68 69 struct rte_dpaa2_xstats_name_off { 70 char name[RTE_ETH_XSTATS_NAME_SIZE]; 71 uint8_t page_id; /* dpni statistics page id */ 72 uint8_t stats_id; /* stats id in the given page */ 73 }; 74 75 static const struct rte_dpaa2_xstats_name_off dpaa2_xstats_strings[] = { 76 {"ingress_multicast_frames", 0, 2}, 77 {"ingress_multicast_bytes", 0, 3}, 78 {"ingress_broadcast_frames", 0, 4}, 79 {"ingress_broadcast_bytes", 0, 5}, 80 {"egress_multicast_frames", 1, 2}, 81 {"egress_multicast_bytes", 1, 3}, 82 {"egress_broadcast_frames", 1, 4}, 83 {"egress_broadcast_bytes", 1, 5}, 84 {"ingress_filtered_frames", 2, 0}, 85 {"ingress_discarded_frames", 2, 1}, 86 {"ingress_nobuffer_discards", 2, 2}, 87 {"egress_discarded_frames", 2, 3}, 88 {"egress_confirmed_frames", 2, 4}, 89 {"cgr_reject_frames", 4, 0}, 90 {"cgr_reject_bytes", 4, 1}, 91 }; 92 93 static const enum rte_filter_op dpaa2_supported_filter_ops[] = { 94 RTE_ETH_FILTER_ADD, 95 RTE_ETH_FILTER_DELETE, 96 RTE_ETH_FILTER_UPDATE, 97 RTE_ETH_FILTER_FLUSH, 98 RTE_ETH_FILTER_GET 99 }; 100 101 static struct rte_dpaa2_driver rte_dpaa2_pmd; 102 static int dpaa2_dev_link_update(struct rte_eth_dev *dev, 103 int wait_to_complete); 104 static int dpaa2_dev_set_link_up(struct rte_eth_dev *dev); 105 static int dpaa2_dev_set_link_down(struct rte_eth_dev *dev); 106 static int dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 107 108 static int 109 dpaa2_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 110 { 111 int ret; 112 struct dpaa2_dev_priv *priv = dev->data->dev_private; 113 struct fsl_mc_io *dpni = dev->process_private; 114 115 PMD_INIT_FUNC_TRACE(); 116 117 if (dpni == NULL) { 118 DPAA2_PMD_ERR("dpni is NULL"); 119 return -1; 120 } 121 122 if (on) 123 ret = dpni_add_vlan_id(dpni, CMD_PRI_LOW, priv->token, 124 vlan_id, 0, 0, 0); 125 else 126 ret = dpni_remove_vlan_id(dpni, CMD_PRI_LOW, 127 priv->token, vlan_id); 128 129 if (ret < 0) 130 DPAA2_PMD_ERR("ret = %d Unable to add/rem vlan %d hwid =%d", 131 ret, vlan_id, priv->hw_id); 132 133 return ret; 134 } 135 136 static int 137 dpaa2_vlan_offload_set(struct rte_eth_dev *dev, int mask) 138 { 139 struct dpaa2_dev_priv *priv = dev->data->dev_private; 140 struct fsl_mc_io *dpni = dev->process_private; 141 int ret = 0; 142 143 PMD_INIT_FUNC_TRACE(); 144 145 if (mask & ETH_VLAN_FILTER_MASK) { 146 /* VLAN Filter not avaialble */ 147 if (!priv->max_vlan_filters) { 148 DPAA2_PMD_INFO("VLAN filter not available"); 149 return -ENOTSUP; 150 } 151 152 if (dev->data->dev_conf.rxmode.offloads & 153 DEV_RX_OFFLOAD_VLAN_FILTER) 154 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW, 155 priv->token, true); 156 else 157 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW, 158 priv->token, false); 159 if (ret < 0) 160 DPAA2_PMD_INFO("Unable to set vlan filter = %d", ret); 161 } 162 163 return ret; 164 } 165 166 static int 167 dpaa2_vlan_tpid_set(struct rte_eth_dev *dev, 168 enum rte_vlan_type vlan_type __rte_unused, 169 uint16_t tpid) 170 { 171 struct dpaa2_dev_priv *priv = dev->data->dev_private; 172 struct fsl_mc_io *dpni = dev->process_private; 173 int ret = -ENOTSUP; 174 175 PMD_INIT_FUNC_TRACE(); 176 177 /* nothing to be done for standard vlan tpids */ 178 if (tpid == 0x8100 || tpid == 0x88A8) 179 return 0; 180 181 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW, 182 priv->token, tpid); 183 if (ret < 0) 184 DPAA2_PMD_INFO("Unable to set vlan tpid = %d", ret); 185 /* if already configured tpids, remove them first */ 186 if (ret == -EBUSY) { 187 struct dpni_custom_tpid_cfg tpid_list = {0}; 188 189 ret = dpni_get_custom_tpid(dpni, CMD_PRI_LOW, 190 priv->token, &tpid_list); 191 if (ret < 0) 192 goto fail; 193 ret = dpni_remove_custom_tpid(dpni, CMD_PRI_LOW, 194 priv->token, tpid_list.tpid1); 195 if (ret < 0) 196 goto fail; 197 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW, 198 priv->token, tpid); 199 } 200 fail: 201 return ret; 202 } 203 204 static int 205 dpaa2_fw_version_get(struct rte_eth_dev *dev, 206 char *fw_version, 207 size_t fw_size) 208 { 209 int ret; 210 struct fsl_mc_io *dpni = dev->process_private; 211 struct mc_soc_version mc_plat_info = {0}; 212 struct mc_version mc_ver_info = {0}; 213 214 PMD_INIT_FUNC_TRACE(); 215 216 if (mc_get_soc_version(dpni, CMD_PRI_LOW, &mc_plat_info)) 217 DPAA2_PMD_WARN("\tmc_get_soc_version failed"); 218 219 if (mc_get_version(dpni, CMD_PRI_LOW, &mc_ver_info)) 220 DPAA2_PMD_WARN("\tmc_get_version failed"); 221 222 ret = snprintf(fw_version, fw_size, 223 "%x-%d.%d.%d", 224 mc_plat_info.svr, 225 mc_ver_info.major, 226 mc_ver_info.minor, 227 mc_ver_info.revision); 228 229 ret += 1; /* add the size of '\0' */ 230 if (fw_size < (uint32_t)ret) 231 return ret; 232 else 233 return 0; 234 } 235 236 static int 237 dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 238 { 239 struct dpaa2_dev_priv *priv = dev->data->dev_private; 240 241 PMD_INIT_FUNC_TRACE(); 242 243 dev_info->max_mac_addrs = priv->max_mac_filters; 244 dev_info->max_rx_pktlen = DPAA2_MAX_RX_PKT_LEN; 245 dev_info->min_rx_bufsize = DPAA2_MIN_RX_BUF_SIZE; 246 dev_info->max_rx_queues = (uint16_t)priv->nb_rx_queues; 247 dev_info->max_tx_queues = (uint16_t)priv->nb_tx_queues; 248 dev_info->rx_offload_capa = dev_rx_offloads_sup | 249 dev_rx_offloads_nodis; 250 dev_info->tx_offload_capa = dev_tx_offloads_sup | 251 dev_tx_offloads_nodis; 252 dev_info->speed_capa = ETH_LINK_SPEED_1G | 253 ETH_LINK_SPEED_2_5G | 254 ETH_LINK_SPEED_10G; 255 256 dev_info->max_hash_mac_addrs = 0; 257 dev_info->max_vfs = 0; 258 dev_info->max_vmdq_pools = ETH_16_POOLS; 259 dev_info->flow_type_rss_offloads = DPAA2_RSS_OFFLOAD_ALL; 260 261 dev_info->default_rxportconf.burst_size = dpaa2_dqrr_size; 262 /* same is rx size for best perf */ 263 dev_info->default_txportconf.burst_size = dpaa2_dqrr_size; 264 265 dev_info->default_rxportconf.nb_queues = 1; 266 dev_info->default_txportconf.nb_queues = 1; 267 dev_info->default_txportconf.ring_size = CONG_ENTER_TX_THRESHOLD; 268 dev_info->default_rxportconf.ring_size = DPAA2_RX_DEFAULT_NBDESC; 269 270 if (dpaa2_svr_family == SVR_LX2160A) { 271 dev_info->speed_capa |= ETH_LINK_SPEED_25G | 272 ETH_LINK_SPEED_40G | 273 ETH_LINK_SPEED_50G | 274 ETH_LINK_SPEED_100G; 275 } 276 277 return 0; 278 } 279 280 static int 281 dpaa2_dev_rx_burst_mode_get(struct rte_eth_dev *dev, 282 __rte_unused uint16_t queue_id, 283 struct rte_eth_burst_mode *mode) 284 { 285 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 286 int ret = -EINVAL; 287 unsigned int i; 288 const struct burst_info { 289 uint64_t flags; 290 const char *output; 291 } rx_offload_map[] = { 292 {DEV_RX_OFFLOAD_CHECKSUM, " Checksum,"}, 293 {DEV_RX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"}, 294 {DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"}, 295 {DEV_RX_OFFLOAD_OUTER_UDP_CKSUM, " Outer UDP csum,"}, 296 {DEV_RX_OFFLOAD_VLAN_STRIP, " VLAN strip,"}, 297 {DEV_RX_OFFLOAD_VLAN_FILTER, " VLAN filter,"}, 298 {DEV_RX_OFFLOAD_JUMBO_FRAME, " Jumbo frame,"}, 299 {DEV_RX_OFFLOAD_TIMESTAMP, " Timestamp,"}, 300 {DEV_RX_OFFLOAD_RSS_HASH, " RSS,"}, 301 {DEV_RX_OFFLOAD_SCATTER, " Scattered,"} 302 }; 303 304 /* Update Rx offload info */ 305 for (i = 0; i < RTE_DIM(rx_offload_map); i++) { 306 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) { 307 snprintf(mode->info, sizeof(mode->info), "%s", 308 rx_offload_map[i].output); 309 ret = 0; 310 break; 311 } 312 } 313 return ret; 314 } 315 316 static int 317 dpaa2_dev_tx_burst_mode_get(struct rte_eth_dev *dev, 318 __rte_unused uint16_t queue_id, 319 struct rte_eth_burst_mode *mode) 320 { 321 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 322 int ret = -EINVAL; 323 unsigned int i; 324 const struct burst_info { 325 uint64_t flags; 326 const char *output; 327 } tx_offload_map[] = { 328 {DEV_TX_OFFLOAD_VLAN_INSERT, " VLAN Insert,"}, 329 {DEV_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"}, 330 {DEV_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"}, 331 {DEV_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"}, 332 {DEV_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"}, 333 {DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"}, 334 {DEV_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"}, 335 {DEV_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"}, 336 {DEV_TX_OFFLOAD_MULTI_SEGS, " Scattered,"} 337 }; 338 339 /* Update Tx offload info */ 340 for (i = 0; i < RTE_DIM(tx_offload_map); i++) { 341 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) { 342 snprintf(mode->info, sizeof(mode->info), "%s", 343 tx_offload_map[i].output); 344 ret = 0; 345 break; 346 } 347 } 348 return ret; 349 } 350 351 static int 352 dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev) 353 { 354 struct dpaa2_dev_priv *priv = dev->data->dev_private; 355 uint16_t dist_idx; 356 uint32_t vq_id; 357 uint8_t num_rxqueue_per_tc; 358 struct dpaa2_queue *mc_q, *mcq; 359 uint32_t tot_queues; 360 int i; 361 struct dpaa2_queue *dpaa2_q; 362 363 PMD_INIT_FUNC_TRACE(); 364 365 num_rxqueue_per_tc = (priv->nb_rx_queues / priv->num_rx_tc); 366 if (priv->tx_conf_en) 367 tot_queues = priv->nb_rx_queues + 2 * priv->nb_tx_queues; 368 else 369 tot_queues = priv->nb_rx_queues + priv->nb_tx_queues; 370 mc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues, 371 RTE_CACHE_LINE_SIZE); 372 if (!mc_q) { 373 DPAA2_PMD_ERR("Memory allocation failed for rx/tx queues"); 374 return -1; 375 } 376 377 for (i = 0; i < priv->nb_rx_queues; i++) { 378 mc_q->eth_data = dev->data; 379 priv->rx_vq[i] = mc_q++; 380 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i]; 381 dpaa2_q->q_storage = rte_malloc("dq_storage", 382 sizeof(struct queue_storage_info_t), 383 RTE_CACHE_LINE_SIZE); 384 if (!dpaa2_q->q_storage) 385 goto fail; 386 387 memset(dpaa2_q->q_storage, 0, 388 sizeof(struct queue_storage_info_t)); 389 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage)) 390 goto fail; 391 } 392 393 for (i = 0; i < priv->nb_tx_queues; i++) { 394 mc_q->eth_data = dev->data; 395 mc_q->flow_id = 0xffff; 396 priv->tx_vq[i] = mc_q++; 397 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; 398 dpaa2_q->cscn = rte_malloc(NULL, 399 sizeof(struct qbman_result), 16); 400 if (!dpaa2_q->cscn) 401 goto fail_tx; 402 } 403 404 if (priv->tx_conf_en) { 405 /*Setup tx confirmation queues*/ 406 for (i = 0; i < priv->nb_tx_queues; i++) { 407 mc_q->eth_data = dev->data; 408 mc_q->tc_index = i; 409 mc_q->flow_id = 0; 410 priv->tx_conf_vq[i] = mc_q++; 411 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i]; 412 dpaa2_q->q_storage = 413 rte_malloc("dq_storage", 414 sizeof(struct queue_storage_info_t), 415 RTE_CACHE_LINE_SIZE); 416 if (!dpaa2_q->q_storage) 417 goto fail_tx_conf; 418 419 memset(dpaa2_q->q_storage, 0, 420 sizeof(struct queue_storage_info_t)); 421 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage)) 422 goto fail_tx_conf; 423 } 424 } 425 426 vq_id = 0; 427 for (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) { 428 mcq = (struct dpaa2_queue *)priv->rx_vq[vq_id]; 429 mcq->tc_index = dist_idx / num_rxqueue_per_tc; 430 mcq->flow_id = dist_idx % num_rxqueue_per_tc; 431 vq_id++; 432 } 433 434 return 0; 435 fail_tx_conf: 436 i -= 1; 437 while (i >= 0) { 438 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i]; 439 rte_free(dpaa2_q->q_storage); 440 priv->tx_conf_vq[i--] = NULL; 441 } 442 i = priv->nb_tx_queues; 443 fail_tx: 444 i -= 1; 445 while (i >= 0) { 446 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; 447 rte_free(dpaa2_q->cscn); 448 priv->tx_vq[i--] = NULL; 449 } 450 i = priv->nb_rx_queues; 451 fail: 452 i -= 1; 453 mc_q = priv->rx_vq[0]; 454 while (i >= 0) { 455 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i]; 456 dpaa2_free_dq_storage(dpaa2_q->q_storage); 457 rte_free(dpaa2_q->q_storage); 458 priv->rx_vq[i--] = NULL; 459 } 460 rte_free(mc_q); 461 return -1; 462 } 463 464 static void 465 dpaa2_free_rx_tx_queues(struct rte_eth_dev *dev) 466 { 467 struct dpaa2_dev_priv *priv = dev->data->dev_private; 468 struct dpaa2_queue *dpaa2_q; 469 int i; 470 471 PMD_INIT_FUNC_TRACE(); 472 473 /* Queue allocation base */ 474 if (priv->rx_vq[0]) { 475 /* cleaning up queue storage */ 476 for (i = 0; i < priv->nb_rx_queues; i++) { 477 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i]; 478 if (dpaa2_q->q_storage) 479 rte_free(dpaa2_q->q_storage); 480 } 481 /* cleanup tx queue cscn */ 482 for (i = 0; i < priv->nb_tx_queues; i++) { 483 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; 484 rte_free(dpaa2_q->cscn); 485 } 486 if (priv->tx_conf_en) { 487 /* cleanup tx conf queue storage */ 488 for (i = 0; i < priv->nb_tx_queues; i++) { 489 dpaa2_q = (struct dpaa2_queue *) 490 priv->tx_conf_vq[i]; 491 rte_free(dpaa2_q->q_storage); 492 } 493 } 494 /*free memory for all queues (RX+TX) */ 495 rte_free(priv->rx_vq[0]); 496 priv->rx_vq[0] = NULL; 497 } 498 } 499 500 static int 501 dpaa2_eth_dev_configure(struct rte_eth_dev *dev) 502 { 503 struct dpaa2_dev_priv *priv = dev->data->dev_private; 504 struct fsl_mc_io *dpni = dev->process_private; 505 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 506 uint64_t rx_offloads = eth_conf->rxmode.offloads; 507 uint64_t tx_offloads = eth_conf->txmode.offloads; 508 int rx_l3_csum_offload = false; 509 int rx_l4_csum_offload = false; 510 int tx_l3_csum_offload = false; 511 int tx_l4_csum_offload = false; 512 int ret, tc_index; 513 514 PMD_INIT_FUNC_TRACE(); 515 516 /* Rx offloads which are enabled by default */ 517 if (dev_rx_offloads_nodis & ~rx_offloads) { 518 DPAA2_PMD_INFO( 519 "Some of rx offloads enabled by default - requested 0x%" PRIx64 520 " fixed are 0x%" PRIx64, 521 rx_offloads, dev_rx_offloads_nodis); 522 } 523 524 /* Tx offloads which are enabled by default */ 525 if (dev_tx_offloads_nodis & ~tx_offloads) { 526 DPAA2_PMD_INFO( 527 "Some of tx offloads enabled by default - requested 0x%" PRIx64 528 " fixed are 0x%" PRIx64, 529 tx_offloads, dev_tx_offloads_nodis); 530 } 531 532 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 533 if (eth_conf->rxmode.max_rx_pkt_len <= DPAA2_MAX_RX_PKT_LEN) { 534 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, 535 priv->token, eth_conf->rxmode.max_rx_pkt_len 536 - RTE_ETHER_CRC_LEN); 537 if (ret) { 538 DPAA2_PMD_ERR( 539 "Unable to set mtu. check config"); 540 return ret; 541 } 542 dev->data->mtu = 543 dev->data->dev_conf.rxmode.max_rx_pkt_len - 544 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - 545 VLAN_TAG_SIZE; 546 } else { 547 return -1; 548 } 549 } 550 551 if (eth_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) { 552 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) { 553 ret = dpaa2_setup_flow_dist(dev, 554 eth_conf->rx_adv_conf.rss_conf.rss_hf, 555 tc_index); 556 if (ret) { 557 DPAA2_PMD_ERR( 558 "Unable to set flow distribution on tc%d." 559 "Check queue config", tc_index); 560 return ret; 561 } 562 } 563 } 564 565 if (rx_offloads & DEV_RX_OFFLOAD_IPV4_CKSUM) 566 rx_l3_csum_offload = true; 567 568 if ((rx_offloads & DEV_RX_OFFLOAD_UDP_CKSUM) || 569 (rx_offloads & DEV_RX_OFFLOAD_TCP_CKSUM) || 570 (rx_offloads & DEV_RX_OFFLOAD_SCTP_CKSUM)) 571 rx_l4_csum_offload = true; 572 573 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 574 DPNI_OFF_RX_L3_CSUM, rx_l3_csum_offload); 575 if (ret) { 576 DPAA2_PMD_ERR("Error to set RX l3 csum:Error = %d", ret); 577 return ret; 578 } 579 580 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 581 DPNI_OFF_RX_L4_CSUM, rx_l4_csum_offload); 582 if (ret) { 583 DPAA2_PMD_ERR("Error to get RX l4 csum:Error = %d", ret); 584 return ret; 585 } 586 587 #if !defined(RTE_LIBRTE_IEEE1588) 588 if (rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) 589 #endif 590 dpaa2_enable_ts[dev->data->port_id] = true; 591 592 if (tx_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM) 593 tx_l3_csum_offload = true; 594 595 if ((tx_offloads & DEV_TX_OFFLOAD_UDP_CKSUM) || 596 (tx_offloads & DEV_TX_OFFLOAD_TCP_CKSUM) || 597 (tx_offloads & DEV_TX_OFFLOAD_SCTP_CKSUM)) 598 tx_l4_csum_offload = true; 599 600 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 601 DPNI_OFF_TX_L3_CSUM, tx_l3_csum_offload); 602 if (ret) { 603 DPAA2_PMD_ERR("Error to set TX l3 csum:Error = %d", ret); 604 return ret; 605 } 606 607 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 608 DPNI_OFF_TX_L4_CSUM, tx_l4_csum_offload); 609 if (ret) { 610 DPAA2_PMD_ERR("Error to get TX l4 csum:Error = %d", ret); 611 return ret; 612 } 613 614 /* Enabling hash results in FD requires setting DPNI_FLCTYPE_HASH in 615 * dpni_set_offload API. Setting this FLCTYPE for DPNI sets the FD[SC] 616 * to 0 for LS2 in the hardware thus disabling data/annotation 617 * stashing. For LX2 this is fixed in hardware and thus hash result and 618 * parse results can be received in FD using this option. 619 */ 620 if (dpaa2_svr_family == SVR_LX2160A) { 621 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 622 DPNI_FLCTYPE_HASH, true); 623 if (ret) { 624 DPAA2_PMD_ERR("Error setting FLCTYPE: Err = %d", ret); 625 return ret; 626 } 627 } 628 629 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 630 dpaa2_vlan_offload_set(dev, ETH_VLAN_FILTER_MASK); 631 632 return 0; 633 } 634 635 /* Function to setup RX flow information. It contains traffic class ID, 636 * flow ID, destination configuration etc. 637 */ 638 static int 639 dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev, 640 uint16_t rx_queue_id, 641 uint16_t nb_rx_desc, 642 unsigned int socket_id __rte_unused, 643 const struct rte_eth_rxconf *rx_conf, 644 struct rte_mempool *mb_pool) 645 { 646 struct dpaa2_dev_priv *priv = dev->data->dev_private; 647 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 648 struct dpaa2_queue *dpaa2_q; 649 struct dpni_queue cfg; 650 uint8_t options = 0; 651 uint8_t flow_id; 652 uint32_t bpid; 653 int i, ret; 654 655 PMD_INIT_FUNC_TRACE(); 656 657 DPAA2_PMD_DEBUG("dev =%p, queue =%d, pool = %p, conf =%p", 658 dev, rx_queue_id, mb_pool, rx_conf); 659 660 /* Rx deferred start is not supported */ 661 if (rx_conf->rx_deferred_start) { 662 DPAA2_PMD_ERR("%p:Rx deferred start not supported", 663 (void *)dev); 664 return -EINVAL; 665 } 666 667 if (!priv->bp_list || priv->bp_list->mp != mb_pool) { 668 bpid = mempool_to_bpid(mb_pool); 669 ret = dpaa2_attach_bp_list(priv, 670 rte_dpaa2_bpid_info[bpid].bp_list); 671 if (ret) 672 return ret; 673 } 674 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id]; 675 dpaa2_q->mb_pool = mb_pool; /**< mbuf pool to populate RX ring. */ 676 dpaa2_q->bp_array = rte_dpaa2_bpid_info; 677 dpaa2_q->nb_desc = UINT16_MAX; 678 dpaa2_q->offloads = rx_conf->offloads; 679 680 /*Get the flow id from given VQ id*/ 681 flow_id = dpaa2_q->flow_id; 682 memset(&cfg, 0, sizeof(struct dpni_queue)); 683 684 options = options | DPNI_QUEUE_OPT_USER_CTX; 685 cfg.user_context = (size_t)(dpaa2_q); 686 687 /* check if a private cgr available. */ 688 for (i = 0; i < priv->max_cgs; i++) { 689 if (!priv->cgid_in_use[i]) { 690 priv->cgid_in_use[i] = 1; 691 break; 692 } 693 } 694 695 if (i < priv->max_cgs) { 696 options |= DPNI_QUEUE_OPT_SET_CGID; 697 cfg.cgid = i; 698 dpaa2_q->cgid = cfg.cgid; 699 } else { 700 dpaa2_q->cgid = 0xff; 701 } 702 703 /*if ls2088 or rev2 device, enable the stashing */ 704 705 if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) { 706 options |= DPNI_QUEUE_OPT_FLC; 707 cfg.flc.stash_control = true; 708 cfg.flc.value &= 0xFFFFFFFFFFFFFFC0; 709 /* 00 00 00 - last 6 bit represent annotation, context stashing, 710 * data stashing setting 01 01 00 (0x14) 711 * (in following order ->DS AS CS) 712 * to enable 1 line data, 1 line annotation. 713 * For LX2, this setting should be 01 00 00 (0x10) 714 */ 715 if ((dpaa2_svr_family & 0xffff0000) == SVR_LX2160A) 716 cfg.flc.value |= 0x10; 717 else 718 cfg.flc.value |= 0x14; 719 } 720 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX, 721 dpaa2_q->tc_index, flow_id, options, &cfg); 722 if (ret) { 723 DPAA2_PMD_ERR("Error in setting the rx flow: = %d", ret); 724 return -1; 725 } 726 727 if (!(priv->flags & DPAA2_RX_TAILDROP_OFF)) { 728 struct dpni_taildrop taildrop; 729 730 taildrop.enable = 1; 731 dpaa2_q->nb_desc = nb_rx_desc; 732 /* Private CGR will use tail drop length as nb_rx_desc. 733 * for rest cases we can use standard byte based tail drop. 734 * There is no HW restriction, but number of CGRs are limited, 735 * hence this restriction is placed. 736 */ 737 if (dpaa2_q->cgid != 0xff) { 738 /*enabling per rx queue congestion control */ 739 taildrop.threshold = nb_rx_desc; 740 taildrop.units = DPNI_CONGESTION_UNIT_FRAMES; 741 taildrop.oal = 0; 742 DPAA2_PMD_DEBUG("Enabling CG Tail Drop on queue = %d", 743 rx_queue_id); 744 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token, 745 DPNI_CP_CONGESTION_GROUP, 746 DPNI_QUEUE_RX, 747 dpaa2_q->tc_index, 748 dpaa2_q->cgid, &taildrop); 749 } else { 750 /*enabling per rx queue congestion control */ 751 taildrop.threshold = CONG_THRESHOLD_RX_BYTES_Q; 752 taildrop.units = DPNI_CONGESTION_UNIT_BYTES; 753 taildrop.oal = CONG_RX_OAL; 754 DPAA2_PMD_DEBUG("Enabling Byte based Drop on queue= %d", 755 rx_queue_id); 756 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token, 757 DPNI_CP_QUEUE, DPNI_QUEUE_RX, 758 dpaa2_q->tc_index, flow_id, 759 &taildrop); 760 } 761 if (ret) { 762 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)", 763 ret); 764 return -1; 765 } 766 } else { /* Disable tail Drop */ 767 struct dpni_taildrop taildrop = {0}; 768 DPAA2_PMD_INFO("Tail drop is disabled on queue"); 769 770 taildrop.enable = 0; 771 if (dpaa2_q->cgid != 0xff) { 772 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token, 773 DPNI_CP_CONGESTION_GROUP, DPNI_QUEUE_RX, 774 dpaa2_q->tc_index, 775 dpaa2_q->cgid, &taildrop); 776 } else { 777 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token, 778 DPNI_CP_QUEUE, DPNI_QUEUE_RX, 779 dpaa2_q->tc_index, flow_id, &taildrop); 780 } 781 if (ret) { 782 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)", 783 ret); 784 return -1; 785 } 786 } 787 788 dev->data->rx_queues[rx_queue_id] = dpaa2_q; 789 return 0; 790 } 791 792 static int 793 dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev, 794 uint16_t tx_queue_id, 795 uint16_t nb_tx_desc, 796 unsigned int socket_id __rte_unused, 797 const struct rte_eth_txconf *tx_conf) 798 { 799 struct dpaa2_dev_priv *priv = dev->data->dev_private; 800 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *) 801 priv->tx_vq[tx_queue_id]; 802 struct dpaa2_queue *dpaa2_tx_conf_q = (struct dpaa2_queue *) 803 priv->tx_conf_vq[tx_queue_id]; 804 struct fsl_mc_io *dpni = dev->process_private; 805 struct dpni_queue tx_conf_cfg; 806 struct dpni_queue tx_flow_cfg; 807 uint8_t options = 0, flow_id; 808 struct dpni_queue_id qid; 809 uint32_t tc_id; 810 int ret; 811 812 PMD_INIT_FUNC_TRACE(); 813 814 /* Tx deferred start is not supported */ 815 if (tx_conf->tx_deferred_start) { 816 DPAA2_PMD_ERR("%p:Tx deferred start not supported", 817 (void *)dev); 818 return -EINVAL; 819 } 820 821 dpaa2_q->nb_desc = UINT16_MAX; 822 dpaa2_q->offloads = tx_conf->offloads; 823 824 /* Return if queue already configured */ 825 if (dpaa2_q->flow_id != 0xffff) { 826 dev->data->tx_queues[tx_queue_id] = dpaa2_q; 827 return 0; 828 } 829 830 memset(&tx_conf_cfg, 0, sizeof(struct dpni_queue)); 831 memset(&tx_flow_cfg, 0, sizeof(struct dpni_queue)); 832 833 tc_id = tx_queue_id; 834 flow_id = 0; 835 836 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX, 837 tc_id, flow_id, options, &tx_flow_cfg); 838 if (ret) { 839 DPAA2_PMD_ERR("Error in setting the tx flow: " 840 "tc_id=%d, flow=%d err=%d", 841 tc_id, flow_id, ret); 842 return -1; 843 } 844 845 dpaa2_q->flow_id = flow_id; 846 847 if (tx_queue_id == 0) { 848 /*Set tx-conf and error configuration*/ 849 if (priv->tx_conf_en) 850 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW, 851 priv->token, 852 DPNI_CONF_AFFINE); 853 else 854 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW, 855 priv->token, 856 DPNI_CONF_DISABLE); 857 if (ret) { 858 DPAA2_PMD_ERR("Error in set tx conf mode settings: " 859 "err=%d", ret); 860 return -1; 861 } 862 } 863 dpaa2_q->tc_index = tc_id; 864 865 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token, 866 DPNI_QUEUE_TX, dpaa2_q->tc_index, 867 dpaa2_q->flow_id, &tx_flow_cfg, &qid); 868 if (ret) { 869 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret); 870 return -1; 871 } 872 dpaa2_q->fqid = qid.fqid; 873 874 if (!(priv->flags & DPAA2_TX_CGR_OFF)) { 875 struct dpni_congestion_notification_cfg cong_notif_cfg = {0}; 876 877 dpaa2_q->nb_desc = nb_tx_desc; 878 879 cong_notif_cfg.units = DPNI_CONGESTION_UNIT_FRAMES; 880 cong_notif_cfg.threshold_entry = nb_tx_desc; 881 /* Notify that the queue is not congested when the data in 882 * the queue is below this thershold. 883 */ 884 cong_notif_cfg.threshold_exit = nb_tx_desc - 24; 885 cong_notif_cfg.message_ctx = 0; 886 cong_notif_cfg.message_iova = 887 (size_t)DPAA2_VADDR_TO_IOVA(dpaa2_q->cscn); 888 cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE; 889 cong_notif_cfg.notification_mode = 890 DPNI_CONG_OPT_WRITE_MEM_ON_ENTER | 891 DPNI_CONG_OPT_WRITE_MEM_ON_EXIT | 892 DPNI_CONG_OPT_COHERENT_WRITE; 893 cong_notif_cfg.cg_point = DPNI_CP_QUEUE; 894 895 ret = dpni_set_congestion_notification(dpni, CMD_PRI_LOW, 896 priv->token, 897 DPNI_QUEUE_TX, 898 tc_id, 899 &cong_notif_cfg); 900 if (ret) { 901 DPAA2_PMD_ERR( 902 "Error in setting tx congestion notification: " 903 "err=%d", ret); 904 return -ret; 905 } 906 } 907 dpaa2_q->cb_eqresp_free = dpaa2_dev_free_eqresp_buf; 908 dev->data->tx_queues[tx_queue_id] = dpaa2_q; 909 910 if (priv->tx_conf_en) { 911 dpaa2_q->tx_conf_queue = dpaa2_tx_conf_q; 912 options = options | DPNI_QUEUE_OPT_USER_CTX; 913 tx_conf_cfg.user_context = (size_t)(dpaa2_q); 914 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, 915 DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index, 916 dpaa2_tx_conf_q->flow_id, options, &tx_conf_cfg); 917 if (ret) { 918 DPAA2_PMD_ERR("Error in setting the tx conf flow: " 919 "tc_index=%d, flow=%d err=%d", 920 dpaa2_tx_conf_q->tc_index, 921 dpaa2_tx_conf_q->flow_id, ret); 922 return -1; 923 } 924 925 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token, 926 DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index, 927 dpaa2_tx_conf_q->flow_id, &tx_conf_cfg, &qid); 928 if (ret) { 929 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret); 930 return -1; 931 } 932 dpaa2_tx_conf_q->fqid = qid.fqid; 933 } 934 return 0; 935 } 936 937 static void 938 dpaa2_dev_rx_queue_release(void *q __rte_unused) 939 { 940 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)q; 941 struct dpaa2_dev_priv *priv = dpaa2_q->eth_data->dev_private; 942 struct fsl_mc_io *dpni = 943 (struct fsl_mc_io *)priv->eth_dev->process_private; 944 uint8_t options = 0; 945 int ret; 946 struct dpni_queue cfg; 947 948 memset(&cfg, 0, sizeof(struct dpni_queue)); 949 PMD_INIT_FUNC_TRACE(); 950 if (dpaa2_q->cgid != 0xff) { 951 options = DPNI_QUEUE_OPT_CLEAR_CGID; 952 cfg.cgid = dpaa2_q->cgid; 953 954 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, 955 DPNI_QUEUE_RX, 956 dpaa2_q->tc_index, dpaa2_q->flow_id, 957 options, &cfg); 958 if (ret) 959 DPAA2_PMD_ERR("Unable to clear CGR from q=%u err=%d", 960 dpaa2_q->fqid, ret); 961 priv->cgid_in_use[dpaa2_q->cgid] = 0; 962 dpaa2_q->cgid = 0xff; 963 } 964 } 965 966 static void 967 dpaa2_dev_tx_queue_release(void *q __rte_unused) 968 { 969 PMD_INIT_FUNC_TRACE(); 970 } 971 972 static uint32_t 973 dpaa2_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id) 974 { 975 int32_t ret; 976 struct dpaa2_dev_priv *priv = dev->data->dev_private; 977 struct dpaa2_queue *dpaa2_q; 978 struct qbman_swp *swp; 979 struct qbman_fq_query_np_rslt state; 980 uint32_t frame_cnt = 0; 981 982 if (unlikely(!DPAA2_PER_LCORE_DPIO)) { 983 ret = dpaa2_affine_qbman_swp(); 984 if (ret) { 985 DPAA2_PMD_ERR( 986 "Failed to allocate IO portal, tid: %d\n", 987 rte_gettid()); 988 return -EINVAL; 989 } 990 } 991 swp = DPAA2_PER_LCORE_PORTAL; 992 993 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id]; 994 995 if (qbman_fq_query_state(swp, dpaa2_q->fqid, &state) == 0) { 996 frame_cnt = qbman_fq_state_frame_count(&state); 997 DPAA2_PMD_DP_DEBUG("RX frame count for q(%d) is %u", 998 rx_queue_id, frame_cnt); 999 } 1000 return frame_cnt; 1001 } 1002 1003 static const uint32_t * 1004 dpaa2_supported_ptypes_get(struct rte_eth_dev *dev) 1005 { 1006 static const uint32_t ptypes[] = { 1007 /*todo -= add more types */ 1008 RTE_PTYPE_L2_ETHER, 1009 RTE_PTYPE_L3_IPV4, 1010 RTE_PTYPE_L3_IPV4_EXT, 1011 RTE_PTYPE_L3_IPV6, 1012 RTE_PTYPE_L3_IPV6_EXT, 1013 RTE_PTYPE_L4_TCP, 1014 RTE_PTYPE_L4_UDP, 1015 RTE_PTYPE_L4_SCTP, 1016 RTE_PTYPE_L4_ICMP, 1017 RTE_PTYPE_UNKNOWN 1018 }; 1019 1020 if (dev->rx_pkt_burst == dpaa2_dev_prefetch_rx || 1021 dev->rx_pkt_burst == dpaa2_dev_rx || 1022 dev->rx_pkt_burst == dpaa2_dev_loopback_rx) 1023 return ptypes; 1024 return NULL; 1025 } 1026 1027 /** 1028 * Dpaa2 link Interrupt handler 1029 * 1030 * @param param 1031 * The address of parameter (struct rte_eth_dev *) regsitered before. 1032 * 1033 * @return 1034 * void 1035 */ 1036 static void 1037 dpaa2_interrupt_handler(void *param) 1038 { 1039 struct rte_eth_dev *dev = param; 1040 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1041 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1042 int ret; 1043 int irq_index = DPNI_IRQ_INDEX; 1044 unsigned int status = 0, clear = 0; 1045 1046 PMD_INIT_FUNC_TRACE(); 1047 1048 if (dpni == NULL) { 1049 DPAA2_PMD_ERR("dpni is NULL"); 1050 return; 1051 } 1052 1053 ret = dpni_get_irq_status(dpni, CMD_PRI_LOW, priv->token, 1054 irq_index, &status); 1055 if (unlikely(ret)) { 1056 DPAA2_PMD_ERR("Can't get irq status (err %d)", ret); 1057 clear = 0xffffffff; 1058 goto out; 1059 } 1060 1061 if (status & DPNI_IRQ_EVENT_LINK_CHANGED) { 1062 clear = DPNI_IRQ_EVENT_LINK_CHANGED; 1063 dpaa2_dev_link_update(dev, 0); 1064 /* calling all the apps registered for link status event */ 1065 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL); 1066 } 1067 out: 1068 ret = dpni_clear_irq_status(dpni, CMD_PRI_LOW, priv->token, 1069 irq_index, clear); 1070 if (unlikely(ret)) 1071 DPAA2_PMD_ERR("Can't clear irq status (err %d)", ret); 1072 } 1073 1074 static int 1075 dpaa2_eth_setup_irqs(struct rte_eth_dev *dev, int enable) 1076 { 1077 int err = 0; 1078 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1079 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1080 int irq_index = DPNI_IRQ_INDEX; 1081 unsigned int mask = DPNI_IRQ_EVENT_LINK_CHANGED; 1082 1083 PMD_INIT_FUNC_TRACE(); 1084 1085 err = dpni_set_irq_mask(dpni, CMD_PRI_LOW, priv->token, 1086 irq_index, mask); 1087 if (err < 0) { 1088 DPAA2_PMD_ERR("Error: dpni_set_irq_mask():%d (%s)", err, 1089 strerror(-err)); 1090 return err; 1091 } 1092 1093 err = dpni_set_irq_enable(dpni, CMD_PRI_LOW, priv->token, 1094 irq_index, enable); 1095 if (err < 0) 1096 DPAA2_PMD_ERR("Error: dpni_set_irq_enable():%d (%s)", err, 1097 strerror(-err)); 1098 1099 return err; 1100 } 1101 1102 static int 1103 dpaa2_dev_start(struct rte_eth_dev *dev) 1104 { 1105 struct rte_device *rdev = dev->device; 1106 struct rte_dpaa2_device *dpaa2_dev; 1107 struct rte_eth_dev_data *data = dev->data; 1108 struct dpaa2_dev_priv *priv = data->dev_private; 1109 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1110 struct dpni_queue cfg; 1111 struct dpni_error_cfg err_cfg; 1112 uint16_t qdid; 1113 struct dpni_queue_id qid; 1114 struct dpaa2_queue *dpaa2_q; 1115 int ret, i; 1116 struct rte_intr_handle *intr_handle; 1117 1118 dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device); 1119 intr_handle = &dpaa2_dev->intr_handle; 1120 1121 PMD_INIT_FUNC_TRACE(); 1122 1123 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token); 1124 if (ret) { 1125 DPAA2_PMD_ERR("Failure in enabling dpni %d device: err=%d", 1126 priv->hw_id, ret); 1127 return ret; 1128 } 1129 1130 /* Power up the phy. Needed to make the link go UP */ 1131 dpaa2_dev_set_link_up(dev); 1132 1133 ret = dpni_get_qdid(dpni, CMD_PRI_LOW, priv->token, 1134 DPNI_QUEUE_TX, &qdid); 1135 if (ret) { 1136 DPAA2_PMD_ERR("Error in getting qdid: err=%d", ret); 1137 return ret; 1138 } 1139 priv->qdid = qdid; 1140 1141 for (i = 0; i < data->nb_rx_queues; i++) { 1142 dpaa2_q = (struct dpaa2_queue *)data->rx_queues[i]; 1143 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token, 1144 DPNI_QUEUE_RX, dpaa2_q->tc_index, 1145 dpaa2_q->flow_id, &cfg, &qid); 1146 if (ret) { 1147 DPAA2_PMD_ERR("Error in getting flow information: " 1148 "err=%d", ret); 1149 return ret; 1150 } 1151 dpaa2_q->fqid = qid.fqid; 1152 } 1153 1154 /*checksum errors, send them to normal path and set it in annotation */ 1155 err_cfg.errors = DPNI_ERROR_L3CE | DPNI_ERROR_L4CE; 1156 err_cfg.errors |= DPNI_ERROR_PHE; 1157 1158 err_cfg.error_action = DPNI_ERROR_ACTION_CONTINUE; 1159 err_cfg.set_frame_annotation = true; 1160 1161 ret = dpni_set_errors_behavior(dpni, CMD_PRI_LOW, 1162 priv->token, &err_cfg); 1163 if (ret) { 1164 DPAA2_PMD_ERR("Error to dpni_set_errors_behavior: code = %d", 1165 ret); 1166 return ret; 1167 } 1168 1169 /* if the interrupts were configured on this devices*/ 1170 if (intr_handle && (intr_handle->fd) && 1171 (dev->data->dev_conf.intr_conf.lsc != 0)) { 1172 /* Registering LSC interrupt handler */ 1173 rte_intr_callback_register(intr_handle, 1174 dpaa2_interrupt_handler, 1175 (void *)dev); 1176 1177 /* enable vfio intr/eventfd mapping 1178 * Interrupt index 0 is required, so we can not use 1179 * rte_intr_enable. 1180 */ 1181 rte_dpaa2_intr_enable(intr_handle, DPNI_IRQ_INDEX); 1182 1183 /* enable dpni_irqs */ 1184 dpaa2_eth_setup_irqs(dev, 1); 1185 } 1186 1187 /* Change the tx burst function if ordered queues are used */ 1188 if (priv->en_ordered) 1189 dev->tx_pkt_burst = dpaa2_dev_tx_ordered; 1190 1191 return 0; 1192 } 1193 1194 /** 1195 * This routine disables all traffic on the adapter by issuing a 1196 * global reset on the MAC. 1197 */ 1198 static int 1199 dpaa2_dev_stop(struct rte_eth_dev *dev) 1200 { 1201 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1202 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1203 int ret; 1204 struct rte_eth_link link; 1205 struct rte_intr_handle *intr_handle = dev->intr_handle; 1206 1207 PMD_INIT_FUNC_TRACE(); 1208 1209 /* reset interrupt callback */ 1210 if (intr_handle && (intr_handle->fd) && 1211 (dev->data->dev_conf.intr_conf.lsc != 0)) { 1212 /*disable dpni irqs */ 1213 dpaa2_eth_setup_irqs(dev, 0); 1214 1215 /* disable vfio intr before callback unregister */ 1216 rte_dpaa2_intr_disable(intr_handle, DPNI_IRQ_INDEX); 1217 1218 /* Unregistering LSC interrupt handler */ 1219 rte_intr_callback_unregister(intr_handle, 1220 dpaa2_interrupt_handler, 1221 (void *)dev); 1222 } 1223 1224 dpaa2_dev_set_link_down(dev); 1225 1226 ret = dpni_disable(dpni, CMD_PRI_LOW, priv->token); 1227 if (ret) { 1228 DPAA2_PMD_ERR("Failure (ret %d) in disabling dpni %d dev", 1229 ret, priv->hw_id); 1230 return ret; 1231 } 1232 1233 /* clear the recorded link status */ 1234 memset(&link, 0, sizeof(link)); 1235 rte_eth_linkstatus_set(dev, &link); 1236 1237 return 0; 1238 } 1239 1240 static int 1241 dpaa2_dev_close(struct rte_eth_dev *dev) 1242 { 1243 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1244 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1245 int i, ret; 1246 struct rte_eth_link link; 1247 1248 PMD_INIT_FUNC_TRACE(); 1249 1250 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1251 return 0; 1252 1253 if (!dpni) { 1254 DPAA2_PMD_WARN("Already closed or not started"); 1255 return -1; 1256 } 1257 1258 dpaa2_flow_clean(dev); 1259 /* Clean the device first */ 1260 ret = dpni_reset(dpni, CMD_PRI_LOW, priv->token); 1261 if (ret) { 1262 DPAA2_PMD_ERR("Failure cleaning dpni device: err=%d", ret); 1263 return -1; 1264 } 1265 1266 memset(&link, 0, sizeof(link)); 1267 rte_eth_linkstatus_set(dev, &link); 1268 1269 /* Free private queues memory */ 1270 dpaa2_free_rx_tx_queues(dev); 1271 /* Close the device at underlying layer*/ 1272 ret = dpni_close(dpni, CMD_PRI_LOW, priv->token); 1273 if (ret) { 1274 DPAA2_PMD_ERR("Failure closing dpni device with err code %d", 1275 ret); 1276 } 1277 1278 /* Free the allocated memory for ethernet private data and dpni*/ 1279 priv->hw = NULL; 1280 dev->process_private = NULL; 1281 rte_free(dpni); 1282 1283 for (i = 0; i < MAX_TCS; i++) 1284 rte_free((void *)(size_t)priv->extract.tc_extract_param[i]); 1285 1286 if (priv->extract.qos_extract_param) 1287 rte_free((void *)(size_t)priv->extract.qos_extract_param); 1288 1289 DPAA2_PMD_INFO("%s: netdev deleted", dev->data->name); 1290 return 0; 1291 } 1292 1293 static int 1294 dpaa2_dev_promiscuous_enable( 1295 struct rte_eth_dev *dev) 1296 { 1297 int ret; 1298 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1299 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1300 1301 PMD_INIT_FUNC_TRACE(); 1302 1303 if (dpni == NULL) { 1304 DPAA2_PMD_ERR("dpni is NULL"); 1305 return -ENODEV; 1306 } 1307 1308 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, true); 1309 if (ret < 0) 1310 DPAA2_PMD_ERR("Unable to enable U promisc mode %d", ret); 1311 1312 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true); 1313 if (ret < 0) 1314 DPAA2_PMD_ERR("Unable to enable M promisc mode %d", ret); 1315 1316 return ret; 1317 } 1318 1319 static int 1320 dpaa2_dev_promiscuous_disable( 1321 struct rte_eth_dev *dev) 1322 { 1323 int ret; 1324 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1325 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1326 1327 PMD_INIT_FUNC_TRACE(); 1328 1329 if (dpni == NULL) { 1330 DPAA2_PMD_ERR("dpni is NULL"); 1331 return -ENODEV; 1332 } 1333 1334 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, false); 1335 if (ret < 0) 1336 DPAA2_PMD_ERR("Unable to disable U promisc mode %d", ret); 1337 1338 if (dev->data->all_multicast == 0) { 1339 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, 1340 priv->token, false); 1341 if (ret < 0) 1342 DPAA2_PMD_ERR("Unable to disable M promisc mode %d", 1343 ret); 1344 } 1345 1346 return ret; 1347 } 1348 1349 static int 1350 dpaa2_dev_allmulticast_enable( 1351 struct rte_eth_dev *dev) 1352 { 1353 int ret; 1354 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1355 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1356 1357 PMD_INIT_FUNC_TRACE(); 1358 1359 if (dpni == NULL) { 1360 DPAA2_PMD_ERR("dpni is NULL"); 1361 return -ENODEV; 1362 } 1363 1364 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true); 1365 if (ret < 0) 1366 DPAA2_PMD_ERR("Unable to enable multicast mode %d", ret); 1367 1368 return ret; 1369 } 1370 1371 static int 1372 dpaa2_dev_allmulticast_disable(struct rte_eth_dev *dev) 1373 { 1374 int ret; 1375 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1376 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1377 1378 PMD_INIT_FUNC_TRACE(); 1379 1380 if (dpni == NULL) { 1381 DPAA2_PMD_ERR("dpni is NULL"); 1382 return -ENODEV; 1383 } 1384 1385 /* must remain on for all promiscuous */ 1386 if (dev->data->promiscuous == 1) 1387 return 0; 1388 1389 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, false); 1390 if (ret < 0) 1391 DPAA2_PMD_ERR("Unable to disable multicast mode %d", ret); 1392 1393 return ret; 1394 } 1395 1396 static int 1397 dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 1398 { 1399 int ret; 1400 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1401 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1402 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN 1403 + VLAN_TAG_SIZE; 1404 1405 PMD_INIT_FUNC_TRACE(); 1406 1407 if (dpni == NULL) { 1408 DPAA2_PMD_ERR("dpni is NULL"); 1409 return -EINVAL; 1410 } 1411 1412 /* check that mtu is within the allowed range */ 1413 if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA2_MAX_RX_PKT_LEN) 1414 return -EINVAL; 1415 1416 if (frame_size > RTE_ETHER_MAX_LEN) 1417 dev->data->dev_conf.rxmode.offloads |= 1418 DEV_RX_OFFLOAD_JUMBO_FRAME; 1419 else 1420 dev->data->dev_conf.rxmode.offloads &= 1421 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 1422 1423 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 1424 1425 /* Set the Max Rx frame length as 'mtu' + 1426 * Maximum Ethernet header length 1427 */ 1428 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, priv->token, 1429 frame_size - RTE_ETHER_CRC_LEN); 1430 if (ret) { 1431 DPAA2_PMD_ERR("Setting the max frame length failed"); 1432 return -1; 1433 } 1434 DPAA2_PMD_INFO("MTU configured for the device: %d", mtu); 1435 return 0; 1436 } 1437 1438 static int 1439 dpaa2_dev_add_mac_addr(struct rte_eth_dev *dev, 1440 struct rte_ether_addr *addr, 1441 __rte_unused uint32_t index, 1442 __rte_unused uint32_t pool) 1443 { 1444 int ret; 1445 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1446 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1447 1448 PMD_INIT_FUNC_TRACE(); 1449 1450 if (dpni == NULL) { 1451 DPAA2_PMD_ERR("dpni is NULL"); 1452 return -1; 1453 } 1454 1455 ret = dpni_add_mac_addr(dpni, CMD_PRI_LOW, priv->token, 1456 addr->addr_bytes, 0, 0, 0); 1457 if (ret) 1458 DPAA2_PMD_ERR( 1459 "error: Adding the MAC ADDR failed: err = %d", ret); 1460 return 0; 1461 } 1462 1463 static void 1464 dpaa2_dev_remove_mac_addr(struct rte_eth_dev *dev, 1465 uint32_t index) 1466 { 1467 int ret; 1468 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1469 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1470 struct rte_eth_dev_data *data = dev->data; 1471 struct rte_ether_addr *macaddr; 1472 1473 PMD_INIT_FUNC_TRACE(); 1474 1475 macaddr = &data->mac_addrs[index]; 1476 1477 if (dpni == NULL) { 1478 DPAA2_PMD_ERR("dpni is NULL"); 1479 return; 1480 } 1481 1482 ret = dpni_remove_mac_addr(dpni, CMD_PRI_LOW, 1483 priv->token, macaddr->addr_bytes); 1484 if (ret) 1485 DPAA2_PMD_ERR( 1486 "error: Removing the MAC ADDR failed: err = %d", ret); 1487 } 1488 1489 static int 1490 dpaa2_dev_set_mac_addr(struct rte_eth_dev *dev, 1491 struct rte_ether_addr *addr) 1492 { 1493 int ret; 1494 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1495 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1496 1497 PMD_INIT_FUNC_TRACE(); 1498 1499 if (dpni == NULL) { 1500 DPAA2_PMD_ERR("dpni is NULL"); 1501 return -EINVAL; 1502 } 1503 1504 ret = dpni_set_primary_mac_addr(dpni, CMD_PRI_LOW, 1505 priv->token, addr->addr_bytes); 1506 1507 if (ret) 1508 DPAA2_PMD_ERR( 1509 "error: Setting the MAC ADDR failed %d", ret); 1510 1511 return ret; 1512 } 1513 1514 static 1515 int dpaa2_dev_stats_get(struct rte_eth_dev *dev, 1516 struct rte_eth_stats *stats) 1517 { 1518 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1519 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1520 int32_t retcode; 1521 uint8_t page0 = 0, page1 = 1, page2 = 2; 1522 union dpni_statistics value; 1523 int i; 1524 struct dpaa2_queue *dpaa2_rxq, *dpaa2_txq; 1525 1526 memset(&value, 0, sizeof(union dpni_statistics)); 1527 1528 PMD_INIT_FUNC_TRACE(); 1529 1530 if (!dpni) { 1531 DPAA2_PMD_ERR("dpni is NULL"); 1532 return -EINVAL; 1533 } 1534 1535 if (!stats) { 1536 DPAA2_PMD_ERR("stats is NULL"); 1537 return -EINVAL; 1538 } 1539 1540 /*Get Counters from page_0*/ 1541 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1542 page0, 0, &value); 1543 if (retcode) 1544 goto err; 1545 1546 stats->ipackets = value.page_0.ingress_all_frames; 1547 stats->ibytes = value.page_0.ingress_all_bytes; 1548 1549 /*Get Counters from page_1*/ 1550 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1551 page1, 0, &value); 1552 if (retcode) 1553 goto err; 1554 1555 stats->opackets = value.page_1.egress_all_frames; 1556 stats->obytes = value.page_1.egress_all_bytes; 1557 1558 /*Get Counters from page_2*/ 1559 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1560 page2, 0, &value); 1561 if (retcode) 1562 goto err; 1563 1564 /* Ingress drop frame count due to configured rules */ 1565 stats->ierrors = value.page_2.ingress_filtered_frames; 1566 /* Ingress drop frame count due to error */ 1567 stats->ierrors += value.page_2.ingress_discarded_frames; 1568 1569 stats->oerrors = value.page_2.egress_discarded_frames; 1570 stats->imissed = value.page_2.ingress_nobuffer_discards; 1571 1572 /* Fill in per queue stats */ 1573 for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) && 1574 (i < priv->nb_rx_queues || i < priv->nb_tx_queues); ++i) { 1575 dpaa2_rxq = (struct dpaa2_queue *)priv->rx_vq[i]; 1576 dpaa2_txq = (struct dpaa2_queue *)priv->tx_vq[i]; 1577 if (dpaa2_rxq) 1578 stats->q_ipackets[i] = dpaa2_rxq->rx_pkts; 1579 if (dpaa2_txq) 1580 stats->q_opackets[i] = dpaa2_txq->tx_pkts; 1581 1582 /* Byte counting is not implemented */ 1583 stats->q_ibytes[i] = 0; 1584 stats->q_obytes[i] = 0; 1585 } 1586 1587 return 0; 1588 1589 err: 1590 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode); 1591 return retcode; 1592 }; 1593 1594 static int 1595 dpaa2_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 1596 unsigned int n) 1597 { 1598 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1599 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1600 int32_t retcode; 1601 union dpni_statistics value[5] = {}; 1602 unsigned int i = 0, num = RTE_DIM(dpaa2_xstats_strings); 1603 1604 if (n < num) 1605 return num; 1606 1607 if (xstats == NULL) 1608 return 0; 1609 1610 /* Get Counters from page_0*/ 1611 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1612 0, 0, &value[0]); 1613 if (retcode) 1614 goto err; 1615 1616 /* Get Counters from page_1*/ 1617 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1618 1, 0, &value[1]); 1619 if (retcode) 1620 goto err; 1621 1622 /* Get Counters from page_2*/ 1623 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1624 2, 0, &value[2]); 1625 if (retcode) 1626 goto err; 1627 1628 for (i = 0; i < priv->max_cgs; i++) { 1629 if (!priv->cgid_in_use[i]) { 1630 /* Get Counters from page_4*/ 1631 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, 1632 priv->token, 1633 4, 0, &value[4]); 1634 if (retcode) 1635 goto err; 1636 break; 1637 } 1638 } 1639 1640 for (i = 0; i < num; i++) { 1641 xstats[i].id = i; 1642 xstats[i].value = value[dpaa2_xstats_strings[i].page_id]. 1643 raw.counter[dpaa2_xstats_strings[i].stats_id]; 1644 } 1645 return i; 1646 err: 1647 DPAA2_PMD_ERR("Error in obtaining extended stats (%d)", retcode); 1648 return retcode; 1649 } 1650 1651 static int 1652 dpaa2_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 1653 struct rte_eth_xstat_name *xstats_names, 1654 unsigned int limit) 1655 { 1656 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings); 1657 1658 if (limit < stat_cnt) 1659 return stat_cnt; 1660 1661 if (xstats_names != NULL) 1662 for (i = 0; i < stat_cnt; i++) 1663 strlcpy(xstats_names[i].name, 1664 dpaa2_xstats_strings[i].name, 1665 sizeof(xstats_names[i].name)); 1666 1667 return stat_cnt; 1668 } 1669 1670 static int 1671 dpaa2_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 1672 uint64_t *values, unsigned int n) 1673 { 1674 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings); 1675 uint64_t values_copy[stat_cnt]; 1676 1677 if (!ids) { 1678 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1679 struct fsl_mc_io *dpni = 1680 (struct fsl_mc_io *)dev->process_private; 1681 int32_t retcode; 1682 union dpni_statistics value[5] = {}; 1683 1684 if (n < stat_cnt) 1685 return stat_cnt; 1686 1687 if (!values) 1688 return 0; 1689 1690 /* Get Counters from page_0*/ 1691 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1692 0, 0, &value[0]); 1693 if (retcode) 1694 return 0; 1695 1696 /* Get Counters from page_1*/ 1697 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1698 1, 0, &value[1]); 1699 if (retcode) 1700 return 0; 1701 1702 /* Get Counters from page_2*/ 1703 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1704 2, 0, &value[2]); 1705 if (retcode) 1706 return 0; 1707 1708 /* Get Counters from page_4*/ 1709 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1710 4, 0, &value[4]); 1711 if (retcode) 1712 return 0; 1713 1714 for (i = 0; i < stat_cnt; i++) { 1715 values[i] = value[dpaa2_xstats_strings[i].page_id]. 1716 raw.counter[dpaa2_xstats_strings[i].stats_id]; 1717 } 1718 return stat_cnt; 1719 } 1720 1721 dpaa2_xstats_get_by_id(dev, NULL, values_copy, stat_cnt); 1722 1723 for (i = 0; i < n; i++) { 1724 if (ids[i] >= stat_cnt) { 1725 DPAA2_PMD_ERR("xstats id value isn't valid"); 1726 return -1; 1727 } 1728 values[i] = values_copy[ids[i]]; 1729 } 1730 return n; 1731 } 1732 1733 static int 1734 dpaa2_xstats_get_names_by_id( 1735 struct rte_eth_dev *dev, 1736 struct rte_eth_xstat_name *xstats_names, 1737 const uint64_t *ids, 1738 unsigned int limit) 1739 { 1740 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings); 1741 struct rte_eth_xstat_name xstats_names_copy[stat_cnt]; 1742 1743 if (!ids) 1744 return dpaa2_xstats_get_names(dev, xstats_names, limit); 1745 1746 dpaa2_xstats_get_names(dev, xstats_names_copy, limit); 1747 1748 for (i = 0; i < limit; i++) { 1749 if (ids[i] >= stat_cnt) { 1750 DPAA2_PMD_ERR("xstats id value isn't valid"); 1751 return -1; 1752 } 1753 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 1754 } 1755 return limit; 1756 } 1757 1758 static int 1759 dpaa2_dev_stats_reset(struct rte_eth_dev *dev) 1760 { 1761 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1762 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1763 int retcode; 1764 int i; 1765 struct dpaa2_queue *dpaa2_q; 1766 1767 PMD_INIT_FUNC_TRACE(); 1768 1769 if (dpni == NULL) { 1770 DPAA2_PMD_ERR("dpni is NULL"); 1771 return -EINVAL; 1772 } 1773 1774 retcode = dpni_reset_statistics(dpni, CMD_PRI_LOW, priv->token); 1775 if (retcode) 1776 goto error; 1777 1778 /* Reset the per queue stats in dpaa2_queue structure */ 1779 for (i = 0; i < priv->nb_rx_queues; i++) { 1780 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i]; 1781 if (dpaa2_q) 1782 dpaa2_q->rx_pkts = 0; 1783 } 1784 1785 for (i = 0; i < priv->nb_tx_queues; i++) { 1786 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; 1787 if (dpaa2_q) 1788 dpaa2_q->tx_pkts = 0; 1789 } 1790 1791 return 0; 1792 1793 error: 1794 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode); 1795 return retcode; 1796 }; 1797 1798 /* return 0 means link status changed, -1 means not changed */ 1799 static int 1800 dpaa2_dev_link_update(struct rte_eth_dev *dev, 1801 int wait_to_complete __rte_unused) 1802 { 1803 int ret; 1804 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1805 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1806 struct rte_eth_link link; 1807 struct dpni_link_state state = {0}; 1808 1809 if (dpni == NULL) { 1810 DPAA2_PMD_ERR("dpni is NULL"); 1811 return 0; 1812 } 1813 1814 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state); 1815 if (ret < 0) { 1816 DPAA2_PMD_DEBUG("error: dpni_get_link_state %d", ret); 1817 return -1; 1818 } 1819 1820 memset(&link, 0, sizeof(struct rte_eth_link)); 1821 link.link_status = state.up; 1822 link.link_speed = state.rate; 1823 1824 if (state.options & DPNI_LINK_OPT_HALF_DUPLEX) 1825 link.link_duplex = ETH_LINK_HALF_DUPLEX; 1826 else 1827 link.link_duplex = ETH_LINK_FULL_DUPLEX; 1828 1829 ret = rte_eth_linkstatus_set(dev, &link); 1830 if (ret == -1) 1831 DPAA2_PMD_DEBUG("No change in status"); 1832 else 1833 DPAA2_PMD_INFO("Port %d Link is %s\n", dev->data->port_id, 1834 link.link_status ? "Up" : "Down"); 1835 1836 return ret; 1837 } 1838 1839 /** 1840 * Toggle the DPNI to enable, if not already enabled. 1841 * This is not strictly PHY up/down - it is more of logical toggling. 1842 */ 1843 static int 1844 dpaa2_dev_set_link_up(struct rte_eth_dev *dev) 1845 { 1846 int ret = -EINVAL; 1847 struct dpaa2_dev_priv *priv; 1848 struct fsl_mc_io *dpni; 1849 int en = 0; 1850 struct dpni_link_state state = {0}; 1851 1852 priv = dev->data->dev_private; 1853 dpni = (struct fsl_mc_io *)dev->process_private; 1854 1855 if (dpni == NULL) { 1856 DPAA2_PMD_ERR("dpni is NULL"); 1857 return ret; 1858 } 1859 1860 /* Check if DPNI is currently enabled */ 1861 ret = dpni_is_enabled(dpni, CMD_PRI_LOW, priv->token, &en); 1862 if (ret) { 1863 /* Unable to obtain dpni status; Not continuing */ 1864 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret); 1865 return -EINVAL; 1866 } 1867 1868 /* Enable link if not already enabled */ 1869 if (!en) { 1870 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token); 1871 if (ret) { 1872 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret); 1873 return -EINVAL; 1874 } 1875 } 1876 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state); 1877 if (ret < 0) { 1878 DPAA2_PMD_DEBUG("Unable to get link state (%d)", ret); 1879 return -1; 1880 } 1881 1882 /* changing tx burst function to start enqueues */ 1883 dev->tx_pkt_burst = dpaa2_dev_tx; 1884 dev->data->dev_link.link_status = state.up; 1885 dev->data->dev_link.link_speed = state.rate; 1886 1887 if (state.up) 1888 DPAA2_PMD_INFO("Port %d Link is Up", dev->data->port_id); 1889 else 1890 DPAA2_PMD_INFO("Port %d Link is Down", dev->data->port_id); 1891 return ret; 1892 } 1893 1894 /** 1895 * Toggle the DPNI to disable, if not already disabled. 1896 * This is not strictly PHY up/down - it is more of logical toggling. 1897 */ 1898 static int 1899 dpaa2_dev_set_link_down(struct rte_eth_dev *dev) 1900 { 1901 int ret = -EINVAL; 1902 struct dpaa2_dev_priv *priv; 1903 struct fsl_mc_io *dpni; 1904 int dpni_enabled = 0; 1905 int retries = 10; 1906 1907 PMD_INIT_FUNC_TRACE(); 1908 1909 priv = dev->data->dev_private; 1910 dpni = (struct fsl_mc_io *)dev->process_private; 1911 1912 if (dpni == NULL) { 1913 DPAA2_PMD_ERR("Device has not yet been configured"); 1914 return ret; 1915 } 1916 1917 /*changing tx burst function to avoid any more enqueues */ 1918 dev->tx_pkt_burst = dummy_dev_tx; 1919 1920 /* Loop while dpni_disable() attempts to drain the egress FQs 1921 * and confirm them back to us. 1922 */ 1923 do { 1924 ret = dpni_disable(dpni, 0, priv->token); 1925 if (ret) { 1926 DPAA2_PMD_ERR("dpni disable failed (%d)", ret); 1927 return ret; 1928 } 1929 ret = dpni_is_enabled(dpni, 0, priv->token, &dpni_enabled); 1930 if (ret) { 1931 DPAA2_PMD_ERR("dpni enable check failed (%d)", ret); 1932 return ret; 1933 } 1934 if (dpni_enabled) 1935 /* Allow the MC some slack */ 1936 rte_delay_us(100 * 1000); 1937 } while (dpni_enabled && --retries); 1938 1939 if (!retries) { 1940 DPAA2_PMD_WARN("Retry count exceeded disabling dpni"); 1941 /* todo- we may have to manually cleanup queues. 1942 */ 1943 } else { 1944 DPAA2_PMD_INFO("Port %d Link DOWN successful", 1945 dev->data->port_id); 1946 } 1947 1948 dev->data->dev_link.link_status = 0; 1949 1950 return ret; 1951 } 1952 1953 static int 1954 dpaa2_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 1955 { 1956 int ret = -EINVAL; 1957 struct dpaa2_dev_priv *priv; 1958 struct fsl_mc_io *dpni; 1959 struct dpni_link_state state = {0}; 1960 1961 PMD_INIT_FUNC_TRACE(); 1962 1963 priv = dev->data->dev_private; 1964 dpni = (struct fsl_mc_io *)dev->process_private; 1965 1966 if (dpni == NULL || fc_conf == NULL) { 1967 DPAA2_PMD_ERR("device not configured"); 1968 return ret; 1969 } 1970 1971 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state); 1972 if (ret) { 1973 DPAA2_PMD_ERR("error: dpni_get_link_state %d", ret); 1974 return ret; 1975 } 1976 1977 memset(fc_conf, 0, sizeof(struct rte_eth_fc_conf)); 1978 if (state.options & DPNI_LINK_OPT_PAUSE) { 1979 /* DPNI_LINK_OPT_PAUSE set 1980 * if ASYM_PAUSE not set, 1981 * RX Side flow control (handle received Pause frame) 1982 * TX side flow control (send Pause frame) 1983 * if ASYM_PAUSE set, 1984 * RX Side flow control (handle received Pause frame) 1985 * No TX side flow control (send Pause frame disabled) 1986 */ 1987 if (!(state.options & DPNI_LINK_OPT_ASYM_PAUSE)) 1988 fc_conf->mode = RTE_FC_FULL; 1989 else 1990 fc_conf->mode = RTE_FC_RX_PAUSE; 1991 } else { 1992 /* DPNI_LINK_OPT_PAUSE not set 1993 * if ASYM_PAUSE set, 1994 * TX side flow control (send Pause frame) 1995 * No RX side flow control (No action on pause frame rx) 1996 * if ASYM_PAUSE not set, 1997 * Flow control disabled 1998 */ 1999 if (state.options & DPNI_LINK_OPT_ASYM_PAUSE) 2000 fc_conf->mode = RTE_FC_TX_PAUSE; 2001 else 2002 fc_conf->mode = RTE_FC_NONE; 2003 } 2004 2005 return ret; 2006 } 2007 2008 static int 2009 dpaa2_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 2010 { 2011 int ret = -EINVAL; 2012 struct dpaa2_dev_priv *priv; 2013 struct fsl_mc_io *dpni; 2014 struct dpni_link_state state = {0}; 2015 struct dpni_link_cfg cfg = {0}; 2016 2017 PMD_INIT_FUNC_TRACE(); 2018 2019 priv = dev->data->dev_private; 2020 dpni = (struct fsl_mc_io *)dev->process_private; 2021 2022 if (dpni == NULL) { 2023 DPAA2_PMD_ERR("dpni is NULL"); 2024 return ret; 2025 } 2026 2027 /* It is necessary to obtain the current state before setting fc_conf 2028 * as MC would return error in case rate, autoneg or duplex values are 2029 * different. 2030 */ 2031 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state); 2032 if (ret) { 2033 DPAA2_PMD_ERR("Unable to get link state (err=%d)", ret); 2034 return -1; 2035 } 2036 2037 /* Disable link before setting configuration */ 2038 dpaa2_dev_set_link_down(dev); 2039 2040 /* Based on fc_conf, update cfg */ 2041 cfg.rate = state.rate; 2042 cfg.options = state.options; 2043 2044 /* update cfg with fc_conf */ 2045 switch (fc_conf->mode) { 2046 case RTE_FC_FULL: 2047 /* Full flow control; 2048 * OPT_PAUSE set, ASYM_PAUSE not set 2049 */ 2050 cfg.options |= DPNI_LINK_OPT_PAUSE; 2051 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE; 2052 break; 2053 case RTE_FC_TX_PAUSE: 2054 /* Enable RX flow control 2055 * OPT_PAUSE not set; 2056 * ASYM_PAUSE set; 2057 */ 2058 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE; 2059 cfg.options &= ~DPNI_LINK_OPT_PAUSE; 2060 break; 2061 case RTE_FC_RX_PAUSE: 2062 /* Enable TX Flow control 2063 * OPT_PAUSE set 2064 * ASYM_PAUSE set 2065 */ 2066 cfg.options |= DPNI_LINK_OPT_PAUSE; 2067 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE; 2068 break; 2069 case RTE_FC_NONE: 2070 /* Disable Flow control 2071 * OPT_PAUSE not set 2072 * ASYM_PAUSE not set 2073 */ 2074 cfg.options &= ~DPNI_LINK_OPT_PAUSE; 2075 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE; 2076 break; 2077 default: 2078 DPAA2_PMD_ERR("Incorrect Flow control flag (%d)", 2079 fc_conf->mode); 2080 return -1; 2081 } 2082 2083 ret = dpni_set_link_cfg(dpni, CMD_PRI_LOW, priv->token, &cfg); 2084 if (ret) 2085 DPAA2_PMD_ERR("Unable to set Link configuration (err=%d)", 2086 ret); 2087 2088 /* Enable link */ 2089 dpaa2_dev_set_link_up(dev); 2090 2091 return ret; 2092 } 2093 2094 static int 2095 dpaa2_dev_rss_hash_update(struct rte_eth_dev *dev, 2096 struct rte_eth_rss_conf *rss_conf) 2097 { 2098 struct rte_eth_dev_data *data = dev->data; 2099 struct dpaa2_dev_priv *priv = data->dev_private; 2100 struct rte_eth_conf *eth_conf = &data->dev_conf; 2101 int ret, tc_index; 2102 2103 PMD_INIT_FUNC_TRACE(); 2104 2105 if (rss_conf->rss_hf) { 2106 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) { 2107 ret = dpaa2_setup_flow_dist(dev, rss_conf->rss_hf, 2108 tc_index); 2109 if (ret) { 2110 DPAA2_PMD_ERR("Unable to set flow dist on tc%d", 2111 tc_index); 2112 return ret; 2113 } 2114 } 2115 } else { 2116 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) { 2117 ret = dpaa2_remove_flow_dist(dev, tc_index); 2118 if (ret) { 2119 DPAA2_PMD_ERR( 2120 "Unable to remove flow dist on tc%d", 2121 tc_index); 2122 return ret; 2123 } 2124 } 2125 } 2126 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf; 2127 return 0; 2128 } 2129 2130 static int 2131 dpaa2_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 2132 struct rte_eth_rss_conf *rss_conf) 2133 { 2134 struct rte_eth_dev_data *data = dev->data; 2135 struct rte_eth_conf *eth_conf = &data->dev_conf; 2136 2137 /* dpaa2 does not support rss_key, so length should be 0*/ 2138 rss_conf->rss_key_len = 0; 2139 rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf; 2140 return 0; 2141 } 2142 2143 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev, 2144 int eth_rx_queue_id, 2145 struct dpaa2_dpcon_dev *dpcon, 2146 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf) 2147 { 2148 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private; 2149 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 2150 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id]; 2151 uint8_t flow_id = dpaa2_ethq->flow_id; 2152 struct dpni_queue cfg; 2153 uint8_t options, priority; 2154 int ret; 2155 2156 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_PARALLEL) 2157 dpaa2_ethq->cb = dpaa2_dev_process_parallel_event; 2158 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) 2159 dpaa2_ethq->cb = dpaa2_dev_process_atomic_event; 2160 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED) 2161 dpaa2_ethq->cb = dpaa2_dev_process_ordered_event; 2162 else 2163 return -EINVAL; 2164 2165 priority = (RTE_EVENT_DEV_PRIORITY_LOWEST / queue_conf->ev.priority) * 2166 (dpcon->num_priorities - 1); 2167 2168 memset(&cfg, 0, sizeof(struct dpni_queue)); 2169 options = DPNI_QUEUE_OPT_DEST; 2170 cfg.destination.type = DPNI_DEST_DPCON; 2171 cfg.destination.id = dpcon->dpcon_id; 2172 cfg.destination.priority = priority; 2173 2174 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) { 2175 options |= DPNI_QUEUE_OPT_HOLD_ACTIVE; 2176 cfg.destination.hold_active = 1; 2177 } 2178 2179 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED && 2180 !eth_priv->en_ordered) { 2181 struct opr_cfg ocfg; 2182 2183 /* Restoration window size = 256 frames */ 2184 ocfg.oprrws = 3; 2185 /* Restoration window size = 512 frames for LX2 */ 2186 if (dpaa2_svr_family == SVR_LX2160A) 2187 ocfg.oprrws = 4; 2188 /* Auto advance NESN window enabled */ 2189 ocfg.oa = 1; 2190 /* Late arrival window size disabled */ 2191 ocfg.olws = 0; 2192 /* ORL resource exhaustaion advance NESN disabled */ 2193 ocfg.oeane = 0; 2194 /* Loose ordering enabled */ 2195 ocfg.oloe = 1; 2196 eth_priv->en_loose_ordered = 1; 2197 /* Strict ordering enabled if explicitly set */ 2198 if (getenv("DPAA2_STRICT_ORDERING_ENABLE")) { 2199 ocfg.oloe = 0; 2200 eth_priv->en_loose_ordered = 0; 2201 } 2202 2203 ret = dpni_set_opr(dpni, CMD_PRI_LOW, eth_priv->token, 2204 dpaa2_ethq->tc_index, flow_id, 2205 OPR_OPT_CREATE, &ocfg); 2206 if (ret) { 2207 DPAA2_PMD_ERR("Error setting opr: ret: %d\n", ret); 2208 return ret; 2209 } 2210 2211 eth_priv->en_ordered = 1; 2212 } 2213 2214 options |= DPNI_QUEUE_OPT_USER_CTX; 2215 cfg.user_context = (size_t)(dpaa2_ethq); 2216 2217 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX, 2218 dpaa2_ethq->tc_index, flow_id, options, &cfg); 2219 if (ret) { 2220 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret); 2221 return ret; 2222 } 2223 2224 memcpy(&dpaa2_ethq->ev, &queue_conf->ev, sizeof(struct rte_event)); 2225 2226 return 0; 2227 } 2228 2229 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev, 2230 int eth_rx_queue_id) 2231 { 2232 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private; 2233 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 2234 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id]; 2235 uint8_t flow_id = dpaa2_ethq->flow_id; 2236 struct dpni_queue cfg; 2237 uint8_t options; 2238 int ret; 2239 2240 memset(&cfg, 0, sizeof(struct dpni_queue)); 2241 options = DPNI_QUEUE_OPT_DEST; 2242 cfg.destination.type = DPNI_DEST_NONE; 2243 2244 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX, 2245 dpaa2_ethq->tc_index, flow_id, options, &cfg); 2246 if (ret) 2247 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret); 2248 2249 return ret; 2250 } 2251 2252 static inline int 2253 dpaa2_dev_verify_filter_ops(enum rte_filter_op filter_op) 2254 { 2255 unsigned int i; 2256 2257 for (i = 0; i < RTE_DIM(dpaa2_supported_filter_ops); i++) { 2258 if (dpaa2_supported_filter_ops[i] == filter_op) 2259 return 0; 2260 } 2261 return -ENOTSUP; 2262 } 2263 2264 static int 2265 dpaa2_dev_flow_ctrl(struct rte_eth_dev *dev, 2266 enum rte_filter_type filter_type, 2267 enum rte_filter_op filter_op, 2268 void *arg) 2269 { 2270 int ret = 0; 2271 2272 if (!dev) 2273 return -ENODEV; 2274 2275 switch (filter_type) { 2276 case RTE_ETH_FILTER_GENERIC: 2277 if (dpaa2_dev_verify_filter_ops(filter_op) < 0) { 2278 ret = -ENOTSUP; 2279 break; 2280 } 2281 *(const void **)arg = &dpaa2_flow_ops; 2282 dpaa2_filter_type |= filter_type; 2283 break; 2284 default: 2285 RTE_LOG(ERR, PMD, "Filter type (%d) not supported", 2286 filter_type); 2287 ret = -ENOTSUP; 2288 break; 2289 } 2290 return ret; 2291 } 2292 2293 static void 2294 dpaa2_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 2295 struct rte_eth_rxq_info *qinfo) 2296 { 2297 struct dpaa2_queue *rxq; 2298 2299 rxq = (struct dpaa2_queue *)dev->data->rx_queues[queue_id]; 2300 2301 qinfo->mp = rxq->mb_pool; 2302 qinfo->scattered_rx = dev->data->scattered_rx; 2303 qinfo->nb_desc = rxq->nb_desc; 2304 2305 qinfo->conf.rx_free_thresh = 1; 2306 qinfo->conf.rx_drop_en = 1; 2307 qinfo->conf.rx_deferred_start = 0; 2308 qinfo->conf.offloads = rxq->offloads; 2309 } 2310 2311 static void 2312 dpaa2_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 2313 struct rte_eth_txq_info *qinfo) 2314 { 2315 struct dpaa2_queue *txq; 2316 2317 txq = dev->data->tx_queues[queue_id]; 2318 2319 qinfo->nb_desc = txq->nb_desc; 2320 qinfo->conf.tx_thresh.pthresh = 0; 2321 qinfo->conf.tx_thresh.hthresh = 0; 2322 qinfo->conf.tx_thresh.wthresh = 0; 2323 2324 qinfo->conf.tx_free_thresh = 0; 2325 qinfo->conf.tx_rs_thresh = 0; 2326 qinfo->conf.offloads = txq->offloads; 2327 qinfo->conf.tx_deferred_start = 0; 2328 } 2329 2330 static struct eth_dev_ops dpaa2_ethdev_ops = { 2331 .dev_configure = dpaa2_eth_dev_configure, 2332 .dev_start = dpaa2_dev_start, 2333 .dev_stop = dpaa2_dev_stop, 2334 .dev_close = dpaa2_dev_close, 2335 .promiscuous_enable = dpaa2_dev_promiscuous_enable, 2336 .promiscuous_disable = dpaa2_dev_promiscuous_disable, 2337 .allmulticast_enable = dpaa2_dev_allmulticast_enable, 2338 .allmulticast_disable = dpaa2_dev_allmulticast_disable, 2339 .dev_set_link_up = dpaa2_dev_set_link_up, 2340 .dev_set_link_down = dpaa2_dev_set_link_down, 2341 .link_update = dpaa2_dev_link_update, 2342 .stats_get = dpaa2_dev_stats_get, 2343 .xstats_get = dpaa2_dev_xstats_get, 2344 .xstats_get_by_id = dpaa2_xstats_get_by_id, 2345 .xstats_get_names_by_id = dpaa2_xstats_get_names_by_id, 2346 .xstats_get_names = dpaa2_xstats_get_names, 2347 .stats_reset = dpaa2_dev_stats_reset, 2348 .xstats_reset = dpaa2_dev_stats_reset, 2349 .fw_version_get = dpaa2_fw_version_get, 2350 .dev_infos_get = dpaa2_dev_info_get, 2351 .dev_supported_ptypes_get = dpaa2_supported_ptypes_get, 2352 .mtu_set = dpaa2_dev_mtu_set, 2353 .vlan_filter_set = dpaa2_vlan_filter_set, 2354 .vlan_offload_set = dpaa2_vlan_offload_set, 2355 .vlan_tpid_set = dpaa2_vlan_tpid_set, 2356 .rx_queue_setup = dpaa2_dev_rx_queue_setup, 2357 .rx_queue_release = dpaa2_dev_rx_queue_release, 2358 .tx_queue_setup = dpaa2_dev_tx_queue_setup, 2359 .tx_queue_release = dpaa2_dev_tx_queue_release, 2360 .rx_burst_mode_get = dpaa2_dev_rx_burst_mode_get, 2361 .tx_burst_mode_get = dpaa2_dev_tx_burst_mode_get, 2362 .flow_ctrl_get = dpaa2_flow_ctrl_get, 2363 .flow_ctrl_set = dpaa2_flow_ctrl_set, 2364 .mac_addr_add = dpaa2_dev_add_mac_addr, 2365 .mac_addr_remove = dpaa2_dev_remove_mac_addr, 2366 .mac_addr_set = dpaa2_dev_set_mac_addr, 2367 .rss_hash_update = dpaa2_dev_rss_hash_update, 2368 .rss_hash_conf_get = dpaa2_dev_rss_hash_conf_get, 2369 .filter_ctrl = dpaa2_dev_flow_ctrl, 2370 .rxq_info_get = dpaa2_rxq_info_get, 2371 .txq_info_get = dpaa2_txq_info_get, 2372 #if defined(RTE_LIBRTE_IEEE1588) 2373 .timesync_enable = dpaa2_timesync_enable, 2374 .timesync_disable = dpaa2_timesync_disable, 2375 .timesync_read_time = dpaa2_timesync_read_time, 2376 .timesync_write_time = dpaa2_timesync_write_time, 2377 .timesync_adjust_time = dpaa2_timesync_adjust_time, 2378 .timesync_read_rx_timestamp = dpaa2_timesync_read_rx_timestamp, 2379 .timesync_read_tx_timestamp = dpaa2_timesync_read_tx_timestamp, 2380 #endif 2381 }; 2382 2383 /* Populate the mac address from physically available (u-boot/firmware) and/or 2384 * one set by higher layers like MC (restool) etc. 2385 * Returns the table of MAC entries (multiple entries) 2386 */ 2387 static int 2388 populate_mac_addr(struct fsl_mc_io *dpni_dev, struct dpaa2_dev_priv *priv, 2389 struct rte_ether_addr *mac_entry) 2390 { 2391 int ret; 2392 struct rte_ether_addr phy_mac, prime_mac; 2393 2394 memset(&phy_mac, 0, sizeof(struct rte_ether_addr)); 2395 memset(&prime_mac, 0, sizeof(struct rte_ether_addr)); 2396 2397 /* Get the physical device MAC address */ 2398 ret = dpni_get_port_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token, 2399 phy_mac.addr_bytes); 2400 if (ret) { 2401 DPAA2_PMD_ERR("DPNI get physical port MAC failed: %d", ret); 2402 goto cleanup; 2403 } 2404 2405 ret = dpni_get_primary_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token, 2406 prime_mac.addr_bytes); 2407 if (ret) { 2408 DPAA2_PMD_ERR("DPNI get Prime port MAC failed: %d", ret); 2409 goto cleanup; 2410 } 2411 2412 /* Now that both MAC have been obtained, do: 2413 * if not_empty_mac(phy) && phy != Prime, overwrite prime with Phy 2414 * and return phy 2415 * If empty_mac(phy), return prime. 2416 * if both are empty, create random MAC, set as prime and return 2417 */ 2418 if (!rte_is_zero_ether_addr(&phy_mac)) { 2419 /* If the addresses are not same, overwrite prime */ 2420 if (!rte_is_same_ether_addr(&phy_mac, &prime_mac)) { 2421 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW, 2422 priv->token, 2423 phy_mac.addr_bytes); 2424 if (ret) { 2425 DPAA2_PMD_ERR("Unable to set MAC Address: %d", 2426 ret); 2427 goto cleanup; 2428 } 2429 memcpy(&prime_mac, &phy_mac, 2430 sizeof(struct rte_ether_addr)); 2431 } 2432 } else if (rte_is_zero_ether_addr(&prime_mac)) { 2433 /* In case phys and prime, both are zero, create random MAC */ 2434 rte_eth_random_addr(prime_mac.addr_bytes); 2435 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW, 2436 priv->token, 2437 prime_mac.addr_bytes); 2438 if (ret) { 2439 DPAA2_PMD_ERR("Unable to set MAC Address: %d", ret); 2440 goto cleanup; 2441 } 2442 } 2443 2444 /* prime_mac the final MAC address */ 2445 memcpy(mac_entry, &prime_mac, sizeof(struct rte_ether_addr)); 2446 return 0; 2447 2448 cleanup: 2449 return -1; 2450 } 2451 2452 static int 2453 check_devargs_handler(__rte_unused const char *key, const char *value, 2454 __rte_unused void *opaque) 2455 { 2456 if (strcmp(value, "1")) 2457 return -1; 2458 2459 return 0; 2460 } 2461 2462 static int 2463 dpaa2_get_devargs(struct rte_devargs *devargs, const char *key) 2464 { 2465 struct rte_kvargs *kvlist; 2466 2467 if (!devargs) 2468 return 0; 2469 2470 kvlist = rte_kvargs_parse(devargs->args, NULL); 2471 if (!kvlist) 2472 return 0; 2473 2474 if (!rte_kvargs_count(kvlist, key)) { 2475 rte_kvargs_free(kvlist); 2476 return 0; 2477 } 2478 2479 if (rte_kvargs_process(kvlist, key, 2480 check_devargs_handler, NULL) < 0) { 2481 rte_kvargs_free(kvlist); 2482 return 0; 2483 } 2484 rte_kvargs_free(kvlist); 2485 2486 return 1; 2487 } 2488 2489 static int 2490 dpaa2_dev_init(struct rte_eth_dev *eth_dev) 2491 { 2492 struct rte_device *dev = eth_dev->device; 2493 struct rte_dpaa2_device *dpaa2_dev; 2494 struct fsl_mc_io *dpni_dev; 2495 struct dpni_attr attr; 2496 struct dpaa2_dev_priv *priv = eth_dev->data->dev_private; 2497 struct dpni_buffer_layout layout; 2498 int ret, hw_id, i; 2499 2500 PMD_INIT_FUNC_TRACE(); 2501 2502 dpni_dev = rte_malloc(NULL, sizeof(struct fsl_mc_io), 0); 2503 if (!dpni_dev) { 2504 DPAA2_PMD_ERR("Memory allocation failed for dpni device"); 2505 return -1; 2506 } 2507 dpni_dev->regs = dpaa2_get_mcp_ptr(MC_PORTAL_INDEX); 2508 eth_dev->process_private = (void *)dpni_dev; 2509 2510 /* For secondary processes, the primary has done all the work */ 2511 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2512 /* In case of secondary, only burst and ops API need to be 2513 * plugged. 2514 */ 2515 eth_dev->dev_ops = &dpaa2_ethdev_ops; 2516 eth_dev->rx_queue_count = dpaa2_dev_rx_queue_count; 2517 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) 2518 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx; 2519 else if (dpaa2_get_devargs(dev->devargs, 2520 DRIVER_NO_PREFETCH_MODE)) 2521 eth_dev->rx_pkt_burst = dpaa2_dev_rx; 2522 else 2523 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx; 2524 eth_dev->tx_pkt_burst = dpaa2_dev_tx; 2525 return 0; 2526 } 2527 2528 dpaa2_dev = container_of(dev, struct rte_dpaa2_device, device); 2529 2530 hw_id = dpaa2_dev->object_id; 2531 ret = dpni_open(dpni_dev, CMD_PRI_LOW, hw_id, &priv->token); 2532 if (ret) { 2533 DPAA2_PMD_ERR( 2534 "Failure in opening dpni@%d with err code %d", 2535 hw_id, ret); 2536 rte_free(dpni_dev); 2537 return -1; 2538 } 2539 2540 /* Clean the device first */ 2541 ret = dpni_reset(dpni_dev, CMD_PRI_LOW, priv->token); 2542 if (ret) { 2543 DPAA2_PMD_ERR("Failure cleaning dpni@%d with err code %d", 2544 hw_id, ret); 2545 goto init_err; 2546 } 2547 2548 ret = dpni_get_attributes(dpni_dev, CMD_PRI_LOW, priv->token, &attr); 2549 if (ret) { 2550 DPAA2_PMD_ERR( 2551 "Failure in get dpni@%d attribute, err code %d", 2552 hw_id, ret); 2553 goto init_err; 2554 } 2555 2556 priv->num_rx_tc = attr.num_rx_tcs; 2557 priv->qos_entries = attr.qos_entries; 2558 priv->fs_entries = attr.fs_entries; 2559 priv->dist_queues = attr.num_queues; 2560 2561 /* only if the custom CG is enabled */ 2562 if (attr.options & DPNI_OPT_CUSTOM_CG) 2563 priv->max_cgs = attr.num_cgs; 2564 else 2565 priv->max_cgs = 0; 2566 2567 for (i = 0; i < priv->max_cgs; i++) 2568 priv->cgid_in_use[i] = 0; 2569 2570 for (i = 0; i < attr.num_rx_tcs; i++) 2571 priv->nb_rx_queues += attr.num_queues; 2572 2573 /* Using number of TX queues as number of TX TCs */ 2574 priv->nb_tx_queues = attr.num_tx_tcs; 2575 2576 DPAA2_PMD_DEBUG("RX-TC= %d, rx_queues= %d, tx_queues=%d, max_cgs=%d", 2577 priv->num_rx_tc, priv->nb_rx_queues, 2578 priv->nb_tx_queues, priv->max_cgs); 2579 2580 priv->hw = dpni_dev; 2581 priv->hw_id = hw_id; 2582 priv->options = attr.options; 2583 priv->max_mac_filters = attr.mac_filter_entries; 2584 priv->max_vlan_filters = attr.vlan_filter_entries; 2585 priv->flags = 0; 2586 #if defined(RTE_LIBRTE_IEEE1588) 2587 priv->tx_conf_en = 1; 2588 #else 2589 priv->tx_conf_en = 0; 2590 #endif 2591 2592 /* Allocate memory for hardware structure for queues */ 2593 ret = dpaa2_alloc_rx_tx_queues(eth_dev); 2594 if (ret) { 2595 DPAA2_PMD_ERR("Queue allocation Failed"); 2596 goto init_err; 2597 } 2598 2599 /* Allocate memory for storing MAC addresses. 2600 * Table of mac_filter_entries size is allocated so that RTE ether lib 2601 * can add MAC entries when rte_eth_dev_mac_addr_add is called. 2602 */ 2603 eth_dev->data->mac_addrs = rte_zmalloc("dpni", 2604 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries, 0); 2605 if (eth_dev->data->mac_addrs == NULL) { 2606 DPAA2_PMD_ERR( 2607 "Failed to allocate %d bytes needed to store MAC addresses", 2608 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries); 2609 ret = -ENOMEM; 2610 goto init_err; 2611 } 2612 2613 ret = populate_mac_addr(dpni_dev, priv, ð_dev->data->mac_addrs[0]); 2614 if (ret) { 2615 DPAA2_PMD_ERR("Unable to fetch MAC Address for device"); 2616 rte_free(eth_dev->data->mac_addrs); 2617 eth_dev->data->mac_addrs = NULL; 2618 goto init_err; 2619 } 2620 2621 /* ... tx buffer layout ... */ 2622 memset(&layout, 0, sizeof(struct dpni_buffer_layout)); 2623 if (priv->tx_conf_en) { 2624 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS | 2625 DPNI_BUF_LAYOUT_OPT_TIMESTAMP; 2626 layout.pass_timestamp = true; 2627 } else { 2628 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS; 2629 } 2630 layout.pass_frame_status = 1; 2631 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token, 2632 DPNI_QUEUE_TX, &layout); 2633 if (ret) { 2634 DPAA2_PMD_ERR("Error (%d) in setting tx buffer layout", ret); 2635 goto init_err; 2636 } 2637 2638 /* ... tx-conf and error buffer layout ... */ 2639 memset(&layout, 0, sizeof(struct dpni_buffer_layout)); 2640 if (priv->tx_conf_en) { 2641 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS | 2642 DPNI_BUF_LAYOUT_OPT_TIMESTAMP; 2643 layout.pass_timestamp = true; 2644 } else { 2645 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS; 2646 } 2647 layout.pass_frame_status = 1; 2648 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token, 2649 DPNI_QUEUE_TX_CONFIRM, &layout); 2650 if (ret) { 2651 DPAA2_PMD_ERR("Error (%d) in setting tx-conf buffer layout", 2652 ret); 2653 goto init_err; 2654 } 2655 2656 eth_dev->dev_ops = &dpaa2_ethdev_ops; 2657 2658 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) { 2659 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx; 2660 DPAA2_PMD_INFO("Loopback mode"); 2661 } else if (dpaa2_get_devargs(dev->devargs, DRIVER_NO_PREFETCH_MODE)) { 2662 eth_dev->rx_pkt_burst = dpaa2_dev_rx; 2663 DPAA2_PMD_INFO("No Prefetch mode"); 2664 } else { 2665 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx; 2666 } 2667 eth_dev->tx_pkt_burst = dpaa2_dev_tx; 2668 2669 /*Init fields w.r.t. classficaition*/ 2670 memset(&priv->extract.qos_key_extract, 0, 2671 sizeof(struct dpaa2_key_extract)); 2672 priv->extract.qos_extract_param = (size_t)rte_malloc(NULL, 256, 64); 2673 if (!priv->extract.qos_extract_param) { 2674 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow " 2675 " classificaiton ", ret); 2676 goto init_err; 2677 } 2678 priv->extract.qos_key_extract.key_info.ipv4_src_offset = 2679 IP_ADDRESS_OFFSET_INVALID; 2680 priv->extract.qos_key_extract.key_info.ipv4_dst_offset = 2681 IP_ADDRESS_OFFSET_INVALID; 2682 priv->extract.qos_key_extract.key_info.ipv6_src_offset = 2683 IP_ADDRESS_OFFSET_INVALID; 2684 priv->extract.qos_key_extract.key_info.ipv6_dst_offset = 2685 IP_ADDRESS_OFFSET_INVALID; 2686 2687 for (i = 0; i < MAX_TCS; i++) { 2688 memset(&priv->extract.tc_key_extract[i], 0, 2689 sizeof(struct dpaa2_key_extract)); 2690 priv->extract.tc_extract_param[i] = 2691 (size_t)rte_malloc(NULL, 256, 64); 2692 if (!priv->extract.tc_extract_param[i]) { 2693 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow classificaiton", 2694 ret); 2695 goto init_err; 2696 } 2697 priv->extract.tc_key_extract[i].key_info.ipv4_src_offset = 2698 IP_ADDRESS_OFFSET_INVALID; 2699 priv->extract.tc_key_extract[i].key_info.ipv4_dst_offset = 2700 IP_ADDRESS_OFFSET_INVALID; 2701 priv->extract.tc_key_extract[i].key_info.ipv6_src_offset = 2702 IP_ADDRESS_OFFSET_INVALID; 2703 priv->extract.tc_key_extract[i].key_info.ipv6_dst_offset = 2704 IP_ADDRESS_OFFSET_INVALID; 2705 } 2706 2707 ret = dpni_set_max_frame_length(dpni_dev, CMD_PRI_LOW, priv->token, 2708 RTE_ETHER_MAX_LEN - RTE_ETHER_CRC_LEN 2709 + VLAN_TAG_SIZE); 2710 if (ret) { 2711 DPAA2_PMD_ERR("Unable to set mtu. check config"); 2712 goto init_err; 2713 } 2714 2715 /*TODO To enable soft parser support DPAA2 driver needs to integrate 2716 * with external entity to receive byte code for software sequence 2717 * and same will be offload to the H/W using MC interface. 2718 * Currently it is assumed that DPAA2 driver has byte code by some 2719 * mean and same if offloaded to H/W. 2720 */ 2721 if (getenv("DPAA2_ENABLE_SOFT_PARSER")) { 2722 WRIOP_SS_INITIALIZER(priv); 2723 ret = dpaa2_eth_load_wriop_soft_parser(priv, DPNI_SS_INGRESS); 2724 if (ret < 0) { 2725 DPAA2_PMD_ERR(" Error(%d) in loading softparser\n", 2726 ret); 2727 return ret; 2728 } 2729 2730 ret = dpaa2_eth_enable_wriop_soft_parser(priv, 2731 DPNI_SS_INGRESS); 2732 if (ret < 0) { 2733 DPAA2_PMD_ERR(" Error(%d) in enabling softparser\n", 2734 ret); 2735 return ret; 2736 } 2737 } 2738 RTE_LOG(INFO, PMD, "%s: netdev created\n", eth_dev->data->name); 2739 return 0; 2740 init_err: 2741 dpaa2_dev_close(eth_dev); 2742 2743 return ret; 2744 } 2745 2746 static int 2747 rte_dpaa2_probe(struct rte_dpaa2_driver *dpaa2_drv, 2748 struct rte_dpaa2_device *dpaa2_dev) 2749 { 2750 struct rte_eth_dev *eth_dev; 2751 struct dpaa2_dev_priv *dev_priv; 2752 int diag; 2753 2754 if ((DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) > 2755 RTE_PKTMBUF_HEADROOM) { 2756 DPAA2_PMD_ERR( 2757 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA2 Annotation req(%d)", 2758 RTE_PKTMBUF_HEADROOM, 2759 DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE); 2760 2761 return -1; 2762 } 2763 2764 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 2765 eth_dev = rte_eth_dev_allocate(dpaa2_dev->device.name); 2766 if (!eth_dev) 2767 return -ENODEV; 2768 dev_priv = rte_zmalloc("ethdev private structure", 2769 sizeof(struct dpaa2_dev_priv), 2770 RTE_CACHE_LINE_SIZE); 2771 if (dev_priv == NULL) { 2772 DPAA2_PMD_CRIT( 2773 "Unable to allocate memory for private data"); 2774 rte_eth_dev_release_port(eth_dev); 2775 return -ENOMEM; 2776 } 2777 eth_dev->data->dev_private = (void *)dev_priv; 2778 /* Store a pointer to eth_dev in dev_private */ 2779 dev_priv->eth_dev = eth_dev; 2780 dev_priv->tx_conf_en = 0; 2781 } else { 2782 eth_dev = rte_eth_dev_attach_secondary(dpaa2_dev->device.name); 2783 if (!eth_dev) { 2784 DPAA2_PMD_DEBUG("returning enodev"); 2785 return -ENODEV; 2786 } 2787 } 2788 2789 eth_dev->device = &dpaa2_dev->device; 2790 2791 dpaa2_dev->eth_dev = eth_dev; 2792 eth_dev->data->rx_mbuf_alloc_failed = 0; 2793 2794 if (dpaa2_drv->drv_flags & RTE_DPAA2_DRV_INTR_LSC) 2795 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC; 2796 2797 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 2798 2799 /* Invoke PMD device initialization function */ 2800 diag = dpaa2_dev_init(eth_dev); 2801 if (diag == 0) { 2802 rte_eth_dev_probing_finish(eth_dev); 2803 return 0; 2804 } 2805 2806 rte_eth_dev_release_port(eth_dev); 2807 return diag; 2808 } 2809 2810 static int 2811 rte_dpaa2_remove(struct rte_dpaa2_device *dpaa2_dev) 2812 { 2813 struct rte_eth_dev *eth_dev; 2814 int ret; 2815 2816 eth_dev = dpaa2_dev->eth_dev; 2817 dpaa2_dev_close(eth_dev); 2818 ret = rte_eth_dev_release_port(eth_dev); 2819 2820 return ret; 2821 } 2822 2823 static struct rte_dpaa2_driver rte_dpaa2_pmd = { 2824 .drv_flags = RTE_DPAA2_DRV_INTR_LSC | RTE_DPAA2_DRV_IOVA_AS_VA, 2825 .drv_type = DPAA2_ETH, 2826 .probe = rte_dpaa2_probe, 2827 .remove = rte_dpaa2_remove, 2828 }; 2829 2830 RTE_PMD_REGISTER_DPAA2(net_dpaa2, rte_dpaa2_pmd); 2831 RTE_PMD_REGISTER_PARAM_STRING(net_dpaa2, 2832 DRIVER_LOOPBACK_MODE "=<int> " 2833 DRIVER_NO_PREFETCH_MODE "=<int>"); 2834 RTE_LOG_REGISTER(dpaa2_logtype_pmd, pmd.net.dpaa2, NOTICE); 2835