1 /* * SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved. 4 * Copyright 2016-2020 NXP 5 * 6 */ 7 8 #include <time.h> 9 #include <net/if.h> 10 11 #include <rte_mbuf.h> 12 #include <rte_ethdev_driver.h> 13 #include <rte_malloc.h> 14 #include <rte_memcpy.h> 15 #include <rte_string_fns.h> 16 #include <rte_cycles.h> 17 #include <rte_kvargs.h> 18 #include <rte_dev.h> 19 #include <rte_fslmc.h> 20 #include <rte_flow_driver.h> 21 22 #include "dpaa2_pmd_logs.h" 23 #include <fslmc_vfio.h> 24 #include <dpaa2_hw_pvt.h> 25 #include <dpaa2_hw_mempool.h> 26 #include <dpaa2_hw_dpio.h> 27 #include <mc/fsl_dpmng.h> 28 #include "dpaa2_ethdev.h" 29 #include "dpaa2_sparser.h" 30 #include <fsl_qbman_debug.h> 31 32 #define DRIVER_LOOPBACK_MODE "drv_loopback" 33 #define DRIVER_NO_PREFETCH_MODE "drv_no_prefetch" 34 35 /* Supported Rx offloads */ 36 static uint64_t dev_rx_offloads_sup = 37 DEV_RX_OFFLOAD_CHECKSUM | 38 DEV_RX_OFFLOAD_SCTP_CKSUM | 39 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 40 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | 41 DEV_RX_OFFLOAD_VLAN_STRIP | 42 DEV_RX_OFFLOAD_VLAN_FILTER | 43 DEV_RX_OFFLOAD_JUMBO_FRAME | 44 DEV_RX_OFFLOAD_TIMESTAMP; 45 46 /* Rx offloads which cannot be disabled */ 47 static uint64_t dev_rx_offloads_nodis = 48 DEV_RX_OFFLOAD_RSS_HASH | 49 DEV_RX_OFFLOAD_SCATTER; 50 51 /* Supported Tx offloads */ 52 static uint64_t dev_tx_offloads_sup = 53 DEV_TX_OFFLOAD_VLAN_INSERT | 54 DEV_TX_OFFLOAD_IPV4_CKSUM | 55 DEV_TX_OFFLOAD_UDP_CKSUM | 56 DEV_TX_OFFLOAD_TCP_CKSUM | 57 DEV_TX_OFFLOAD_SCTP_CKSUM | 58 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 59 DEV_TX_OFFLOAD_MT_LOCKFREE | 60 DEV_TX_OFFLOAD_MBUF_FAST_FREE; 61 62 /* Tx offloads which cannot be disabled */ 63 static uint64_t dev_tx_offloads_nodis = 64 DEV_TX_OFFLOAD_MULTI_SEGS; 65 66 /* enable timestamp in mbuf */ 67 bool dpaa2_enable_ts[RTE_MAX_ETHPORTS]; 68 69 struct rte_dpaa2_xstats_name_off { 70 char name[RTE_ETH_XSTATS_NAME_SIZE]; 71 uint8_t page_id; /* dpni statistics page id */ 72 uint8_t stats_id; /* stats id in the given page */ 73 }; 74 75 static const struct rte_dpaa2_xstats_name_off dpaa2_xstats_strings[] = { 76 {"ingress_multicast_frames", 0, 2}, 77 {"ingress_multicast_bytes", 0, 3}, 78 {"ingress_broadcast_frames", 0, 4}, 79 {"ingress_broadcast_bytes", 0, 5}, 80 {"egress_multicast_frames", 1, 2}, 81 {"egress_multicast_bytes", 1, 3}, 82 {"egress_broadcast_frames", 1, 4}, 83 {"egress_broadcast_bytes", 1, 5}, 84 {"ingress_filtered_frames", 2, 0}, 85 {"ingress_discarded_frames", 2, 1}, 86 {"ingress_nobuffer_discards", 2, 2}, 87 {"egress_discarded_frames", 2, 3}, 88 {"egress_confirmed_frames", 2, 4}, 89 {"cgr_reject_frames", 4, 0}, 90 {"cgr_reject_bytes", 4, 1}, 91 }; 92 93 static const enum rte_filter_op dpaa2_supported_filter_ops[] = { 94 RTE_ETH_FILTER_ADD, 95 RTE_ETH_FILTER_DELETE, 96 RTE_ETH_FILTER_UPDATE, 97 RTE_ETH_FILTER_FLUSH, 98 RTE_ETH_FILTER_GET 99 }; 100 101 static struct rte_dpaa2_driver rte_dpaa2_pmd; 102 static int dpaa2_dev_uninit(struct rte_eth_dev *eth_dev); 103 static int dpaa2_dev_link_update(struct rte_eth_dev *dev, 104 int wait_to_complete); 105 static int dpaa2_dev_set_link_up(struct rte_eth_dev *dev); 106 static int dpaa2_dev_set_link_down(struct rte_eth_dev *dev); 107 static int dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 108 109 static int 110 dpaa2_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 111 { 112 int ret; 113 struct dpaa2_dev_priv *priv = dev->data->dev_private; 114 struct fsl_mc_io *dpni = dev->process_private; 115 116 PMD_INIT_FUNC_TRACE(); 117 118 if (dpni == NULL) { 119 DPAA2_PMD_ERR("dpni is NULL"); 120 return -1; 121 } 122 123 if (on) 124 ret = dpni_add_vlan_id(dpni, CMD_PRI_LOW, priv->token, 125 vlan_id, 0, 0, 0); 126 else 127 ret = dpni_remove_vlan_id(dpni, CMD_PRI_LOW, 128 priv->token, vlan_id); 129 130 if (ret < 0) 131 DPAA2_PMD_ERR("ret = %d Unable to add/rem vlan %d hwid =%d", 132 ret, vlan_id, priv->hw_id); 133 134 return ret; 135 } 136 137 static int 138 dpaa2_vlan_offload_set(struct rte_eth_dev *dev, int mask) 139 { 140 struct dpaa2_dev_priv *priv = dev->data->dev_private; 141 struct fsl_mc_io *dpni = dev->process_private; 142 int ret = 0; 143 144 PMD_INIT_FUNC_TRACE(); 145 146 if (mask & ETH_VLAN_FILTER_MASK) { 147 /* VLAN Filter not avaialble */ 148 if (!priv->max_vlan_filters) { 149 DPAA2_PMD_INFO("VLAN filter not available"); 150 return -ENOTSUP; 151 } 152 153 if (dev->data->dev_conf.rxmode.offloads & 154 DEV_RX_OFFLOAD_VLAN_FILTER) 155 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW, 156 priv->token, true); 157 else 158 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW, 159 priv->token, false); 160 if (ret < 0) 161 DPAA2_PMD_INFO("Unable to set vlan filter = %d", ret); 162 } 163 164 return ret; 165 } 166 167 static int 168 dpaa2_vlan_tpid_set(struct rte_eth_dev *dev, 169 enum rte_vlan_type vlan_type __rte_unused, 170 uint16_t tpid) 171 { 172 struct dpaa2_dev_priv *priv = dev->data->dev_private; 173 struct fsl_mc_io *dpni = dev->process_private; 174 int ret = -ENOTSUP; 175 176 PMD_INIT_FUNC_TRACE(); 177 178 /* nothing to be done for standard vlan tpids */ 179 if (tpid == 0x8100 || tpid == 0x88A8) 180 return 0; 181 182 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW, 183 priv->token, tpid); 184 if (ret < 0) 185 DPAA2_PMD_INFO("Unable to set vlan tpid = %d", ret); 186 /* if already configured tpids, remove them first */ 187 if (ret == -EBUSY) { 188 struct dpni_custom_tpid_cfg tpid_list = {0}; 189 190 ret = dpni_get_custom_tpid(dpni, CMD_PRI_LOW, 191 priv->token, &tpid_list); 192 if (ret < 0) 193 goto fail; 194 ret = dpni_remove_custom_tpid(dpni, CMD_PRI_LOW, 195 priv->token, tpid_list.tpid1); 196 if (ret < 0) 197 goto fail; 198 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW, 199 priv->token, tpid); 200 } 201 fail: 202 return ret; 203 } 204 205 static int 206 dpaa2_fw_version_get(struct rte_eth_dev *dev, 207 char *fw_version, 208 size_t fw_size) 209 { 210 int ret; 211 struct fsl_mc_io *dpni = dev->process_private; 212 struct mc_soc_version mc_plat_info = {0}; 213 struct mc_version mc_ver_info = {0}; 214 215 PMD_INIT_FUNC_TRACE(); 216 217 if (mc_get_soc_version(dpni, CMD_PRI_LOW, &mc_plat_info)) 218 DPAA2_PMD_WARN("\tmc_get_soc_version failed"); 219 220 if (mc_get_version(dpni, CMD_PRI_LOW, &mc_ver_info)) 221 DPAA2_PMD_WARN("\tmc_get_version failed"); 222 223 ret = snprintf(fw_version, fw_size, 224 "%x-%d.%d.%d", 225 mc_plat_info.svr, 226 mc_ver_info.major, 227 mc_ver_info.minor, 228 mc_ver_info.revision); 229 230 ret += 1; /* add the size of '\0' */ 231 if (fw_size < (uint32_t)ret) 232 return ret; 233 else 234 return 0; 235 } 236 237 static int 238 dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 239 { 240 struct dpaa2_dev_priv *priv = dev->data->dev_private; 241 242 PMD_INIT_FUNC_TRACE(); 243 244 dev_info->max_mac_addrs = priv->max_mac_filters; 245 dev_info->max_rx_pktlen = DPAA2_MAX_RX_PKT_LEN; 246 dev_info->min_rx_bufsize = DPAA2_MIN_RX_BUF_SIZE; 247 dev_info->max_rx_queues = (uint16_t)priv->nb_rx_queues; 248 dev_info->max_tx_queues = (uint16_t)priv->nb_tx_queues; 249 dev_info->rx_offload_capa = dev_rx_offloads_sup | 250 dev_rx_offloads_nodis; 251 dev_info->tx_offload_capa = dev_tx_offloads_sup | 252 dev_tx_offloads_nodis; 253 dev_info->speed_capa = ETH_LINK_SPEED_1G | 254 ETH_LINK_SPEED_2_5G | 255 ETH_LINK_SPEED_10G; 256 257 dev_info->max_hash_mac_addrs = 0; 258 dev_info->max_vfs = 0; 259 dev_info->max_vmdq_pools = ETH_16_POOLS; 260 dev_info->flow_type_rss_offloads = DPAA2_RSS_OFFLOAD_ALL; 261 262 dev_info->default_rxportconf.burst_size = dpaa2_dqrr_size; 263 /* same is rx size for best perf */ 264 dev_info->default_txportconf.burst_size = dpaa2_dqrr_size; 265 266 dev_info->default_rxportconf.nb_queues = 1; 267 dev_info->default_txportconf.nb_queues = 1; 268 dev_info->default_txportconf.ring_size = CONG_ENTER_TX_THRESHOLD; 269 dev_info->default_rxportconf.ring_size = DPAA2_RX_DEFAULT_NBDESC; 270 271 if (dpaa2_svr_family == SVR_LX2160A) { 272 dev_info->speed_capa |= ETH_LINK_SPEED_25G | 273 ETH_LINK_SPEED_40G | 274 ETH_LINK_SPEED_50G | 275 ETH_LINK_SPEED_100G; 276 } 277 278 return 0; 279 } 280 281 static int 282 dpaa2_dev_rx_burst_mode_get(struct rte_eth_dev *dev, 283 __rte_unused uint16_t queue_id, 284 struct rte_eth_burst_mode *mode) 285 { 286 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 287 int ret = -EINVAL; 288 unsigned int i; 289 const struct burst_info { 290 uint64_t flags; 291 const char *output; 292 } rx_offload_map[] = { 293 {DEV_RX_OFFLOAD_CHECKSUM, " Checksum,"}, 294 {DEV_RX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"}, 295 {DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"}, 296 {DEV_RX_OFFLOAD_OUTER_UDP_CKSUM, " Outer UDP csum,"}, 297 {DEV_RX_OFFLOAD_VLAN_STRIP, " VLAN strip,"}, 298 {DEV_RX_OFFLOAD_VLAN_FILTER, " VLAN filter,"}, 299 {DEV_RX_OFFLOAD_JUMBO_FRAME, " Jumbo frame,"}, 300 {DEV_RX_OFFLOAD_TIMESTAMP, " Timestamp,"}, 301 {DEV_RX_OFFLOAD_RSS_HASH, " RSS,"}, 302 {DEV_RX_OFFLOAD_SCATTER, " Scattered,"} 303 }; 304 305 /* Update Rx offload info */ 306 for (i = 0; i < RTE_DIM(rx_offload_map); i++) { 307 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) { 308 snprintf(mode->info, sizeof(mode->info), "%s", 309 rx_offload_map[i].output); 310 ret = 0; 311 break; 312 } 313 } 314 return ret; 315 } 316 317 static int 318 dpaa2_dev_tx_burst_mode_get(struct rte_eth_dev *dev, 319 __rte_unused uint16_t queue_id, 320 struct rte_eth_burst_mode *mode) 321 { 322 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 323 int ret = -EINVAL; 324 unsigned int i; 325 const struct burst_info { 326 uint64_t flags; 327 const char *output; 328 } tx_offload_map[] = { 329 {DEV_TX_OFFLOAD_VLAN_INSERT, " VLAN Insert,"}, 330 {DEV_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"}, 331 {DEV_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"}, 332 {DEV_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"}, 333 {DEV_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"}, 334 {DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"}, 335 {DEV_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"}, 336 {DEV_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"}, 337 {DEV_TX_OFFLOAD_MULTI_SEGS, " Scattered,"} 338 }; 339 340 /* Update Tx offload info */ 341 for (i = 0; i < RTE_DIM(tx_offload_map); i++) { 342 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) { 343 snprintf(mode->info, sizeof(mode->info), "%s", 344 tx_offload_map[i].output); 345 ret = 0; 346 break; 347 } 348 } 349 return ret; 350 } 351 352 static int 353 dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev) 354 { 355 struct dpaa2_dev_priv *priv = dev->data->dev_private; 356 uint16_t dist_idx; 357 uint32_t vq_id; 358 uint8_t num_rxqueue_per_tc; 359 struct dpaa2_queue *mc_q, *mcq; 360 uint32_t tot_queues; 361 int i; 362 struct dpaa2_queue *dpaa2_q; 363 364 PMD_INIT_FUNC_TRACE(); 365 366 num_rxqueue_per_tc = (priv->nb_rx_queues / priv->num_rx_tc); 367 if (priv->tx_conf_en) 368 tot_queues = priv->nb_rx_queues + 2 * priv->nb_tx_queues; 369 else 370 tot_queues = priv->nb_rx_queues + priv->nb_tx_queues; 371 mc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues, 372 RTE_CACHE_LINE_SIZE); 373 if (!mc_q) { 374 DPAA2_PMD_ERR("Memory allocation failed for rx/tx queues"); 375 return -1; 376 } 377 378 for (i = 0; i < priv->nb_rx_queues; i++) { 379 mc_q->eth_data = dev->data; 380 priv->rx_vq[i] = mc_q++; 381 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i]; 382 dpaa2_q->q_storage = rte_malloc("dq_storage", 383 sizeof(struct queue_storage_info_t), 384 RTE_CACHE_LINE_SIZE); 385 if (!dpaa2_q->q_storage) 386 goto fail; 387 388 memset(dpaa2_q->q_storage, 0, 389 sizeof(struct queue_storage_info_t)); 390 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage)) 391 goto fail; 392 } 393 394 for (i = 0; i < priv->nb_tx_queues; i++) { 395 mc_q->eth_data = dev->data; 396 mc_q->flow_id = 0xffff; 397 priv->tx_vq[i] = mc_q++; 398 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; 399 dpaa2_q->cscn = rte_malloc(NULL, 400 sizeof(struct qbman_result), 16); 401 if (!dpaa2_q->cscn) 402 goto fail_tx; 403 } 404 405 if (priv->tx_conf_en) { 406 /*Setup tx confirmation queues*/ 407 for (i = 0; i < priv->nb_tx_queues; i++) { 408 mc_q->eth_data = dev->data; 409 mc_q->tc_index = i; 410 mc_q->flow_id = 0; 411 priv->tx_conf_vq[i] = mc_q++; 412 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i]; 413 dpaa2_q->q_storage = 414 rte_malloc("dq_storage", 415 sizeof(struct queue_storage_info_t), 416 RTE_CACHE_LINE_SIZE); 417 if (!dpaa2_q->q_storage) 418 goto fail_tx_conf; 419 420 memset(dpaa2_q->q_storage, 0, 421 sizeof(struct queue_storage_info_t)); 422 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage)) 423 goto fail_tx_conf; 424 } 425 } 426 427 vq_id = 0; 428 for (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) { 429 mcq = (struct dpaa2_queue *)priv->rx_vq[vq_id]; 430 mcq->tc_index = dist_idx / num_rxqueue_per_tc; 431 mcq->flow_id = dist_idx % num_rxqueue_per_tc; 432 vq_id++; 433 } 434 435 return 0; 436 fail_tx_conf: 437 i -= 1; 438 while (i >= 0) { 439 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i]; 440 rte_free(dpaa2_q->q_storage); 441 priv->tx_conf_vq[i--] = NULL; 442 } 443 i = priv->nb_tx_queues; 444 fail_tx: 445 i -= 1; 446 while (i >= 0) { 447 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; 448 rte_free(dpaa2_q->cscn); 449 priv->tx_vq[i--] = NULL; 450 } 451 i = priv->nb_rx_queues; 452 fail: 453 i -= 1; 454 mc_q = priv->rx_vq[0]; 455 while (i >= 0) { 456 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i]; 457 dpaa2_free_dq_storage(dpaa2_q->q_storage); 458 rte_free(dpaa2_q->q_storage); 459 priv->rx_vq[i--] = NULL; 460 } 461 rte_free(mc_q); 462 return -1; 463 } 464 465 static void 466 dpaa2_free_rx_tx_queues(struct rte_eth_dev *dev) 467 { 468 struct dpaa2_dev_priv *priv = dev->data->dev_private; 469 struct dpaa2_queue *dpaa2_q; 470 int i; 471 472 PMD_INIT_FUNC_TRACE(); 473 474 /* Queue allocation base */ 475 if (priv->rx_vq[0]) { 476 /* cleaning up queue storage */ 477 for (i = 0; i < priv->nb_rx_queues; i++) { 478 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i]; 479 if (dpaa2_q->q_storage) 480 rte_free(dpaa2_q->q_storage); 481 } 482 /* cleanup tx queue cscn */ 483 for (i = 0; i < priv->nb_tx_queues; i++) { 484 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; 485 rte_free(dpaa2_q->cscn); 486 } 487 if (priv->tx_conf_en) { 488 /* cleanup tx conf queue storage */ 489 for (i = 0; i < priv->nb_tx_queues; i++) { 490 dpaa2_q = (struct dpaa2_queue *) 491 priv->tx_conf_vq[i]; 492 rte_free(dpaa2_q->q_storage); 493 } 494 } 495 /*free memory for all queues (RX+TX) */ 496 rte_free(priv->rx_vq[0]); 497 priv->rx_vq[0] = NULL; 498 } 499 } 500 501 static int 502 dpaa2_eth_dev_configure(struct rte_eth_dev *dev) 503 { 504 struct dpaa2_dev_priv *priv = dev->data->dev_private; 505 struct fsl_mc_io *dpni = dev->process_private; 506 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 507 uint64_t rx_offloads = eth_conf->rxmode.offloads; 508 uint64_t tx_offloads = eth_conf->txmode.offloads; 509 int rx_l3_csum_offload = false; 510 int rx_l4_csum_offload = false; 511 int tx_l3_csum_offload = false; 512 int tx_l4_csum_offload = false; 513 int ret, tc_index; 514 515 PMD_INIT_FUNC_TRACE(); 516 517 /* Rx offloads which are enabled by default */ 518 if (dev_rx_offloads_nodis & ~rx_offloads) { 519 DPAA2_PMD_INFO( 520 "Some of rx offloads enabled by default - requested 0x%" PRIx64 521 " fixed are 0x%" PRIx64, 522 rx_offloads, dev_rx_offloads_nodis); 523 } 524 525 /* Tx offloads which are enabled by default */ 526 if (dev_tx_offloads_nodis & ~tx_offloads) { 527 DPAA2_PMD_INFO( 528 "Some of tx offloads enabled by default - requested 0x%" PRIx64 529 " fixed are 0x%" PRIx64, 530 tx_offloads, dev_tx_offloads_nodis); 531 } 532 533 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 534 if (eth_conf->rxmode.max_rx_pkt_len <= DPAA2_MAX_RX_PKT_LEN) { 535 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, 536 priv->token, eth_conf->rxmode.max_rx_pkt_len 537 - RTE_ETHER_CRC_LEN); 538 if (ret) { 539 DPAA2_PMD_ERR( 540 "Unable to set mtu. check config"); 541 return ret; 542 } 543 dev->data->mtu = 544 dev->data->dev_conf.rxmode.max_rx_pkt_len - 545 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - 546 VLAN_TAG_SIZE; 547 } else { 548 return -1; 549 } 550 } 551 552 if (eth_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) { 553 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) { 554 ret = dpaa2_setup_flow_dist(dev, 555 eth_conf->rx_adv_conf.rss_conf.rss_hf, 556 tc_index); 557 if (ret) { 558 DPAA2_PMD_ERR( 559 "Unable to set flow distribution on tc%d." 560 "Check queue config", tc_index); 561 return ret; 562 } 563 } 564 } 565 566 if (rx_offloads & DEV_RX_OFFLOAD_IPV4_CKSUM) 567 rx_l3_csum_offload = true; 568 569 if ((rx_offloads & DEV_RX_OFFLOAD_UDP_CKSUM) || 570 (rx_offloads & DEV_RX_OFFLOAD_TCP_CKSUM) || 571 (rx_offloads & DEV_RX_OFFLOAD_SCTP_CKSUM)) 572 rx_l4_csum_offload = true; 573 574 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 575 DPNI_OFF_RX_L3_CSUM, rx_l3_csum_offload); 576 if (ret) { 577 DPAA2_PMD_ERR("Error to set RX l3 csum:Error = %d", ret); 578 return ret; 579 } 580 581 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 582 DPNI_OFF_RX_L4_CSUM, rx_l4_csum_offload); 583 if (ret) { 584 DPAA2_PMD_ERR("Error to get RX l4 csum:Error = %d", ret); 585 return ret; 586 } 587 588 #if !defined(RTE_LIBRTE_IEEE1588) 589 if (rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) 590 #endif 591 dpaa2_enable_ts[dev->data->port_id] = true; 592 593 if (tx_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM) 594 tx_l3_csum_offload = true; 595 596 if ((tx_offloads & DEV_TX_OFFLOAD_UDP_CKSUM) || 597 (tx_offloads & DEV_TX_OFFLOAD_TCP_CKSUM) || 598 (tx_offloads & DEV_TX_OFFLOAD_SCTP_CKSUM)) 599 tx_l4_csum_offload = true; 600 601 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 602 DPNI_OFF_TX_L3_CSUM, tx_l3_csum_offload); 603 if (ret) { 604 DPAA2_PMD_ERR("Error to set TX l3 csum:Error = %d", ret); 605 return ret; 606 } 607 608 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 609 DPNI_OFF_TX_L4_CSUM, tx_l4_csum_offload); 610 if (ret) { 611 DPAA2_PMD_ERR("Error to get TX l4 csum:Error = %d", ret); 612 return ret; 613 } 614 615 /* Enabling hash results in FD requires setting DPNI_FLCTYPE_HASH in 616 * dpni_set_offload API. Setting this FLCTYPE for DPNI sets the FD[SC] 617 * to 0 for LS2 in the hardware thus disabling data/annotation 618 * stashing. For LX2 this is fixed in hardware and thus hash result and 619 * parse results can be received in FD using this option. 620 */ 621 if (dpaa2_svr_family == SVR_LX2160A) { 622 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 623 DPNI_FLCTYPE_HASH, true); 624 if (ret) { 625 DPAA2_PMD_ERR("Error setting FLCTYPE: Err = %d", ret); 626 return ret; 627 } 628 } 629 630 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 631 dpaa2_vlan_offload_set(dev, ETH_VLAN_FILTER_MASK); 632 633 return 0; 634 } 635 636 /* Function to setup RX flow information. It contains traffic class ID, 637 * flow ID, destination configuration etc. 638 */ 639 static int 640 dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev, 641 uint16_t rx_queue_id, 642 uint16_t nb_rx_desc, 643 unsigned int socket_id __rte_unused, 644 const struct rte_eth_rxconf *rx_conf, 645 struct rte_mempool *mb_pool) 646 { 647 struct dpaa2_dev_priv *priv = dev->data->dev_private; 648 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 649 struct dpaa2_queue *dpaa2_q; 650 struct dpni_queue cfg; 651 uint8_t options = 0; 652 uint8_t flow_id; 653 uint32_t bpid; 654 int i, ret; 655 656 PMD_INIT_FUNC_TRACE(); 657 658 DPAA2_PMD_DEBUG("dev =%p, queue =%d, pool = %p, conf =%p", 659 dev, rx_queue_id, mb_pool, rx_conf); 660 661 /* Rx deferred start is not supported */ 662 if (rx_conf->rx_deferred_start) { 663 DPAA2_PMD_ERR("%p:Rx deferred start not supported", 664 (void *)dev); 665 return -EINVAL; 666 } 667 668 if (!priv->bp_list || priv->bp_list->mp != mb_pool) { 669 bpid = mempool_to_bpid(mb_pool); 670 ret = dpaa2_attach_bp_list(priv, 671 rte_dpaa2_bpid_info[bpid].bp_list); 672 if (ret) 673 return ret; 674 } 675 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id]; 676 dpaa2_q->mb_pool = mb_pool; /**< mbuf pool to populate RX ring. */ 677 dpaa2_q->bp_array = rte_dpaa2_bpid_info; 678 dpaa2_q->nb_desc = UINT16_MAX; 679 dpaa2_q->offloads = rx_conf->offloads; 680 681 /*Get the flow id from given VQ id*/ 682 flow_id = dpaa2_q->flow_id; 683 memset(&cfg, 0, sizeof(struct dpni_queue)); 684 685 options = options | DPNI_QUEUE_OPT_USER_CTX; 686 cfg.user_context = (size_t)(dpaa2_q); 687 688 /* check if a private cgr available. */ 689 for (i = 0; i < priv->max_cgs; i++) { 690 if (!priv->cgid_in_use[i]) { 691 priv->cgid_in_use[i] = 1; 692 break; 693 } 694 } 695 696 if (i < priv->max_cgs) { 697 options |= DPNI_QUEUE_OPT_SET_CGID; 698 cfg.cgid = i; 699 dpaa2_q->cgid = cfg.cgid; 700 } else { 701 dpaa2_q->cgid = 0xff; 702 } 703 704 /*if ls2088 or rev2 device, enable the stashing */ 705 706 if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) { 707 options |= DPNI_QUEUE_OPT_FLC; 708 cfg.flc.stash_control = true; 709 cfg.flc.value &= 0xFFFFFFFFFFFFFFC0; 710 /* 00 00 00 - last 6 bit represent annotation, context stashing, 711 * data stashing setting 01 01 00 (0x14) 712 * (in following order ->DS AS CS) 713 * to enable 1 line data, 1 line annotation. 714 * For LX2, this setting should be 01 00 00 (0x10) 715 */ 716 if ((dpaa2_svr_family & 0xffff0000) == SVR_LX2160A) 717 cfg.flc.value |= 0x10; 718 else 719 cfg.flc.value |= 0x14; 720 } 721 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX, 722 dpaa2_q->tc_index, flow_id, options, &cfg); 723 if (ret) { 724 DPAA2_PMD_ERR("Error in setting the rx flow: = %d", ret); 725 return -1; 726 } 727 728 if (!(priv->flags & DPAA2_RX_TAILDROP_OFF)) { 729 struct dpni_taildrop taildrop; 730 731 taildrop.enable = 1; 732 dpaa2_q->nb_desc = nb_rx_desc; 733 /* Private CGR will use tail drop length as nb_rx_desc. 734 * for rest cases we can use standard byte based tail drop. 735 * There is no HW restriction, but number of CGRs are limited, 736 * hence this restriction is placed. 737 */ 738 if (dpaa2_q->cgid != 0xff) { 739 /*enabling per rx queue congestion control */ 740 taildrop.threshold = nb_rx_desc; 741 taildrop.units = DPNI_CONGESTION_UNIT_FRAMES; 742 taildrop.oal = 0; 743 DPAA2_PMD_DEBUG("Enabling CG Tail Drop on queue = %d", 744 rx_queue_id); 745 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token, 746 DPNI_CP_CONGESTION_GROUP, 747 DPNI_QUEUE_RX, 748 dpaa2_q->tc_index, 749 dpaa2_q->cgid, &taildrop); 750 } else { 751 /*enabling per rx queue congestion control */ 752 taildrop.threshold = CONG_THRESHOLD_RX_BYTES_Q; 753 taildrop.units = DPNI_CONGESTION_UNIT_BYTES; 754 taildrop.oal = CONG_RX_OAL; 755 DPAA2_PMD_DEBUG("Enabling Byte based Drop on queue= %d", 756 rx_queue_id); 757 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token, 758 DPNI_CP_QUEUE, DPNI_QUEUE_RX, 759 dpaa2_q->tc_index, flow_id, 760 &taildrop); 761 } 762 if (ret) { 763 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)", 764 ret); 765 return -1; 766 } 767 } else { /* Disable tail Drop */ 768 struct dpni_taildrop taildrop = {0}; 769 DPAA2_PMD_INFO("Tail drop is disabled on queue"); 770 771 taildrop.enable = 0; 772 if (dpaa2_q->cgid != 0xff) { 773 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token, 774 DPNI_CP_CONGESTION_GROUP, DPNI_QUEUE_RX, 775 dpaa2_q->tc_index, 776 dpaa2_q->cgid, &taildrop); 777 } else { 778 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token, 779 DPNI_CP_QUEUE, DPNI_QUEUE_RX, 780 dpaa2_q->tc_index, flow_id, &taildrop); 781 } 782 if (ret) { 783 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)", 784 ret); 785 return -1; 786 } 787 } 788 789 dev->data->rx_queues[rx_queue_id] = dpaa2_q; 790 return 0; 791 } 792 793 static int 794 dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev, 795 uint16_t tx_queue_id, 796 uint16_t nb_tx_desc, 797 unsigned int socket_id __rte_unused, 798 const struct rte_eth_txconf *tx_conf) 799 { 800 struct dpaa2_dev_priv *priv = dev->data->dev_private; 801 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *) 802 priv->tx_vq[tx_queue_id]; 803 struct dpaa2_queue *dpaa2_tx_conf_q = (struct dpaa2_queue *) 804 priv->tx_conf_vq[tx_queue_id]; 805 struct fsl_mc_io *dpni = dev->process_private; 806 struct dpni_queue tx_conf_cfg; 807 struct dpni_queue tx_flow_cfg; 808 uint8_t options = 0, flow_id; 809 struct dpni_queue_id qid; 810 uint32_t tc_id; 811 int ret; 812 813 PMD_INIT_FUNC_TRACE(); 814 815 /* Tx deferred start is not supported */ 816 if (tx_conf->tx_deferred_start) { 817 DPAA2_PMD_ERR("%p:Tx deferred start not supported", 818 (void *)dev); 819 return -EINVAL; 820 } 821 822 dpaa2_q->nb_desc = UINT16_MAX; 823 dpaa2_q->offloads = tx_conf->offloads; 824 825 /* Return if queue already configured */ 826 if (dpaa2_q->flow_id != 0xffff) { 827 dev->data->tx_queues[tx_queue_id] = dpaa2_q; 828 return 0; 829 } 830 831 memset(&tx_conf_cfg, 0, sizeof(struct dpni_queue)); 832 memset(&tx_flow_cfg, 0, sizeof(struct dpni_queue)); 833 834 tc_id = tx_queue_id; 835 flow_id = 0; 836 837 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX, 838 tc_id, flow_id, options, &tx_flow_cfg); 839 if (ret) { 840 DPAA2_PMD_ERR("Error in setting the tx flow: " 841 "tc_id=%d, flow=%d err=%d", 842 tc_id, flow_id, ret); 843 return -1; 844 } 845 846 dpaa2_q->flow_id = flow_id; 847 848 if (tx_queue_id == 0) { 849 /*Set tx-conf and error configuration*/ 850 if (priv->tx_conf_en) 851 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW, 852 priv->token, 853 DPNI_CONF_AFFINE); 854 else 855 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW, 856 priv->token, 857 DPNI_CONF_DISABLE); 858 if (ret) { 859 DPAA2_PMD_ERR("Error in set tx conf mode settings: " 860 "err=%d", ret); 861 return -1; 862 } 863 } 864 dpaa2_q->tc_index = tc_id; 865 866 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token, 867 DPNI_QUEUE_TX, dpaa2_q->tc_index, 868 dpaa2_q->flow_id, &tx_flow_cfg, &qid); 869 if (ret) { 870 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret); 871 return -1; 872 } 873 dpaa2_q->fqid = qid.fqid; 874 875 if (!(priv->flags & DPAA2_TX_CGR_OFF)) { 876 struct dpni_congestion_notification_cfg cong_notif_cfg = {0}; 877 878 dpaa2_q->nb_desc = nb_tx_desc; 879 880 cong_notif_cfg.units = DPNI_CONGESTION_UNIT_FRAMES; 881 cong_notif_cfg.threshold_entry = nb_tx_desc; 882 /* Notify that the queue is not congested when the data in 883 * the queue is below this thershold. 884 */ 885 cong_notif_cfg.threshold_exit = nb_tx_desc - 24; 886 cong_notif_cfg.message_ctx = 0; 887 cong_notif_cfg.message_iova = 888 (size_t)DPAA2_VADDR_TO_IOVA(dpaa2_q->cscn); 889 cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE; 890 cong_notif_cfg.notification_mode = 891 DPNI_CONG_OPT_WRITE_MEM_ON_ENTER | 892 DPNI_CONG_OPT_WRITE_MEM_ON_EXIT | 893 DPNI_CONG_OPT_COHERENT_WRITE; 894 cong_notif_cfg.cg_point = DPNI_CP_QUEUE; 895 896 ret = dpni_set_congestion_notification(dpni, CMD_PRI_LOW, 897 priv->token, 898 DPNI_QUEUE_TX, 899 tc_id, 900 &cong_notif_cfg); 901 if (ret) { 902 DPAA2_PMD_ERR( 903 "Error in setting tx congestion notification: " 904 "err=%d", ret); 905 return -ret; 906 } 907 } 908 dpaa2_q->cb_eqresp_free = dpaa2_dev_free_eqresp_buf; 909 dev->data->tx_queues[tx_queue_id] = dpaa2_q; 910 911 if (priv->tx_conf_en) { 912 dpaa2_q->tx_conf_queue = dpaa2_tx_conf_q; 913 options = options | DPNI_QUEUE_OPT_USER_CTX; 914 tx_conf_cfg.user_context = (size_t)(dpaa2_q); 915 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, 916 DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index, 917 dpaa2_tx_conf_q->flow_id, options, &tx_conf_cfg); 918 if (ret) { 919 DPAA2_PMD_ERR("Error in setting the tx conf flow: " 920 "tc_index=%d, flow=%d err=%d", 921 dpaa2_tx_conf_q->tc_index, 922 dpaa2_tx_conf_q->flow_id, ret); 923 return -1; 924 } 925 926 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token, 927 DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index, 928 dpaa2_tx_conf_q->flow_id, &tx_conf_cfg, &qid); 929 if (ret) { 930 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret); 931 return -1; 932 } 933 dpaa2_tx_conf_q->fqid = qid.fqid; 934 } 935 return 0; 936 } 937 938 static void 939 dpaa2_dev_rx_queue_release(void *q __rte_unused) 940 { 941 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)q; 942 struct dpaa2_dev_priv *priv = dpaa2_q->eth_data->dev_private; 943 struct fsl_mc_io *dpni = 944 (struct fsl_mc_io *)priv->eth_dev->process_private; 945 uint8_t options = 0; 946 int ret; 947 struct dpni_queue cfg; 948 949 memset(&cfg, 0, sizeof(struct dpni_queue)); 950 PMD_INIT_FUNC_TRACE(); 951 if (dpaa2_q->cgid != 0xff) { 952 options = DPNI_QUEUE_OPT_CLEAR_CGID; 953 cfg.cgid = dpaa2_q->cgid; 954 955 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, 956 DPNI_QUEUE_RX, 957 dpaa2_q->tc_index, dpaa2_q->flow_id, 958 options, &cfg); 959 if (ret) 960 DPAA2_PMD_ERR("Unable to clear CGR from q=%u err=%d", 961 dpaa2_q->fqid, ret); 962 priv->cgid_in_use[dpaa2_q->cgid] = 0; 963 dpaa2_q->cgid = 0xff; 964 } 965 } 966 967 static void 968 dpaa2_dev_tx_queue_release(void *q __rte_unused) 969 { 970 PMD_INIT_FUNC_TRACE(); 971 } 972 973 static uint32_t 974 dpaa2_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id) 975 { 976 int32_t ret; 977 struct dpaa2_dev_priv *priv = dev->data->dev_private; 978 struct dpaa2_queue *dpaa2_q; 979 struct qbman_swp *swp; 980 struct qbman_fq_query_np_rslt state; 981 uint32_t frame_cnt = 0; 982 983 if (unlikely(!DPAA2_PER_LCORE_DPIO)) { 984 ret = dpaa2_affine_qbman_swp(); 985 if (ret) { 986 DPAA2_PMD_ERR( 987 "Failed to allocate IO portal, tid: %d\n", 988 rte_gettid()); 989 return -EINVAL; 990 } 991 } 992 swp = DPAA2_PER_LCORE_PORTAL; 993 994 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id]; 995 996 if (qbman_fq_query_state(swp, dpaa2_q->fqid, &state) == 0) { 997 frame_cnt = qbman_fq_state_frame_count(&state); 998 DPAA2_PMD_DP_DEBUG("RX frame count for q(%d) is %u", 999 rx_queue_id, frame_cnt); 1000 } 1001 return frame_cnt; 1002 } 1003 1004 static const uint32_t * 1005 dpaa2_supported_ptypes_get(struct rte_eth_dev *dev) 1006 { 1007 static const uint32_t ptypes[] = { 1008 /*todo -= add more types */ 1009 RTE_PTYPE_L2_ETHER, 1010 RTE_PTYPE_L3_IPV4, 1011 RTE_PTYPE_L3_IPV4_EXT, 1012 RTE_PTYPE_L3_IPV6, 1013 RTE_PTYPE_L3_IPV6_EXT, 1014 RTE_PTYPE_L4_TCP, 1015 RTE_PTYPE_L4_UDP, 1016 RTE_PTYPE_L4_SCTP, 1017 RTE_PTYPE_L4_ICMP, 1018 RTE_PTYPE_UNKNOWN 1019 }; 1020 1021 if (dev->rx_pkt_burst == dpaa2_dev_prefetch_rx || 1022 dev->rx_pkt_burst == dpaa2_dev_rx || 1023 dev->rx_pkt_burst == dpaa2_dev_loopback_rx) 1024 return ptypes; 1025 return NULL; 1026 } 1027 1028 /** 1029 * Dpaa2 link Interrupt handler 1030 * 1031 * @param param 1032 * The address of parameter (struct rte_eth_dev *) regsitered before. 1033 * 1034 * @return 1035 * void 1036 */ 1037 static void 1038 dpaa2_interrupt_handler(void *param) 1039 { 1040 struct rte_eth_dev *dev = param; 1041 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1042 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1043 int ret; 1044 int irq_index = DPNI_IRQ_INDEX; 1045 unsigned int status = 0, clear = 0; 1046 1047 PMD_INIT_FUNC_TRACE(); 1048 1049 if (dpni == NULL) { 1050 DPAA2_PMD_ERR("dpni is NULL"); 1051 return; 1052 } 1053 1054 ret = dpni_get_irq_status(dpni, CMD_PRI_LOW, priv->token, 1055 irq_index, &status); 1056 if (unlikely(ret)) { 1057 DPAA2_PMD_ERR("Can't get irq status (err %d)", ret); 1058 clear = 0xffffffff; 1059 goto out; 1060 } 1061 1062 if (status & DPNI_IRQ_EVENT_LINK_CHANGED) { 1063 clear = DPNI_IRQ_EVENT_LINK_CHANGED; 1064 dpaa2_dev_link_update(dev, 0); 1065 /* calling all the apps registered for link status event */ 1066 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL); 1067 } 1068 out: 1069 ret = dpni_clear_irq_status(dpni, CMD_PRI_LOW, priv->token, 1070 irq_index, clear); 1071 if (unlikely(ret)) 1072 DPAA2_PMD_ERR("Can't clear irq status (err %d)", ret); 1073 } 1074 1075 static int 1076 dpaa2_eth_setup_irqs(struct rte_eth_dev *dev, int enable) 1077 { 1078 int err = 0; 1079 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1080 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1081 int irq_index = DPNI_IRQ_INDEX; 1082 unsigned int mask = DPNI_IRQ_EVENT_LINK_CHANGED; 1083 1084 PMD_INIT_FUNC_TRACE(); 1085 1086 err = dpni_set_irq_mask(dpni, CMD_PRI_LOW, priv->token, 1087 irq_index, mask); 1088 if (err < 0) { 1089 DPAA2_PMD_ERR("Error: dpni_set_irq_mask():%d (%s)", err, 1090 strerror(-err)); 1091 return err; 1092 } 1093 1094 err = dpni_set_irq_enable(dpni, CMD_PRI_LOW, priv->token, 1095 irq_index, enable); 1096 if (err < 0) 1097 DPAA2_PMD_ERR("Error: dpni_set_irq_enable():%d (%s)", err, 1098 strerror(-err)); 1099 1100 return err; 1101 } 1102 1103 static int 1104 dpaa2_dev_start(struct rte_eth_dev *dev) 1105 { 1106 struct rte_device *rdev = dev->device; 1107 struct rte_dpaa2_device *dpaa2_dev; 1108 struct rte_eth_dev_data *data = dev->data; 1109 struct dpaa2_dev_priv *priv = data->dev_private; 1110 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1111 struct dpni_queue cfg; 1112 struct dpni_error_cfg err_cfg; 1113 uint16_t qdid; 1114 struct dpni_queue_id qid; 1115 struct dpaa2_queue *dpaa2_q; 1116 int ret, i; 1117 struct rte_intr_handle *intr_handle; 1118 1119 dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device); 1120 intr_handle = &dpaa2_dev->intr_handle; 1121 1122 PMD_INIT_FUNC_TRACE(); 1123 1124 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token); 1125 if (ret) { 1126 DPAA2_PMD_ERR("Failure in enabling dpni %d device: err=%d", 1127 priv->hw_id, ret); 1128 return ret; 1129 } 1130 1131 /* Power up the phy. Needed to make the link go UP */ 1132 dpaa2_dev_set_link_up(dev); 1133 1134 ret = dpni_get_qdid(dpni, CMD_PRI_LOW, priv->token, 1135 DPNI_QUEUE_TX, &qdid); 1136 if (ret) { 1137 DPAA2_PMD_ERR("Error in getting qdid: err=%d", ret); 1138 return ret; 1139 } 1140 priv->qdid = qdid; 1141 1142 for (i = 0; i < data->nb_rx_queues; i++) { 1143 dpaa2_q = (struct dpaa2_queue *)data->rx_queues[i]; 1144 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token, 1145 DPNI_QUEUE_RX, dpaa2_q->tc_index, 1146 dpaa2_q->flow_id, &cfg, &qid); 1147 if (ret) { 1148 DPAA2_PMD_ERR("Error in getting flow information: " 1149 "err=%d", ret); 1150 return ret; 1151 } 1152 dpaa2_q->fqid = qid.fqid; 1153 } 1154 1155 /*checksum errors, send them to normal path and set it in annotation */ 1156 err_cfg.errors = DPNI_ERROR_L3CE | DPNI_ERROR_L4CE; 1157 err_cfg.errors |= DPNI_ERROR_PHE; 1158 1159 err_cfg.error_action = DPNI_ERROR_ACTION_CONTINUE; 1160 err_cfg.set_frame_annotation = true; 1161 1162 ret = dpni_set_errors_behavior(dpni, CMD_PRI_LOW, 1163 priv->token, &err_cfg); 1164 if (ret) { 1165 DPAA2_PMD_ERR("Error to dpni_set_errors_behavior: code = %d", 1166 ret); 1167 return ret; 1168 } 1169 1170 /* if the interrupts were configured on this devices*/ 1171 if (intr_handle && (intr_handle->fd) && 1172 (dev->data->dev_conf.intr_conf.lsc != 0)) { 1173 /* Registering LSC interrupt handler */ 1174 rte_intr_callback_register(intr_handle, 1175 dpaa2_interrupt_handler, 1176 (void *)dev); 1177 1178 /* enable vfio intr/eventfd mapping 1179 * Interrupt index 0 is required, so we can not use 1180 * rte_intr_enable. 1181 */ 1182 rte_dpaa2_intr_enable(intr_handle, DPNI_IRQ_INDEX); 1183 1184 /* enable dpni_irqs */ 1185 dpaa2_eth_setup_irqs(dev, 1); 1186 } 1187 1188 /* Change the tx burst function if ordered queues are used */ 1189 if (priv->en_ordered) 1190 dev->tx_pkt_burst = dpaa2_dev_tx_ordered; 1191 1192 return 0; 1193 } 1194 1195 /** 1196 * This routine disables all traffic on the adapter by issuing a 1197 * global reset on the MAC. 1198 */ 1199 static void 1200 dpaa2_dev_stop(struct rte_eth_dev *dev) 1201 { 1202 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1203 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1204 int ret; 1205 struct rte_eth_link link; 1206 struct rte_intr_handle *intr_handle = dev->intr_handle; 1207 1208 PMD_INIT_FUNC_TRACE(); 1209 1210 /* reset interrupt callback */ 1211 if (intr_handle && (intr_handle->fd) && 1212 (dev->data->dev_conf.intr_conf.lsc != 0)) { 1213 /*disable dpni irqs */ 1214 dpaa2_eth_setup_irqs(dev, 0); 1215 1216 /* disable vfio intr before callback unregister */ 1217 rte_dpaa2_intr_disable(intr_handle, DPNI_IRQ_INDEX); 1218 1219 /* Unregistering LSC interrupt handler */ 1220 rte_intr_callback_unregister(intr_handle, 1221 dpaa2_interrupt_handler, 1222 (void *)dev); 1223 } 1224 1225 dpaa2_dev_set_link_down(dev); 1226 1227 ret = dpni_disable(dpni, CMD_PRI_LOW, priv->token); 1228 if (ret) { 1229 DPAA2_PMD_ERR("Failure (ret %d) in disabling dpni %d dev", 1230 ret, priv->hw_id); 1231 return; 1232 } 1233 1234 /* clear the recorded link status */ 1235 memset(&link, 0, sizeof(link)); 1236 rte_eth_linkstatus_set(dev, &link); 1237 } 1238 1239 static void 1240 dpaa2_dev_close(struct rte_eth_dev *dev) 1241 { 1242 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1243 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1244 int ret; 1245 struct rte_eth_link link; 1246 1247 PMD_INIT_FUNC_TRACE(); 1248 1249 dpaa2_flow_clean(dev); 1250 1251 /* Clean the device first */ 1252 ret = dpni_reset(dpni, CMD_PRI_LOW, priv->token); 1253 if (ret) { 1254 DPAA2_PMD_ERR("Failure cleaning dpni device: err=%d", ret); 1255 return; 1256 } 1257 1258 memset(&link, 0, sizeof(link)); 1259 rte_eth_linkstatus_set(dev, &link); 1260 } 1261 1262 static int 1263 dpaa2_dev_promiscuous_enable( 1264 struct rte_eth_dev *dev) 1265 { 1266 int ret; 1267 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1268 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1269 1270 PMD_INIT_FUNC_TRACE(); 1271 1272 if (dpni == NULL) { 1273 DPAA2_PMD_ERR("dpni is NULL"); 1274 return -ENODEV; 1275 } 1276 1277 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, true); 1278 if (ret < 0) 1279 DPAA2_PMD_ERR("Unable to enable U promisc mode %d", ret); 1280 1281 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true); 1282 if (ret < 0) 1283 DPAA2_PMD_ERR("Unable to enable M promisc mode %d", ret); 1284 1285 return ret; 1286 } 1287 1288 static int 1289 dpaa2_dev_promiscuous_disable( 1290 struct rte_eth_dev *dev) 1291 { 1292 int ret; 1293 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1294 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1295 1296 PMD_INIT_FUNC_TRACE(); 1297 1298 if (dpni == NULL) { 1299 DPAA2_PMD_ERR("dpni is NULL"); 1300 return -ENODEV; 1301 } 1302 1303 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, false); 1304 if (ret < 0) 1305 DPAA2_PMD_ERR("Unable to disable U promisc mode %d", ret); 1306 1307 if (dev->data->all_multicast == 0) { 1308 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, 1309 priv->token, false); 1310 if (ret < 0) 1311 DPAA2_PMD_ERR("Unable to disable M promisc mode %d", 1312 ret); 1313 } 1314 1315 return ret; 1316 } 1317 1318 static int 1319 dpaa2_dev_allmulticast_enable( 1320 struct rte_eth_dev *dev) 1321 { 1322 int ret; 1323 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1324 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1325 1326 PMD_INIT_FUNC_TRACE(); 1327 1328 if (dpni == NULL) { 1329 DPAA2_PMD_ERR("dpni is NULL"); 1330 return -ENODEV; 1331 } 1332 1333 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true); 1334 if (ret < 0) 1335 DPAA2_PMD_ERR("Unable to enable multicast mode %d", ret); 1336 1337 return ret; 1338 } 1339 1340 static int 1341 dpaa2_dev_allmulticast_disable(struct rte_eth_dev *dev) 1342 { 1343 int ret; 1344 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1345 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1346 1347 PMD_INIT_FUNC_TRACE(); 1348 1349 if (dpni == NULL) { 1350 DPAA2_PMD_ERR("dpni is NULL"); 1351 return -ENODEV; 1352 } 1353 1354 /* must remain on for all promiscuous */ 1355 if (dev->data->promiscuous == 1) 1356 return 0; 1357 1358 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, false); 1359 if (ret < 0) 1360 DPAA2_PMD_ERR("Unable to disable multicast mode %d", ret); 1361 1362 return ret; 1363 } 1364 1365 static int 1366 dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 1367 { 1368 int ret; 1369 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1370 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1371 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN 1372 + VLAN_TAG_SIZE; 1373 1374 PMD_INIT_FUNC_TRACE(); 1375 1376 if (dpni == NULL) { 1377 DPAA2_PMD_ERR("dpni is NULL"); 1378 return -EINVAL; 1379 } 1380 1381 /* check that mtu is within the allowed range */ 1382 if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA2_MAX_RX_PKT_LEN) 1383 return -EINVAL; 1384 1385 if (frame_size > RTE_ETHER_MAX_LEN) 1386 dev->data->dev_conf.rxmode.offloads |= 1387 DEV_RX_OFFLOAD_JUMBO_FRAME; 1388 else 1389 dev->data->dev_conf.rxmode.offloads &= 1390 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 1391 1392 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 1393 1394 /* Set the Max Rx frame length as 'mtu' + 1395 * Maximum Ethernet header length 1396 */ 1397 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, priv->token, 1398 frame_size - RTE_ETHER_CRC_LEN); 1399 if (ret) { 1400 DPAA2_PMD_ERR("Setting the max frame length failed"); 1401 return -1; 1402 } 1403 DPAA2_PMD_INFO("MTU configured for the device: %d", mtu); 1404 return 0; 1405 } 1406 1407 static int 1408 dpaa2_dev_add_mac_addr(struct rte_eth_dev *dev, 1409 struct rte_ether_addr *addr, 1410 __rte_unused uint32_t index, 1411 __rte_unused uint32_t pool) 1412 { 1413 int ret; 1414 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1415 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1416 1417 PMD_INIT_FUNC_TRACE(); 1418 1419 if (dpni == NULL) { 1420 DPAA2_PMD_ERR("dpni is NULL"); 1421 return -1; 1422 } 1423 1424 ret = dpni_add_mac_addr(dpni, CMD_PRI_LOW, priv->token, 1425 addr->addr_bytes, 0, 0, 0); 1426 if (ret) 1427 DPAA2_PMD_ERR( 1428 "error: Adding the MAC ADDR failed: err = %d", ret); 1429 return 0; 1430 } 1431 1432 static void 1433 dpaa2_dev_remove_mac_addr(struct rte_eth_dev *dev, 1434 uint32_t index) 1435 { 1436 int ret; 1437 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1438 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1439 struct rte_eth_dev_data *data = dev->data; 1440 struct rte_ether_addr *macaddr; 1441 1442 PMD_INIT_FUNC_TRACE(); 1443 1444 macaddr = &data->mac_addrs[index]; 1445 1446 if (dpni == NULL) { 1447 DPAA2_PMD_ERR("dpni is NULL"); 1448 return; 1449 } 1450 1451 ret = dpni_remove_mac_addr(dpni, CMD_PRI_LOW, 1452 priv->token, macaddr->addr_bytes); 1453 if (ret) 1454 DPAA2_PMD_ERR( 1455 "error: Removing the MAC ADDR failed: err = %d", ret); 1456 } 1457 1458 static int 1459 dpaa2_dev_set_mac_addr(struct rte_eth_dev *dev, 1460 struct rte_ether_addr *addr) 1461 { 1462 int ret; 1463 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1464 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1465 1466 PMD_INIT_FUNC_TRACE(); 1467 1468 if (dpni == NULL) { 1469 DPAA2_PMD_ERR("dpni is NULL"); 1470 return -EINVAL; 1471 } 1472 1473 ret = dpni_set_primary_mac_addr(dpni, CMD_PRI_LOW, 1474 priv->token, addr->addr_bytes); 1475 1476 if (ret) 1477 DPAA2_PMD_ERR( 1478 "error: Setting the MAC ADDR failed %d", ret); 1479 1480 return ret; 1481 } 1482 1483 static 1484 int dpaa2_dev_stats_get(struct rte_eth_dev *dev, 1485 struct rte_eth_stats *stats) 1486 { 1487 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1488 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1489 int32_t retcode; 1490 uint8_t page0 = 0, page1 = 1, page2 = 2; 1491 union dpni_statistics value; 1492 int i; 1493 struct dpaa2_queue *dpaa2_rxq, *dpaa2_txq; 1494 1495 memset(&value, 0, sizeof(union dpni_statistics)); 1496 1497 PMD_INIT_FUNC_TRACE(); 1498 1499 if (!dpni) { 1500 DPAA2_PMD_ERR("dpni is NULL"); 1501 return -EINVAL; 1502 } 1503 1504 if (!stats) { 1505 DPAA2_PMD_ERR("stats is NULL"); 1506 return -EINVAL; 1507 } 1508 1509 /*Get Counters from page_0*/ 1510 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1511 page0, 0, &value); 1512 if (retcode) 1513 goto err; 1514 1515 stats->ipackets = value.page_0.ingress_all_frames; 1516 stats->ibytes = value.page_0.ingress_all_bytes; 1517 1518 /*Get Counters from page_1*/ 1519 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1520 page1, 0, &value); 1521 if (retcode) 1522 goto err; 1523 1524 stats->opackets = value.page_1.egress_all_frames; 1525 stats->obytes = value.page_1.egress_all_bytes; 1526 1527 /*Get Counters from page_2*/ 1528 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1529 page2, 0, &value); 1530 if (retcode) 1531 goto err; 1532 1533 /* Ingress drop frame count due to configured rules */ 1534 stats->ierrors = value.page_2.ingress_filtered_frames; 1535 /* Ingress drop frame count due to error */ 1536 stats->ierrors += value.page_2.ingress_discarded_frames; 1537 1538 stats->oerrors = value.page_2.egress_discarded_frames; 1539 stats->imissed = value.page_2.ingress_nobuffer_discards; 1540 1541 /* Fill in per queue stats */ 1542 for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) && 1543 (i < priv->nb_rx_queues || i < priv->nb_tx_queues); ++i) { 1544 dpaa2_rxq = (struct dpaa2_queue *)priv->rx_vq[i]; 1545 dpaa2_txq = (struct dpaa2_queue *)priv->tx_vq[i]; 1546 if (dpaa2_rxq) 1547 stats->q_ipackets[i] = dpaa2_rxq->rx_pkts; 1548 if (dpaa2_txq) 1549 stats->q_opackets[i] = dpaa2_txq->tx_pkts; 1550 1551 /* Byte counting is not implemented */ 1552 stats->q_ibytes[i] = 0; 1553 stats->q_obytes[i] = 0; 1554 } 1555 1556 return 0; 1557 1558 err: 1559 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode); 1560 return retcode; 1561 }; 1562 1563 static int 1564 dpaa2_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 1565 unsigned int n) 1566 { 1567 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1568 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1569 int32_t retcode; 1570 union dpni_statistics value[5] = {}; 1571 unsigned int i = 0, num = RTE_DIM(dpaa2_xstats_strings); 1572 1573 if (n < num) 1574 return num; 1575 1576 if (xstats == NULL) 1577 return 0; 1578 1579 /* Get Counters from page_0*/ 1580 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1581 0, 0, &value[0]); 1582 if (retcode) 1583 goto err; 1584 1585 /* Get Counters from page_1*/ 1586 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1587 1, 0, &value[1]); 1588 if (retcode) 1589 goto err; 1590 1591 /* Get Counters from page_2*/ 1592 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1593 2, 0, &value[2]); 1594 if (retcode) 1595 goto err; 1596 1597 for (i = 0; i < priv->max_cgs; i++) { 1598 if (!priv->cgid_in_use[i]) { 1599 /* Get Counters from page_4*/ 1600 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, 1601 priv->token, 1602 4, 0, &value[4]); 1603 if (retcode) 1604 goto err; 1605 break; 1606 } 1607 } 1608 1609 for (i = 0; i < num; i++) { 1610 xstats[i].id = i; 1611 xstats[i].value = value[dpaa2_xstats_strings[i].page_id]. 1612 raw.counter[dpaa2_xstats_strings[i].stats_id]; 1613 } 1614 return i; 1615 err: 1616 DPAA2_PMD_ERR("Error in obtaining extended stats (%d)", retcode); 1617 return retcode; 1618 } 1619 1620 static int 1621 dpaa2_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 1622 struct rte_eth_xstat_name *xstats_names, 1623 unsigned int limit) 1624 { 1625 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings); 1626 1627 if (limit < stat_cnt) 1628 return stat_cnt; 1629 1630 if (xstats_names != NULL) 1631 for (i = 0; i < stat_cnt; i++) 1632 strlcpy(xstats_names[i].name, 1633 dpaa2_xstats_strings[i].name, 1634 sizeof(xstats_names[i].name)); 1635 1636 return stat_cnt; 1637 } 1638 1639 static int 1640 dpaa2_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 1641 uint64_t *values, unsigned int n) 1642 { 1643 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings); 1644 uint64_t values_copy[stat_cnt]; 1645 1646 if (!ids) { 1647 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1648 struct fsl_mc_io *dpni = 1649 (struct fsl_mc_io *)dev->process_private; 1650 int32_t retcode; 1651 union dpni_statistics value[5] = {}; 1652 1653 if (n < stat_cnt) 1654 return stat_cnt; 1655 1656 if (!values) 1657 return 0; 1658 1659 /* Get Counters from page_0*/ 1660 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1661 0, 0, &value[0]); 1662 if (retcode) 1663 return 0; 1664 1665 /* Get Counters from page_1*/ 1666 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1667 1, 0, &value[1]); 1668 if (retcode) 1669 return 0; 1670 1671 /* Get Counters from page_2*/ 1672 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1673 2, 0, &value[2]); 1674 if (retcode) 1675 return 0; 1676 1677 /* Get Counters from page_4*/ 1678 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1679 4, 0, &value[4]); 1680 if (retcode) 1681 return 0; 1682 1683 for (i = 0; i < stat_cnt; i++) { 1684 values[i] = value[dpaa2_xstats_strings[i].page_id]. 1685 raw.counter[dpaa2_xstats_strings[i].stats_id]; 1686 } 1687 return stat_cnt; 1688 } 1689 1690 dpaa2_xstats_get_by_id(dev, NULL, values_copy, stat_cnt); 1691 1692 for (i = 0; i < n; i++) { 1693 if (ids[i] >= stat_cnt) { 1694 DPAA2_PMD_ERR("xstats id value isn't valid"); 1695 return -1; 1696 } 1697 values[i] = values_copy[ids[i]]; 1698 } 1699 return n; 1700 } 1701 1702 static int 1703 dpaa2_xstats_get_names_by_id( 1704 struct rte_eth_dev *dev, 1705 struct rte_eth_xstat_name *xstats_names, 1706 const uint64_t *ids, 1707 unsigned int limit) 1708 { 1709 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings); 1710 struct rte_eth_xstat_name xstats_names_copy[stat_cnt]; 1711 1712 if (!ids) 1713 return dpaa2_xstats_get_names(dev, xstats_names, limit); 1714 1715 dpaa2_xstats_get_names(dev, xstats_names_copy, limit); 1716 1717 for (i = 0; i < limit; i++) { 1718 if (ids[i] >= stat_cnt) { 1719 DPAA2_PMD_ERR("xstats id value isn't valid"); 1720 return -1; 1721 } 1722 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 1723 } 1724 return limit; 1725 } 1726 1727 static int 1728 dpaa2_dev_stats_reset(struct rte_eth_dev *dev) 1729 { 1730 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1731 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1732 int retcode; 1733 int i; 1734 struct dpaa2_queue *dpaa2_q; 1735 1736 PMD_INIT_FUNC_TRACE(); 1737 1738 if (dpni == NULL) { 1739 DPAA2_PMD_ERR("dpni is NULL"); 1740 return -EINVAL; 1741 } 1742 1743 retcode = dpni_reset_statistics(dpni, CMD_PRI_LOW, priv->token); 1744 if (retcode) 1745 goto error; 1746 1747 /* Reset the per queue stats in dpaa2_queue structure */ 1748 for (i = 0; i < priv->nb_rx_queues; i++) { 1749 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i]; 1750 if (dpaa2_q) 1751 dpaa2_q->rx_pkts = 0; 1752 } 1753 1754 for (i = 0; i < priv->nb_tx_queues; i++) { 1755 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; 1756 if (dpaa2_q) 1757 dpaa2_q->tx_pkts = 0; 1758 } 1759 1760 return 0; 1761 1762 error: 1763 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode); 1764 return retcode; 1765 }; 1766 1767 /* return 0 means link status changed, -1 means not changed */ 1768 static int 1769 dpaa2_dev_link_update(struct rte_eth_dev *dev, 1770 int wait_to_complete __rte_unused) 1771 { 1772 int ret; 1773 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1774 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1775 struct rte_eth_link link; 1776 struct dpni_link_state state = {0}; 1777 1778 if (dpni == NULL) { 1779 DPAA2_PMD_ERR("dpni is NULL"); 1780 return 0; 1781 } 1782 1783 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state); 1784 if (ret < 0) { 1785 DPAA2_PMD_DEBUG("error: dpni_get_link_state %d", ret); 1786 return -1; 1787 } 1788 1789 memset(&link, 0, sizeof(struct rte_eth_link)); 1790 link.link_status = state.up; 1791 link.link_speed = state.rate; 1792 1793 if (state.options & DPNI_LINK_OPT_HALF_DUPLEX) 1794 link.link_duplex = ETH_LINK_HALF_DUPLEX; 1795 else 1796 link.link_duplex = ETH_LINK_FULL_DUPLEX; 1797 1798 ret = rte_eth_linkstatus_set(dev, &link); 1799 if (ret == -1) 1800 DPAA2_PMD_DEBUG("No change in status"); 1801 else 1802 DPAA2_PMD_INFO("Port %d Link is %s\n", dev->data->port_id, 1803 link.link_status ? "Up" : "Down"); 1804 1805 return ret; 1806 } 1807 1808 /** 1809 * Toggle the DPNI to enable, if not already enabled. 1810 * This is not strictly PHY up/down - it is more of logical toggling. 1811 */ 1812 static int 1813 dpaa2_dev_set_link_up(struct rte_eth_dev *dev) 1814 { 1815 int ret = -EINVAL; 1816 struct dpaa2_dev_priv *priv; 1817 struct fsl_mc_io *dpni; 1818 int en = 0; 1819 struct dpni_link_state state = {0}; 1820 1821 priv = dev->data->dev_private; 1822 dpni = (struct fsl_mc_io *)dev->process_private; 1823 1824 if (dpni == NULL) { 1825 DPAA2_PMD_ERR("dpni is NULL"); 1826 return ret; 1827 } 1828 1829 /* Check if DPNI is currently enabled */ 1830 ret = dpni_is_enabled(dpni, CMD_PRI_LOW, priv->token, &en); 1831 if (ret) { 1832 /* Unable to obtain dpni status; Not continuing */ 1833 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret); 1834 return -EINVAL; 1835 } 1836 1837 /* Enable link if not already enabled */ 1838 if (!en) { 1839 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token); 1840 if (ret) { 1841 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret); 1842 return -EINVAL; 1843 } 1844 } 1845 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state); 1846 if (ret < 0) { 1847 DPAA2_PMD_DEBUG("Unable to get link state (%d)", ret); 1848 return -1; 1849 } 1850 1851 /* changing tx burst function to start enqueues */ 1852 dev->tx_pkt_burst = dpaa2_dev_tx; 1853 dev->data->dev_link.link_status = state.up; 1854 dev->data->dev_link.link_speed = state.rate; 1855 1856 if (state.up) 1857 DPAA2_PMD_INFO("Port %d Link is Up", dev->data->port_id); 1858 else 1859 DPAA2_PMD_INFO("Port %d Link is Down", dev->data->port_id); 1860 return ret; 1861 } 1862 1863 /** 1864 * Toggle the DPNI to disable, if not already disabled. 1865 * This is not strictly PHY up/down - it is more of logical toggling. 1866 */ 1867 static int 1868 dpaa2_dev_set_link_down(struct rte_eth_dev *dev) 1869 { 1870 int ret = -EINVAL; 1871 struct dpaa2_dev_priv *priv; 1872 struct fsl_mc_io *dpni; 1873 int dpni_enabled = 0; 1874 int retries = 10; 1875 1876 PMD_INIT_FUNC_TRACE(); 1877 1878 priv = dev->data->dev_private; 1879 dpni = (struct fsl_mc_io *)dev->process_private; 1880 1881 if (dpni == NULL) { 1882 DPAA2_PMD_ERR("Device has not yet been configured"); 1883 return ret; 1884 } 1885 1886 /*changing tx burst function to avoid any more enqueues */ 1887 dev->tx_pkt_burst = dummy_dev_tx; 1888 1889 /* Loop while dpni_disable() attempts to drain the egress FQs 1890 * and confirm them back to us. 1891 */ 1892 do { 1893 ret = dpni_disable(dpni, 0, priv->token); 1894 if (ret) { 1895 DPAA2_PMD_ERR("dpni disable failed (%d)", ret); 1896 return ret; 1897 } 1898 ret = dpni_is_enabled(dpni, 0, priv->token, &dpni_enabled); 1899 if (ret) { 1900 DPAA2_PMD_ERR("dpni enable check failed (%d)", ret); 1901 return ret; 1902 } 1903 if (dpni_enabled) 1904 /* Allow the MC some slack */ 1905 rte_delay_us(100 * 1000); 1906 } while (dpni_enabled && --retries); 1907 1908 if (!retries) { 1909 DPAA2_PMD_WARN("Retry count exceeded disabling dpni"); 1910 /* todo- we may have to manually cleanup queues. 1911 */ 1912 } else { 1913 DPAA2_PMD_INFO("Port %d Link DOWN successful", 1914 dev->data->port_id); 1915 } 1916 1917 dev->data->dev_link.link_status = 0; 1918 1919 return ret; 1920 } 1921 1922 static int 1923 dpaa2_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 1924 { 1925 int ret = -EINVAL; 1926 struct dpaa2_dev_priv *priv; 1927 struct fsl_mc_io *dpni; 1928 struct dpni_link_state state = {0}; 1929 1930 PMD_INIT_FUNC_TRACE(); 1931 1932 priv = dev->data->dev_private; 1933 dpni = (struct fsl_mc_io *)dev->process_private; 1934 1935 if (dpni == NULL || fc_conf == NULL) { 1936 DPAA2_PMD_ERR("device not configured"); 1937 return ret; 1938 } 1939 1940 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state); 1941 if (ret) { 1942 DPAA2_PMD_ERR("error: dpni_get_link_state %d", ret); 1943 return ret; 1944 } 1945 1946 memset(fc_conf, 0, sizeof(struct rte_eth_fc_conf)); 1947 if (state.options & DPNI_LINK_OPT_PAUSE) { 1948 /* DPNI_LINK_OPT_PAUSE set 1949 * if ASYM_PAUSE not set, 1950 * RX Side flow control (handle received Pause frame) 1951 * TX side flow control (send Pause frame) 1952 * if ASYM_PAUSE set, 1953 * RX Side flow control (handle received Pause frame) 1954 * No TX side flow control (send Pause frame disabled) 1955 */ 1956 if (!(state.options & DPNI_LINK_OPT_ASYM_PAUSE)) 1957 fc_conf->mode = RTE_FC_FULL; 1958 else 1959 fc_conf->mode = RTE_FC_RX_PAUSE; 1960 } else { 1961 /* DPNI_LINK_OPT_PAUSE not set 1962 * if ASYM_PAUSE set, 1963 * TX side flow control (send Pause frame) 1964 * No RX side flow control (No action on pause frame rx) 1965 * if ASYM_PAUSE not set, 1966 * Flow control disabled 1967 */ 1968 if (state.options & DPNI_LINK_OPT_ASYM_PAUSE) 1969 fc_conf->mode = RTE_FC_TX_PAUSE; 1970 else 1971 fc_conf->mode = RTE_FC_NONE; 1972 } 1973 1974 return ret; 1975 } 1976 1977 static int 1978 dpaa2_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 1979 { 1980 int ret = -EINVAL; 1981 struct dpaa2_dev_priv *priv; 1982 struct fsl_mc_io *dpni; 1983 struct dpni_link_state state = {0}; 1984 struct dpni_link_cfg cfg = {0}; 1985 1986 PMD_INIT_FUNC_TRACE(); 1987 1988 priv = dev->data->dev_private; 1989 dpni = (struct fsl_mc_io *)dev->process_private; 1990 1991 if (dpni == NULL) { 1992 DPAA2_PMD_ERR("dpni is NULL"); 1993 return ret; 1994 } 1995 1996 /* It is necessary to obtain the current state before setting fc_conf 1997 * as MC would return error in case rate, autoneg or duplex values are 1998 * different. 1999 */ 2000 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state); 2001 if (ret) { 2002 DPAA2_PMD_ERR("Unable to get link state (err=%d)", ret); 2003 return -1; 2004 } 2005 2006 /* Disable link before setting configuration */ 2007 dpaa2_dev_set_link_down(dev); 2008 2009 /* Based on fc_conf, update cfg */ 2010 cfg.rate = state.rate; 2011 cfg.options = state.options; 2012 2013 /* update cfg with fc_conf */ 2014 switch (fc_conf->mode) { 2015 case RTE_FC_FULL: 2016 /* Full flow control; 2017 * OPT_PAUSE set, ASYM_PAUSE not set 2018 */ 2019 cfg.options |= DPNI_LINK_OPT_PAUSE; 2020 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE; 2021 break; 2022 case RTE_FC_TX_PAUSE: 2023 /* Enable RX flow control 2024 * OPT_PAUSE not set; 2025 * ASYM_PAUSE set; 2026 */ 2027 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE; 2028 cfg.options &= ~DPNI_LINK_OPT_PAUSE; 2029 break; 2030 case RTE_FC_RX_PAUSE: 2031 /* Enable TX Flow control 2032 * OPT_PAUSE set 2033 * ASYM_PAUSE set 2034 */ 2035 cfg.options |= DPNI_LINK_OPT_PAUSE; 2036 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE; 2037 break; 2038 case RTE_FC_NONE: 2039 /* Disable Flow control 2040 * OPT_PAUSE not set 2041 * ASYM_PAUSE not set 2042 */ 2043 cfg.options &= ~DPNI_LINK_OPT_PAUSE; 2044 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE; 2045 break; 2046 default: 2047 DPAA2_PMD_ERR("Incorrect Flow control flag (%d)", 2048 fc_conf->mode); 2049 return -1; 2050 } 2051 2052 ret = dpni_set_link_cfg(dpni, CMD_PRI_LOW, priv->token, &cfg); 2053 if (ret) 2054 DPAA2_PMD_ERR("Unable to set Link configuration (err=%d)", 2055 ret); 2056 2057 /* Enable link */ 2058 dpaa2_dev_set_link_up(dev); 2059 2060 return ret; 2061 } 2062 2063 static int 2064 dpaa2_dev_rss_hash_update(struct rte_eth_dev *dev, 2065 struct rte_eth_rss_conf *rss_conf) 2066 { 2067 struct rte_eth_dev_data *data = dev->data; 2068 struct dpaa2_dev_priv *priv = data->dev_private; 2069 struct rte_eth_conf *eth_conf = &data->dev_conf; 2070 int ret, tc_index; 2071 2072 PMD_INIT_FUNC_TRACE(); 2073 2074 if (rss_conf->rss_hf) { 2075 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) { 2076 ret = dpaa2_setup_flow_dist(dev, rss_conf->rss_hf, 2077 tc_index); 2078 if (ret) { 2079 DPAA2_PMD_ERR("Unable to set flow dist on tc%d", 2080 tc_index); 2081 return ret; 2082 } 2083 } 2084 } else { 2085 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) { 2086 ret = dpaa2_remove_flow_dist(dev, tc_index); 2087 if (ret) { 2088 DPAA2_PMD_ERR( 2089 "Unable to remove flow dist on tc%d", 2090 tc_index); 2091 return ret; 2092 } 2093 } 2094 } 2095 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf; 2096 return 0; 2097 } 2098 2099 static int 2100 dpaa2_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 2101 struct rte_eth_rss_conf *rss_conf) 2102 { 2103 struct rte_eth_dev_data *data = dev->data; 2104 struct rte_eth_conf *eth_conf = &data->dev_conf; 2105 2106 /* dpaa2 does not support rss_key, so length should be 0*/ 2107 rss_conf->rss_key_len = 0; 2108 rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf; 2109 return 0; 2110 } 2111 2112 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev, 2113 int eth_rx_queue_id, 2114 struct dpaa2_dpcon_dev *dpcon, 2115 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf) 2116 { 2117 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private; 2118 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 2119 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id]; 2120 uint8_t flow_id = dpaa2_ethq->flow_id; 2121 struct dpni_queue cfg; 2122 uint8_t options, priority; 2123 int ret; 2124 2125 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_PARALLEL) 2126 dpaa2_ethq->cb = dpaa2_dev_process_parallel_event; 2127 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) 2128 dpaa2_ethq->cb = dpaa2_dev_process_atomic_event; 2129 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED) 2130 dpaa2_ethq->cb = dpaa2_dev_process_ordered_event; 2131 else 2132 return -EINVAL; 2133 2134 priority = (RTE_EVENT_DEV_PRIORITY_LOWEST / queue_conf->ev.priority) * 2135 (dpcon->num_priorities - 1); 2136 2137 memset(&cfg, 0, sizeof(struct dpni_queue)); 2138 options = DPNI_QUEUE_OPT_DEST; 2139 cfg.destination.type = DPNI_DEST_DPCON; 2140 cfg.destination.id = dpcon->dpcon_id; 2141 cfg.destination.priority = priority; 2142 2143 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) { 2144 options |= DPNI_QUEUE_OPT_HOLD_ACTIVE; 2145 cfg.destination.hold_active = 1; 2146 } 2147 2148 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED && 2149 !eth_priv->en_ordered) { 2150 struct opr_cfg ocfg; 2151 2152 /* Restoration window size = 256 frames */ 2153 ocfg.oprrws = 3; 2154 /* Restoration window size = 512 frames for LX2 */ 2155 if (dpaa2_svr_family == SVR_LX2160A) 2156 ocfg.oprrws = 4; 2157 /* Auto advance NESN window enabled */ 2158 ocfg.oa = 1; 2159 /* Late arrival window size disabled */ 2160 ocfg.olws = 0; 2161 /* ORL resource exhaustaion advance NESN disabled */ 2162 ocfg.oeane = 0; 2163 /* Loose ordering enabled */ 2164 ocfg.oloe = 1; 2165 eth_priv->en_loose_ordered = 1; 2166 /* Strict ordering enabled if explicitly set */ 2167 if (getenv("DPAA2_STRICT_ORDERING_ENABLE")) { 2168 ocfg.oloe = 0; 2169 eth_priv->en_loose_ordered = 0; 2170 } 2171 2172 ret = dpni_set_opr(dpni, CMD_PRI_LOW, eth_priv->token, 2173 dpaa2_ethq->tc_index, flow_id, 2174 OPR_OPT_CREATE, &ocfg); 2175 if (ret) { 2176 DPAA2_PMD_ERR("Error setting opr: ret: %d\n", ret); 2177 return ret; 2178 } 2179 2180 eth_priv->en_ordered = 1; 2181 } 2182 2183 options |= DPNI_QUEUE_OPT_USER_CTX; 2184 cfg.user_context = (size_t)(dpaa2_ethq); 2185 2186 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX, 2187 dpaa2_ethq->tc_index, flow_id, options, &cfg); 2188 if (ret) { 2189 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret); 2190 return ret; 2191 } 2192 2193 memcpy(&dpaa2_ethq->ev, &queue_conf->ev, sizeof(struct rte_event)); 2194 2195 return 0; 2196 } 2197 2198 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev, 2199 int eth_rx_queue_id) 2200 { 2201 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private; 2202 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 2203 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id]; 2204 uint8_t flow_id = dpaa2_ethq->flow_id; 2205 struct dpni_queue cfg; 2206 uint8_t options; 2207 int ret; 2208 2209 memset(&cfg, 0, sizeof(struct dpni_queue)); 2210 options = DPNI_QUEUE_OPT_DEST; 2211 cfg.destination.type = DPNI_DEST_NONE; 2212 2213 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX, 2214 dpaa2_ethq->tc_index, flow_id, options, &cfg); 2215 if (ret) 2216 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret); 2217 2218 return ret; 2219 } 2220 2221 static inline int 2222 dpaa2_dev_verify_filter_ops(enum rte_filter_op filter_op) 2223 { 2224 unsigned int i; 2225 2226 for (i = 0; i < RTE_DIM(dpaa2_supported_filter_ops); i++) { 2227 if (dpaa2_supported_filter_ops[i] == filter_op) 2228 return 0; 2229 } 2230 return -ENOTSUP; 2231 } 2232 2233 static int 2234 dpaa2_dev_flow_ctrl(struct rte_eth_dev *dev, 2235 enum rte_filter_type filter_type, 2236 enum rte_filter_op filter_op, 2237 void *arg) 2238 { 2239 int ret = 0; 2240 2241 if (!dev) 2242 return -ENODEV; 2243 2244 switch (filter_type) { 2245 case RTE_ETH_FILTER_GENERIC: 2246 if (dpaa2_dev_verify_filter_ops(filter_op) < 0) { 2247 ret = -ENOTSUP; 2248 break; 2249 } 2250 *(const void **)arg = &dpaa2_flow_ops; 2251 dpaa2_filter_type |= filter_type; 2252 break; 2253 default: 2254 RTE_LOG(ERR, PMD, "Filter type (%d) not supported", 2255 filter_type); 2256 ret = -ENOTSUP; 2257 break; 2258 } 2259 return ret; 2260 } 2261 2262 static void 2263 dpaa2_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 2264 struct rte_eth_rxq_info *qinfo) 2265 { 2266 struct dpaa2_queue *rxq; 2267 2268 rxq = (struct dpaa2_queue *)dev->data->rx_queues[queue_id]; 2269 2270 qinfo->mp = rxq->mb_pool; 2271 qinfo->scattered_rx = dev->data->scattered_rx; 2272 qinfo->nb_desc = rxq->nb_desc; 2273 2274 qinfo->conf.rx_free_thresh = 1; 2275 qinfo->conf.rx_drop_en = 1; 2276 qinfo->conf.rx_deferred_start = 0; 2277 qinfo->conf.offloads = rxq->offloads; 2278 } 2279 2280 static void 2281 dpaa2_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 2282 struct rte_eth_txq_info *qinfo) 2283 { 2284 struct dpaa2_queue *txq; 2285 2286 txq = dev->data->tx_queues[queue_id]; 2287 2288 qinfo->nb_desc = txq->nb_desc; 2289 qinfo->conf.tx_thresh.pthresh = 0; 2290 qinfo->conf.tx_thresh.hthresh = 0; 2291 qinfo->conf.tx_thresh.wthresh = 0; 2292 2293 qinfo->conf.tx_free_thresh = 0; 2294 qinfo->conf.tx_rs_thresh = 0; 2295 qinfo->conf.offloads = txq->offloads; 2296 qinfo->conf.tx_deferred_start = 0; 2297 } 2298 2299 static struct eth_dev_ops dpaa2_ethdev_ops = { 2300 .dev_configure = dpaa2_eth_dev_configure, 2301 .dev_start = dpaa2_dev_start, 2302 .dev_stop = dpaa2_dev_stop, 2303 .dev_close = dpaa2_dev_close, 2304 .promiscuous_enable = dpaa2_dev_promiscuous_enable, 2305 .promiscuous_disable = dpaa2_dev_promiscuous_disable, 2306 .allmulticast_enable = dpaa2_dev_allmulticast_enable, 2307 .allmulticast_disable = dpaa2_dev_allmulticast_disable, 2308 .dev_set_link_up = dpaa2_dev_set_link_up, 2309 .dev_set_link_down = dpaa2_dev_set_link_down, 2310 .link_update = dpaa2_dev_link_update, 2311 .stats_get = dpaa2_dev_stats_get, 2312 .xstats_get = dpaa2_dev_xstats_get, 2313 .xstats_get_by_id = dpaa2_xstats_get_by_id, 2314 .xstats_get_names_by_id = dpaa2_xstats_get_names_by_id, 2315 .xstats_get_names = dpaa2_xstats_get_names, 2316 .stats_reset = dpaa2_dev_stats_reset, 2317 .xstats_reset = dpaa2_dev_stats_reset, 2318 .fw_version_get = dpaa2_fw_version_get, 2319 .dev_infos_get = dpaa2_dev_info_get, 2320 .dev_supported_ptypes_get = dpaa2_supported_ptypes_get, 2321 .mtu_set = dpaa2_dev_mtu_set, 2322 .vlan_filter_set = dpaa2_vlan_filter_set, 2323 .vlan_offload_set = dpaa2_vlan_offload_set, 2324 .vlan_tpid_set = dpaa2_vlan_tpid_set, 2325 .rx_queue_setup = dpaa2_dev_rx_queue_setup, 2326 .rx_queue_release = dpaa2_dev_rx_queue_release, 2327 .tx_queue_setup = dpaa2_dev_tx_queue_setup, 2328 .tx_queue_release = dpaa2_dev_tx_queue_release, 2329 .rx_burst_mode_get = dpaa2_dev_rx_burst_mode_get, 2330 .tx_burst_mode_get = dpaa2_dev_tx_burst_mode_get, 2331 .flow_ctrl_get = dpaa2_flow_ctrl_get, 2332 .flow_ctrl_set = dpaa2_flow_ctrl_set, 2333 .mac_addr_add = dpaa2_dev_add_mac_addr, 2334 .mac_addr_remove = dpaa2_dev_remove_mac_addr, 2335 .mac_addr_set = dpaa2_dev_set_mac_addr, 2336 .rss_hash_update = dpaa2_dev_rss_hash_update, 2337 .rss_hash_conf_get = dpaa2_dev_rss_hash_conf_get, 2338 .filter_ctrl = dpaa2_dev_flow_ctrl, 2339 .rxq_info_get = dpaa2_rxq_info_get, 2340 .txq_info_get = dpaa2_txq_info_get, 2341 #if defined(RTE_LIBRTE_IEEE1588) 2342 .timesync_enable = dpaa2_timesync_enable, 2343 .timesync_disable = dpaa2_timesync_disable, 2344 .timesync_read_time = dpaa2_timesync_read_time, 2345 .timesync_write_time = dpaa2_timesync_write_time, 2346 .timesync_adjust_time = dpaa2_timesync_adjust_time, 2347 .timesync_read_rx_timestamp = dpaa2_timesync_read_rx_timestamp, 2348 .timesync_read_tx_timestamp = dpaa2_timesync_read_tx_timestamp, 2349 #endif 2350 }; 2351 2352 /* Populate the mac address from physically available (u-boot/firmware) and/or 2353 * one set by higher layers like MC (restool) etc. 2354 * Returns the table of MAC entries (multiple entries) 2355 */ 2356 static int 2357 populate_mac_addr(struct fsl_mc_io *dpni_dev, struct dpaa2_dev_priv *priv, 2358 struct rte_ether_addr *mac_entry) 2359 { 2360 int ret; 2361 struct rte_ether_addr phy_mac, prime_mac; 2362 2363 memset(&phy_mac, 0, sizeof(struct rte_ether_addr)); 2364 memset(&prime_mac, 0, sizeof(struct rte_ether_addr)); 2365 2366 /* Get the physical device MAC address */ 2367 ret = dpni_get_port_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token, 2368 phy_mac.addr_bytes); 2369 if (ret) { 2370 DPAA2_PMD_ERR("DPNI get physical port MAC failed: %d", ret); 2371 goto cleanup; 2372 } 2373 2374 ret = dpni_get_primary_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token, 2375 prime_mac.addr_bytes); 2376 if (ret) { 2377 DPAA2_PMD_ERR("DPNI get Prime port MAC failed: %d", ret); 2378 goto cleanup; 2379 } 2380 2381 /* Now that both MAC have been obtained, do: 2382 * if not_empty_mac(phy) && phy != Prime, overwrite prime with Phy 2383 * and return phy 2384 * If empty_mac(phy), return prime. 2385 * if both are empty, create random MAC, set as prime and return 2386 */ 2387 if (!rte_is_zero_ether_addr(&phy_mac)) { 2388 /* If the addresses are not same, overwrite prime */ 2389 if (!rte_is_same_ether_addr(&phy_mac, &prime_mac)) { 2390 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW, 2391 priv->token, 2392 phy_mac.addr_bytes); 2393 if (ret) { 2394 DPAA2_PMD_ERR("Unable to set MAC Address: %d", 2395 ret); 2396 goto cleanup; 2397 } 2398 memcpy(&prime_mac, &phy_mac, 2399 sizeof(struct rte_ether_addr)); 2400 } 2401 } else if (rte_is_zero_ether_addr(&prime_mac)) { 2402 /* In case phys and prime, both are zero, create random MAC */ 2403 rte_eth_random_addr(prime_mac.addr_bytes); 2404 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW, 2405 priv->token, 2406 prime_mac.addr_bytes); 2407 if (ret) { 2408 DPAA2_PMD_ERR("Unable to set MAC Address: %d", ret); 2409 goto cleanup; 2410 } 2411 } 2412 2413 /* prime_mac the final MAC address */ 2414 memcpy(mac_entry, &prime_mac, sizeof(struct rte_ether_addr)); 2415 return 0; 2416 2417 cleanup: 2418 return -1; 2419 } 2420 2421 static int 2422 check_devargs_handler(__rte_unused const char *key, const char *value, 2423 __rte_unused void *opaque) 2424 { 2425 if (strcmp(value, "1")) 2426 return -1; 2427 2428 return 0; 2429 } 2430 2431 static int 2432 dpaa2_get_devargs(struct rte_devargs *devargs, const char *key) 2433 { 2434 struct rte_kvargs *kvlist; 2435 2436 if (!devargs) 2437 return 0; 2438 2439 kvlist = rte_kvargs_parse(devargs->args, NULL); 2440 if (!kvlist) 2441 return 0; 2442 2443 if (!rte_kvargs_count(kvlist, key)) { 2444 rte_kvargs_free(kvlist); 2445 return 0; 2446 } 2447 2448 if (rte_kvargs_process(kvlist, key, 2449 check_devargs_handler, NULL) < 0) { 2450 rte_kvargs_free(kvlist); 2451 return 0; 2452 } 2453 rte_kvargs_free(kvlist); 2454 2455 return 1; 2456 } 2457 2458 static int 2459 dpaa2_dev_init(struct rte_eth_dev *eth_dev) 2460 { 2461 struct rte_device *dev = eth_dev->device; 2462 struct rte_dpaa2_device *dpaa2_dev; 2463 struct fsl_mc_io *dpni_dev; 2464 struct dpni_attr attr; 2465 struct dpaa2_dev_priv *priv = eth_dev->data->dev_private; 2466 struct dpni_buffer_layout layout; 2467 int ret, hw_id, i; 2468 2469 PMD_INIT_FUNC_TRACE(); 2470 2471 dpni_dev = rte_malloc(NULL, sizeof(struct fsl_mc_io), 0); 2472 if (!dpni_dev) { 2473 DPAA2_PMD_ERR("Memory allocation failed for dpni device"); 2474 return -1; 2475 } 2476 dpni_dev->regs = dpaa2_get_mcp_ptr(MC_PORTAL_INDEX); 2477 eth_dev->process_private = (void *)dpni_dev; 2478 2479 /* For secondary processes, the primary has done all the work */ 2480 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2481 /* In case of secondary, only burst and ops API need to be 2482 * plugged. 2483 */ 2484 eth_dev->dev_ops = &dpaa2_ethdev_ops; 2485 eth_dev->rx_queue_count = dpaa2_dev_rx_queue_count; 2486 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) 2487 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx; 2488 else if (dpaa2_get_devargs(dev->devargs, 2489 DRIVER_NO_PREFETCH_MODE)) 2490 eth_dev->rx_pkt_burst = dpaa2_dev_rx; 2491 else 2492 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx; 2493 eth_dev->tx_pkt_burst = dpaa2_dev_tx; 2494 return 0; 2495 } 2496 2497 dpaa2_dev = container_of(dev, struct rte_dpaa2_device, device); 2498 2499 hw_id = dpaa2_dev->object_id; 2500 ret = dpni_open(dpni_dev, CMD_PRI_LOW, hw_id, &priv->token); 2501 if (ret) { 2502 DPAA2_PMD_ERR( 2503 "Failure in opening dpni@%d with err code %d", 2504 hw_id, ret); 2505 rte_free(dpni_dev); 2506 return -1; 2507 } 2508 2509 /* Clean the device first */ 2510 ret = dpni_reset(dpni_dev, CMD_PRI_LOW, priv->token); 2511 if (ret) { 2512 DPAA2_PMD_ERR("Failure cleaning dpni@%d with err code %d", 2513 hw_id, ret); 2514 goto init_err; 2515 } 2516 2517 ret = dpni_get_attributes(dpni_dev, CMD_PRI_LOW, priv->token, &attr); 2518 if (ret) { 2519 DPAA2_PMD_ERR( 2520 "Failure in get dpni@%d attribute, err code %d", 2521 hw_id, ret); 2522 goto init_err; 2523 } 2524 2525 priv->num_rx_tc = attr.num_rx_tcs; 2526 priv->qos_entries = attr.qos_entries; 2527 priv->fs_entries = attr.fs_entries; 2528 priv->dist_queues = attr.num_queues; 2529 2530 /* only if the custom CG is enabled */ 2531 if (attr.options & DPNI_OPT_CUSTOM_CG) 2532 priv->max_cgs = attr.num_cgs; 2533 else 2534 priv->max_cgs = 0; 2535 2536 for (i = 0; i < priv->max_cgs; i++) 2537 priv->cgid_in_use[i] = 0; 2538 2539 for (i = 0; i < attr.num_rx_tcs; i++) 2540 priv->nb_rx_queues += attr.num_queues; 2541 2542 /* Using number of TX queues as number of TX TCs */ 2543 priv->nb_tx_queues = attr.num_tx_tcs; 2544 2545 DPAA2_PMD_DEBUG("RX-TC= %d, rx_queues= %d, tx_queues=%d, max_cgs=%d", 2546 priv->num_rx_tc, priv->nb_rx_queues, 2547 priv->nb_tx_queues, priv->max_cgs); 2548 2549 priv->hw = dpni_dev; 2550 priv->hw_id = hw_id; 2551 priv->options = attr.options; 2552 priv->max_mac_filters = attr.mac_filter_entries; 2553 priv->max_vlan_filters = attr.vlan_filter_entries; 2554 priv->flags = 0; 2555 #if defined(RTE_LIBRTE_IEEE1588) 2556 priv->tx_conf_en = 1; 2557 #else 2558 priv->tx_conf_en = 0; 2559 #endif 2560 2561 /* Allocate memory for hardware structure for queues */ 2562 ret = dpaa2_alloc_rx_tx_queues(eth_dev); 2563 if (ret) { 2564 DPAA2_PMD_ERR("Queue allocation Failed"); 2565 goto init_err; 2566 } 2567 2568 /* Allocate memory for storing MAC addresses. 2569 * Table of mac_filter_entries size is allocated so that RTE ether lib 2570 * can add MAC entries when rte_eth_dev_mac_addr_add is called. 2571 */ 2572 eth_dev->data->mac_addrs = rte_zmalloc("dpni", 2573 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries, 0); 2574 if (eth_dev->data->mac_addrs == NULL) { 2575 DPAA2_PMD_ERR( 2576 "Failed to allocate %d bytes needed to store MAC addresses", 2577 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries); 2578 ret = -ENOMEM; 2579 goto init_err; 2580 } 2581 2582 ret = populate_mac_addr(dpni_dev, priv, ð_dev->data->mac_addrs[0]); 2583 if (ret) { 2584 DPAA2_PMD_ERR("Unable to fetch MAC Address for device"); 2585 rte_free(eth_dev->data->mac_addrs); 2586 eth_dev->data->mac_addrs = NULL; 2587 goto init_err; 2588 } 2589 2590 /* ... tx buffer layout ... */ 2591 memset(&layout, 0, sizeof(struct dpni_buffer_layout)); 2592 if (priv->tx_conf_en) { 2593 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS | 2594 DPNI_BUF_LAYOUT_OPT_TIMESTAMP; 2595 layout.pass_timestamp = true; 2596 } else { 2597 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS; 2598 } 2599 layout.pass_frame_status = 1; 2600 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token, 2601 DPNI_QUEUE_TX, &layout); 2602 if (ret) { 2603 DPAA2_PMD_ERR("Error (%d) in setting tx buffer layout", ret); 2604 goto init_err; 2605 } 2606 2607 /* ... tx-conf and error buffer layout ... */ 2608 memset(&layout, 0, sizeof(struct dpni_buffer_layout)); 2609 if (priv->tx_conf_en) { 2610 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS | 2611 DPNI_BUF_LAYOUT_OPT_TIMESTAMP; 2612 layout.pass_timestamp = true; 2613 } else { 2614 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS; 2615 } 2616 layout.pass_frame_status = 1; 2617 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token, 2618 DPNI_QUEUE_TX_CONFIRM, &layout); 2619 if (ret) { 2620 DPAA2_PMD_ERR("Error (%d) in setting tx-conf buffer layout", 2621 ret); 2622 goto init_err; 2623 } 2624 2625 eth_dev->dev_ops = &dpaa2_ethdev_ops; 2626 2627 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) { 2628 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx; 2629 DPAA2_PMD_INFO("Loopback mode"); 2630 } else if (dpaa2_get_devargs(dev->devargs, DRIVER_NO_PREFETCH_MODE)) { 2631 eth_dev->rx_pkt_burst = dpaa2_dev_rx; 2632 DPAA2_PMD_INFO("No Prefetch mode"); 2633 } else { 2634 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx; 2635 } 2636 eth_dev->tx_pkt_burst = dpaa2_dev_tx; 2637 2638 /*Init fields w.r.t. classficaition*/ 2639 memset(&priv->extract.qos_key_extract, 0, 2640 sizeof(struct dpaa2_key_extract)); 2641 priv->extract.qos_extract_param = (size_t)rte_malloc(NULL, 256, 64); 2642 if (!priv->extract.qos_extract_param) { 2643 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow " 2644 " classificaiton ", ret); 2645 goto init_err; 2646 } 2647 priv->extract.qos_key_extract.key_info.ipv4_src_offset = 2648 IP_ADDRESS_OFFSET_INVALID; 2649 priv->extract.qos_key_extract.key_info.ipv4_dst_offset = 2650 IP_ADDRESS_OFFSET_INVALID; 2651 priv->extract.qos_key_extract.key_info.ipv6_src_offset = 2652 IP_ADDRESS_OFFSET_INVALID; 2653 priv->extract.qos_key_extract.key_info.ipv6_dst_offset = 2654 IP_ADDRESS_OFFSET_INVALID; 2655 2656 for (i = 0; i < MAX_TCS; i++) { 2657 memset(&priv->extract.tc_key_extract[i], 0, 2658 sizeof(struct dpaa2_key_extract)); 2659 priv->extract.tc_extract_param[i] = 2660 (size_t)rte_malloc(NULL, 256, 64); 2661 if (!priv->extract.tc_extract_param[i]) { 2662 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow classificaiton", 2663 ret); 2664 goto init_err; 2665 } 2666 priv->extract.tc_key_extract[i].key_info.ipv4_src_offset = 2667 IP_ADDRESS_OFFSET_INVALID; 2668 priv->extract.tc_key_extract[i].key_info.ipv4_dst_offset = 2669 IP_ADDRESS_OFFSET_INVALID; 2670 priv->extract.tc_key_extract[i].key_info.ipv6_src_offset = 2671 IP_ADDRESS_OFFSET_INVALID; 2672 priv->extract.tc_key_extract[i].key_info.ipv6_dst_offset = 2673 IP_ADDRESS_OFFSET_INVALID; 2674 } 2675 2676 ret = dpni_set_max_frame_length(dpni_dev, CMD_PRI_LOW, priv->token, 2677 RTE_ETHER_MAX_LEN - RTE_ETHER_CRC_LEN 2678 + VLAN_TAG_SIZE); 2679 if (ret) { 2680 DPAA2_PMD_ERR("Unable to set mtu. check config"); 2681 goto init_err; 2682 } 2683 2684 /*TODO To enable soft parser support DPAA2 driver needs to integrate 2685 * with external entity to receive byte code for software sequence 2686 * and same will be offload to the H/W using MC interface. 2687 * Currently it is assumed that DPAA2 driver has byte code by some 2688 * mean and same if offloaded to H/W. 2689 */ 2690 if (getenv("DPAA2_ENABLE_SOFT_PARSER")) { 2691 WRIOP_SS_INITIALIZER(priv); 2692 ret = dpaa2_eth_load_wriop_soft_parser(priv, DPNI_SS_INGRESS); 2693 if (ret < 0) { 2694 DPAA2_PMD_ERR(" Error(%d) in loading softparser\n", 2695 ret); 2696 return ret; 2697 } 2698 2699 ret = dpaa2_eth_enable_wriop_soft_parser(priv, 2700 DPNI_SS_INGRESS); 2701 if (ret < 0) { 2702 DPAA2_PMD_ERR(" Error(%d) in enabling softparser\n", 2703 ret); 2704 return ret; 2705 } 2706 } 2707 RTE_LOG(INFO, PMD, "%s: netdev created\n", eth_dev->data->name); 2708 return 0; 2709 init_err: 2710 dpaa2_dev_uninit(eth_dev); 2711 return ret; 2712 } 2713 2714 static int 2715 dpaa2_dev_uninit(struct rte_eth_dev *eth_dev) 2716 { 2717 struct dpaa2_dev_priv *priv = eth_dev->data->dev_private; 2718 struct fsl_mc_io *dpni = (struct fsl_mc_io *)eth_dev->process_private; 2719 int i, ret; 2720 2721 PMD_INIT_FUNC_TRACE(); 2722 2723 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2724 return 0; 2725 2726 if (!dpni) { 2727 DPAA2_PMD_WARN("Already closed or not started"); 2728 return -1; 2729 } 2730 2731 dpaa2_dev_close(eth_dev); 2732 2733 dpaa2_free_rx_tx_queues(eth_dev); 2734 2735 /* Close the device at underlying layer*/ 2736 ret = dpni_close(dpni, CMD_PRI_LOW, priv->token); 2737 if (ret) { 2738 DPAA2_PMD_ERR( 2739 "Failure closing dpni device with err code %d", 2740 ret); 2741 } 2742 2743 /* Free the allocated memory for ethernet private data and dpni*/ 2744 priv->hw = NULL; 2745 eth_dev->process_private = NULL; 2746 rte_free(dpni); 2747 2748 for (i = 0; i < MAX_TCS; i++) 2749 rte_free((void *)(size_t)priv->extract.tc_extract_param[i]); 2750 2751 if (priv->extract.qos_extract_param) 2752 rte_free((void *)(size_t)priv->extract.qos_extract_param); 2753 2754 eth_dev->dev_ops = NULL; 2755 eth_dev->rx_pkt_burst = NULL; 2756 eth_dev->tx_pkt_burst = NULL; 2757 2758 DPAA2_PMD_INFO("%s: netdev deleted", eth_dev->data->name); 2759 return 0; 2760 } 2761 2762 static int 2763 rte_dpaa2_probe(struct rte_dpaa2_driver *dpaa2_drv, 2764 struct rte_dpaa2_device *dpaa2_dev) 2765 { 2766 struct rte_eth_dev *eth_dev; 2767 struct dpaa2_dev_priv *dev_priv; 2768 int diag; 2769 2770 if ((DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) > 2771 RTE_PKTMBUF_HEADROOM) { 2772 DPAA2_PMD_ERR( 2773 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA2 Annotation req(%d)", 2774 RTE_PKTMBUF_HEADROOM, 2775 DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE); 2776 2777 return -1; 2778 } 2779 2780 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 2781 eth_dev = rte_eth_dev_allocate(dpaa2_dev->device.name); 2782 if (!eth_dev) 2783 return -ENODEV; 2784 dev_priv = rte_zmalloc("ethdev private structure", 2785 sizeof(struct dpaa2_dev_priv), 2786 RTE_CACHE_LINE_SIZE); 2787 if (dev_priv == NULL) { 2788 DPAA2_PMD_CRIT( 2789 "Unable to allocate memory for private data"); 2790 rte_eth_dev_release_port(eth_dev); 2791 return -ENOMEM; 2792 } 2793 eth_dev->data->dev_private = (void *)dev_priv; 2794 /* Store a pointer to eth_dev in dev_private */ 2795 dev_priv->eth_dev = eth_dev; 2796 dev_priv->tx_conf_en = 0; 2797 } else { 2798 eth_dev = rte_eth_dev_attach_secondary(dpaa2_dev->device.name); 2799 if (!eth_dev) { 2800 DPAA2_PMD_DEBUG("returning enodev"); 2801 return -ENODEV; 2802 } 2803 } 2804 2805 eth_dev->device = &dpaa2_dev->device; 2806 2807 dpaa2_dev->eth_dev = eth_dev; 2808 eth_dev->data->rx_mbuf_alloc_failed = 0; 2809 2810 if (dpaa2_drv->drv_flags & RTE_DPAA2_DRV_INTR_LSC) 2811 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC; 2812 2813 /* Invoke PMD device initialization function */ 2814 diag = dpaa2_dev_init(eth_dev); 2815 if (diag == 0) { 2816 rte_eth_dev_probing_finish(eth_dev); 2817 return 0; 2818 } 2819 2820 rte_eth_dev_release_port(eth_dev); 2821 return diag; 2822 } 2823 2824 static int 2825 rte_dpaa2_remove(struct rte_dpaa2_device *dpaa2_dev) 2826 { 2827 struct rte_eth_dev *eth_dev; 2828 2829 eth_dev = dpaa2_dev->eth_dev; 2830 dpaa2_dev_uninit(eth_dev); 2831 2832 rte_eth_dev_release_port(eth_dev); 2833 2834 return 0; 2835 } 2836 2837 static struct rte_dpaa2_driver rte_dpaa2_pmd = { 2838 .drv_flags = RTE_DPAA2_DRV_INTR_LSC | RTE_DPAA2_DRV_IOVA_AS_VA, 2839 .drv_type = DPAA2_ETH, 2840 .probe = rte_dpaa2_probe, 2841 .remove = rte_dpaa2_remove, 2842 }; 2843 2844 RTE_PMD_REGISTER_DPAA2(net_dpaa2, rte_dpaa2_pmd); 2845 RTE_PMD_REGISTER_PARAM_STRING(net_dpaa2, 2846 DRIVER_LOOPBACK_MODE "=<int> " 2847 DRIVER_NO_PREFETCH_MODE "=<int>"); 2848 RTE_LOG_REGISTER(dpaa2_logtype_pmd, pmd.net.dpaa2, NOTICE); 2849