1 /* * SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved. 4 * Copyright 2016-2021 NXP 5 * 6 */ 7 8 #include <time.h> 9 #include <net/if.h> 10 11 #include <rte_mbuf.h> 12 #include <ethdev_driver.h> 13 #include <rte_malloc.h> 14 #include <rte_memcpy.h> 15 #include <rte_string_fns.h> 16 #include <rte_cycles.h> 17 #include <rte_kvargs.h> 18 #include <dev_driver.h> 19 #include <bus_fslmc_driver.h> 20 #include <rte_flow_driver.h> 21 #include "rte_dpaa2_mempool.h" 22 23 #include "dpaa2_pmd_logs.h" 24 #include <fslmc_vfio.h> 25 #include <dpaa2_hw_pvt.h> 26 #include <dpaa2_hw_mempool.h> 27 #include <dpaa2_hw_dpio.h> 28 #include <mc/fsl_dpmng.h> 29 #include "dpaa2_ethdev.h" 30 #include "dpaa2_sparser.h" 31 #include <fsl_qbman_debug.h> 32 33 #define DRIVER_LOOPBACK_MODE "drv_loopback" 34 #define DRIVER_NO_PREFETCH_MODE "drv_no_prefetch" 35 #define DRIVER_TX_CONF "drv_tx_conf" 36 #define DRIVER_ERROR_QUEUE "drv_err_queue" 37 #define CHECK_INTERVAL 100 /* 100ms */ 38 #define MAX_REPEAT_TIME 90 /* 9s (90 * 100ms) in total */ 39 40 /* Supported Rx offloads */ 41 static uint64_t dev_rx_offloads_sup = 42 RTE_ETH_RX_OFFLOAD_CHECKSUM | 43 RTE_ETH_RX_OFFLOAD_SCTP_CKSUM | 44 RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM | 45 RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM | 46 RTE_ETH_RX_OFFLOAD_VLAN_STRIP | 47 RTE_ETH_RX_OFFLOAD_VLAN_FILTER | 48 RTE_ETH_RX_OFFLOAD_TIMESTAMP; 49 50 /* Rx offloads which cannot be disabled */ 51 static uint64_t dev_rx_offloads_nodis = 52 RTE_ETH_RX_OFFLOAD_RSS_HASH | 53 RTE_ETH_RX_OFFLOAD_SCATTER; 54 55 /* Supported Tx offloads */ 56 static uint64_t dev_tx_offloads_sup = 57 RTE_ETH_TX_OFFLOAD_VLAN_INSERT | 58 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | 59 RTE_ETH_TX_OFFLOAD_UDP_CKSUM | 60 RTE_ETH_TX_OFFLOAD_TCP_CKSUM | 61 RTE_ETH_TX_OFFLOAD_SCTP_CKSUM | 62 RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM | 63 RTE_ETH_TX_OFFLOAD_MT_LOCKFREE | 64 RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE; 65 66 /* Tx offloads which cannot be disabled */ 67 static uint64_t dev_tx_offloads_nodis = 68 RTE_ETH_TX_OFFLOAD_MULTI_SEGS; 69 70 /* enable timestamp in mbuf */ 71 bool dpaa2_enable_ts[RTE_MAX_ETHPORTS]; 72 uint64_t dpaa2_timestamp_rx_dynflag; 73 int dpaa2_timestamp_dynfield_offset = -1; 74 75 /* Enable error queue */ 76 bool dpaa2_enable_err_queue; 77 78 #define MAX_NB_RX_DESC 11264 79 int total_nb_rx_desc; 80 81 int dpaa2_valid_dev; 82 struct rte_mempool *dpaa2_tx_sg_pool; 83 84 struct rte_dpaa2_xstats_name_off { 85 char name[RTE_ETH_XSTATS_NAME_SIZE]; 86 uint8_t page_id; /* dpni statistics page id */ 87 uint8_t stats_id; /* stats id in the given page */ 88 }; 89 90 static const struct rte_dpaa2_xstats_name_off dpaa2_xstats_strings[] = { 91 {"ingress_multicast_frames", 0, 2}, 92 {"ingress_multicast_bytes", 0, 3}, 93 {"ingress_broadcast_frames", 0, 4}, 94 {"ingress_broadcast_bytes", 0, 5}, 95 {"egress_multicast_frames", 1, 2}, 96 {"egress_multicast_bytes", 1, 3}, 97 {"egress_broadcast_frames", 1, 4}, 98 {"egress_broadcast_bytes", 1, 5}, 99 {"ingress_filtered_frames", 2, 0}, 100 {"ingress_discarded_frames", 2, 1}, 101 {"ingress_nobuffer_discards", 2, 2}, 102 {"egress_discarded_frames", 2, 3}, 103 {"egress_confirmed_frames", 2, 4}, 104 {"cgr_reject_frames", 4, 0}, 105 {"cgr_reject_bytes", 4, 1}, 106 }; 107 108 static struct rte_dpaa2_driver rte_dpaa2_pmd; 109 static int dpaa2_dev_link_update(struct rte_eth_dev *dev, 110 int wait_to_complete); 111 static int dpaa2_dev_set_link_up(struct rte_eth_dev *dev); 112 static int dpaa2_dev_set_link_down(struct rte_eth_dev *dev); 113 static int dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 114 115 static int 116 dpaa2_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 117 { 118 int ret; 119 struct dpaa2_dev_priv *priv = dev->data->dev_private; 120 struct fsl_mc_io *dpni = dev->process_private; 121 122 PMD_INIT_FUNC_TRACE(); 123 124 if (dpni == NULL) { 125 DPAA2_PMD_ERR("dpni is NULL"); 126 return -1; 127 } 128 129 if (on) 130 ret = dpni_add_vlan_id(dpni, CMD_PRI_LOW, priv->token, 131 vlan_id, 0, 0, 0); 132 else 133 ret = dpni_remove_vlan_id(dpni, CMD_PRI_LOW, 134 priv->token, vlan_id); 135 136 if (ret < 0) 137 DPAA2_PMD_ERR("ret = %d Unable to add/rem vlan %d hwid =%d", 138 ret, vlan_id, priv->hw_id); 139 140 return ret; 141 } 142 143 static int 144 dpaa2_vlan_offload_set(struct rte_eth_dev *dev, int mask) 145 { 146 struct dpaa2_dev_priv *priv = dev->data->dev_private; 147 struct fsl_mc_io *dpni = dev->process_private; 148 int ret = 0; 149 150 PMD_INIT_FUNC_TRACE(); 151 152 if (mask & RTE_ETH_VLAN_FILTER_MASK) { 153 /* VLAN Filter not available */ 154 if (!priv->max_vlan_filters) { 155 DPAA2_PMD_INFO("VLAN filter not available"); 156 return -ENOTSUP; 157 } 158 159 if (dev->data->dev_conf.rxmode.offloads & 160 RTE_ETH_RX_OFFLOAD_VLAN_FILTER) 161 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW, 162 priv->token, true); 163 else 164 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW, 165 priv->token, false); 166 if (ret < 0) 167 DPAA2_PMD_INFO("Unable to set vlan filter = %d", ret); 168 } 169 170 return ret; 171 } 172 173 static int 174 dpaa2_vlan_tpid_set(struct rte_eth_dev *dev, 175 enum rte_vlan_type vlan_type __rte_unused, 176 uint16_t tpid) 177 { 178 struct dpaa2_dev_priv *priv = dev->data->dev_private; 179 struct fsl_mc_io *dpni = dev->process_private; 180 int ret = -ENOTSUP; 181 182 PMD_INIT_FUNC_TRACE(); 183 184 /* nothing to be done for standard vlan tpids */ 185 if (tpid == 0x8100 || tpid == 0x88A8) 186 return 0; 187 188 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW, 189 priv->token, tpid); 190 if (ret < 0) 191 DPAA2_PMD_INFO("Unable to set vlan tpid = %d", ret); 192 /* if already configured tpids, remove them first */ 193 if (ret == -EBUSY) { 194 struct dpni_custom_tpid_cfg tpid_list = {0}; 195 196 ret = dpni_get_custom_tpid(dpni, CMD_PRI_LOW, 197 priv->token, &tpid_list); 198 if (ret < 0) 199 goto fail; 200 ret = dpni_remove_custom_tpid(dpni, CMD_PRI_LOW, 201 priv->token, tpid_list.tpid1); 202 if (ret < 0) 203 goto fail; 204 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW, 205 priv->token, tpid); 206 } 207 fail: 208 return ret; 209 } 210 211 static int 212 dpaa2_fw_version_get(struct rte_eth_dev *dev, 213 char *fw_version, 214 size_t fw_size) 215 { 216 int ret; 217 struct fsl_mc_io *dpni = dev->process_private; 218 struct mc_soc_version mc_plat_info = {0}; 219 struct mc_version mc_ver_info = {0}; 220 221 PMD_INIT_FUNC_TRACE(); 222 223 if (mc_get_soc_version(dpni, CMD_PRI_LOW, &mc_plat_info)) 224 DPAA2_PMD_WARN("\tmc_get_soc_version failed"); 225 226 if (mc_get_version(dpni, CMD_PRI_LOW, &mc_ver_info)) 227 DPAA2_PMD_WARN("\tmc_get_version failed"); 228 229 ret = snprintf(fw_version, fw_size, 230 "%x-%d.%d.%d", 231 mc_plat_info.svr, 232 mc_ver_info.major, 233 mc_ver_info.minor, 234 mc_ver_info.revision); 235 if (ret < 0) 236 return -EINVAL; 237 238 ret += 1; /* add the size of '\0' */ 239 if (fw_size < (size_t)ret) 240 return ret; 241 else 242 return 0; 243 } 244 245 static int 246 dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 247 { 248 struct dpaa2_dev_priv *priv = dev->data->dev_private; 249 250 PMD_INIT_FUNC_TRACE(); 251 252 dev_info->max_mac_addrs = priv->max_mac_filters; 253 dev_info->max_rx_pktlen = DPAA2_MAX_RX_PKT_LEN; 254 dev_info->min_rx_bufsize = DPAA2_MIN_RX_BUF_SIZE; 255 dev_info->max_rx_queues = (uint16_t)priv->nb_rx_queues; 256 dev_info->max_tx_queues = (uint16_t)priv->nb_tx_queues; 257 dev_info->rx_offload_capa = dev_rx_offloads_sup | 258 dev_rx_offloads_nodis; 259 dev_info->tx_offload_capa = dev_tx_offloads_sup | 260 dev_tx_offloads_nodis; 261 dev_info->speed_capa = RTE_ETH_LINK_SPEED_1G | 262 RTE_ETH_LINK_SPEED_2_5G | 263 RTE_ETH_LINK_SPEED_10G; 264 dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; 265 266 dev_info->max_hash_mac_addrs = 0; 267 dev_info->max_vfs = 0; 268 dev_info->max_vmdq_pools = RTE_ETH_16_POOLS; 269 dev_info->flow_type_rss_offloads = DPAA2_RSS_OFFLOAD_ALL; 270 271 dev_info->default_rxportconf.burst_size = dpaa2_dqrr_size; 272 /* same is rx size for best perf */ 273 dev_info->default_txportconf.burst_size = dpaa2_dqrr_size; 274 275 dev_info->default_rxportconf.nb_queues = 1; 276 dev_info->default_txportconf.nb_queues = 1; 277 dev_info->default_txportconf.ring_size = CONG_ENTER_TX_THRESHOLD; 278 dev_info->default_rxportconf.ring_size = DPAA2_RX_DEFAULT_NBDESC; 279 280 if (dpaa2_svr_family == SVR_LX2160A) { 281 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_25G | 282 RTE_ETH_LINK_SPEED_40G | 283 RTE_ETH_LINK_SPEED_50G | 284 RTE_ETH_LINK_SPEED_100G; 285 } 286 287 return 0; 288 } 289 290 static int 291 dpaa2_dev_rx_burst_mode_get(struct rte_eth_dev *dev, 292 __rte_unused uint16_t queue_id, 293 struct rte_eth_burst_mode *mode) 294 { 295 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 296 int ret = -EINVAL; 297 unsigned int i; 298 const struct burst_info { 299 uint64_t flags; 300 const char *output; 301 } rx_offload_map[] = { 302 {RTE_ETH_RX_OFFLOAD_CHECKSUM, " Checksum,"}, 303 {RTE_ETH_RX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"}, 304 {RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"}, 305 {RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM, " Outer UDP csum,"}, 306 {RTE_ETH_RX_OFFLOAD_VLAN_STRIP, " VLAN strip,"}, 307 {RTE_ETH_RX_OFFLOAD_VLAN_FILTER, " VLAN filter,"}, 308 {RTE_ETH_RX_OFFLOAD_TIMESTAMP, " Timestamp,"}, 309 {RTE_ETH_RX_OFFLOAD_RSS_HASH, " RSS,"}, 310 {RTE_ETH_RX_OFFLOAD_SCATTER, " Scattered,"} 311 }; 312 313 /* Update Rx offload info */ 314 for (i = 0; i < RTE_DIM(rx_offload_map); i++) { 315 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) { 316 snprintf(mode->info, sizeof(mode->info), "%s", 317 rx_offload_map[i].output); 318 ret = 0; 319 break; 320 } 321 } 322 return ret; 323 } 324 325 static int 326 dpaa2_dev_tx_burst_mode_get(struct rte_eth_dev *dev, 327 __rte_unused uint16_t queue_id, 328 struct rte_eth_burst_mode *mode) 329 { 330 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 331 int ret = -EINVAL; 332 unsigned int i; 333 const struct burst_info { 334 uint64_t flags; 335 const char *output; 336 } tx_offload_map[] = { 337 {RTE_ETH_TX_OFFLOAD_VLAN_INSERT, " VLAN Insert,"}, 338 {RTE_ETH_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"}, 339 {RTE_ETH_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"}, 340 {RTE_ETH_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"}, 341 {RTE_ETH_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"}, 342 {RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"}, 343 {RTE_ETH_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"}, 344 {RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"}, 345 {RTE_ETH_TX_OFFLOAD_MULTI_SEGS, " Scattered,"} 346 }; 347 348 /* Update Tx offload info */ 349 for (i = 0; i < RTE_DIM(tx_offload_map); i++) { 350 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) { 351 snprintf(mode->info, sizeof(mode->info), "%s", 352 tx_offload_map[i].output); 353 ret = 0; 354 break; 355 } 356 } 357 return ret; 358 } 359 360 static int 361 dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev) 362 { 363 struct dpaa2_dev_priv *priv = dev->data->dev_private; 364 uint16_t dist_idx; 365 uint32_t vq_id; 366 uint8_t num_rxqueue_per_tc; 367 struct dpaa2_queue *mc_q, *mcq; 368 uint32_t tot_queues; 369 int i; 370 struct dpaa2_queue *dpaa2_q; 371 372 PMD_INIT_FUNC_TRACE(); 373 374 num_rxqueue_per_tc = (priv->nb_rx_queues / priv->num_rx_tc); 375 if (priv->flags & DPAA2_TX_CONF_ENABLE) 376 tot_queues = priv->nb_rx_queues + 2 * priv->nb_tx_queues; 377 else 378 tot_queues = priv->nb_rx_queues + priv->nb_tx_queues; 379 mc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues, 380 RTE_CACHE_LINE_SIZE); 381 if (!mc_q) { 382 DPAA2_PMD_ERR("Memory allocation failed for rx/tx queues"); 383 return -1; 384 } 385 386 for (i = 0; i < priv->nb_rx_queues; i++) { 387 mc_q->eth_data = dev->data; 388 priv->rx_vq[i] = mc_q++; 389 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i]; 390 dpaa2_q->q_storage = rte_malloc("dq_storage", 391 sizeof(struct queue_storage_info_t), 392 RTE_CACHE_LINE_SIZE); 393 if (!dpaa2_q->q_storage) 394 goto fail; 395 396 memset(dpaa2_q->q_storage, 0, 397 sizeof(struct queue_storage_info_t)); 398 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage)) 399 goto fail; 400 } 401 402 if (dpaa2_enable_err_queue) { 403 priv->rx_err_vq = rte_zmalloc("dpni_rx_err", 404 sizeof(struct dpaa2_queue), 0); 405 if (!priv->rx_err_vq) 406 goto fail; 407 408 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq; 409 dpaa2_q->q_storage = rte_malloc("err_dq_storage", 410 sizeof(struct queue_storage_info_t) * 411 RTE_MAX_LCORE, 412 RTE_CACHE_LINE_SIZE); 413 if (!dpaa2_q->q_storage) 414 goto fail; 415 416 memset(dpaa2_q->q_storage, 0, 417 sizeof(struct queue_storage_info_t)); 418 for (i = 0; i < RTE_MAX_LCORE; i++) 419 if (dpaa2_alloc_dq_storage(&dpaa2_q->q_storage[i])) 420 goto fail; 421 } 422 423 for (i = 0; i < priv->nb_tx_queues; i++) { 424 mc_q->eth_data = dev->data; 425 mc_q->flow_id = 0xffff; 426 priv->tx_vq[i] = mc_q++; 427 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; 428 dpaa2_q->cscn = rte_malloc(NULL, 429 sizeof(struct qbman_result), 16); 430 if (!dpaa2_q->cscn) 431 goto fail_tx; 432 } 433 434 if (priv->flags & DPAA2_TX_CONF_ENABLE) { 435 /*Setup tx confirmation queues*/ 436 for (i = 0; i < priv->nb_tx_queues; i++) { 437 mc_q->eth_data = dev->data; 438 mc_q->tc_index = i; 439 mc_q->flow_id = 0; 440 priv->tx_conf_vq[i] = mc_q++; 441 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i]; 442 dpaa2_q->q_storage = 443 rte_malloc("dq_storage", 444 sizeof(struct queue_storage_info_t), 445 RTE_CACHE_LINE_SIZE); 446 if (!dpaa2_q->q_storage) 447 goto fail_tx_conf; 448 449 memset(dpaa2_q->q_storage, 0, 450 sizeof(struct queue_storage_info_t)); 451 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage)) 452 goto fail_tx_conf; 453 } 454 } 455 456 vq_id = 0; 457 for (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) { 458 mcq = (struct dpaa2_queue *)priv->rx_vq[vq_id]; 459 mcq->tc_index = dist_idx / num_rxqueue_per_tc; 460 mcq->flow_id = dist_idx % num_rxqueue_per_tc; 461 vq_id++; 462 } 463 464 return 0; 465 fail_tx_conf: 466 i -= 1; 467 while (i >= 0) { 468 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i]; 469 rte_free(dpaa2_q->q_storage); 470 priv->tx_conf_vq[i--] = NULL; 471 } 472 i = priv->nb_tx_queues; 473 fail_tx: 474 i -= 1; 475 while (i >= 0) { 476 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; 477 rte_free(dpaa2_q->cscn); 478 priv->tx_vq[i--] = NULL; 479 } 480 i = priv->nb_rx_queues; 481 fail: 482 i -= 1; 483 mc_q = priv->rx_vq[0]; 484 while (i >= 0) { 485 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i]; 486 dpaa2_free_dq_storage(dpaa2_q->q_storage); 487 rte_free(dpaa2_q->q_storage); 488 priv->rx_vq[i--] = NULL; 489 } 490 491 if (dpaa2_enable_err_queue) { 492 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq; 493 if (dpaa2_q->q_storage) 494 dpaa2_free_dq_storage(dpaa2_q->q_storage); 495 rte_free(dpaa2_q->q_storage); 496 } 497 498 rte_free(mc_q); 499 return -1; 500 } 501 502 static void 503 dpaa2_free_rx_tx_queues(struct rte_eth_dev *dev) 504 { 505 struct dpaa2_dev_priv *priv = dev->data->dev_private; 506 struct dpaa2_queue *dpaa2_q; 507 int i; 508 509 PMD_INIT_FUNC_TRACE(); 510 511 /* Queue allocation base */ 512 if (priv->rx_vq[0]) { 513 /* cleaning up queue storage */ 514 for (i = 0; i < priv->nb_rx_queues; i++) { 515 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i]; 516 rte_free(dpaa2_q->q_storage); 517 } 518 /* cleanup tx queue cscn */ 519 for (i = 0; i < priv->nb_tx_queues; i++) { 520 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; 521 rte_free(dpaa2_q->cscn); 522 } 523 if (priv->flags & DPAA2_TX_CONF_ENABLE) { 524 /* cleanup tx conf queue storage */ 525 for (i = 0; i < priv->nb_tx_queues; i++) { 526 dpaa2_q = (struct dpaa2_queue *) 527 priv->tx_conf_vq[i]; 528 rte_free(dpaa2_q->q_storage); 529 } 530 } 531 /*free memory for all queues (RX+TX) */ 532 rte_free(priv->rx_vq[0]); 533 priv->rx_vq[0] = NULL; 534 } 535 } 536 537 static int 538 dpaa2_eth_dev_configure(struct rte_eth_dev *dev) 539 { 540 struct dpaa2_dev_priv *priv = dev->data->dev_private; 541 struct fsl_mc_io *dpni = dev->process_private; 542 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 543 uint64_t rx_offloads = eth_conf->rxmode.offloads; 544 uint64_t tx_offloads = eth_conf->txmode.offloads; 545 int rx_l3_csum_offload = false; 546 int rx_l4_csum_offload = false; 547 int tx_l3_csum_offload = false; 548 int tx_l4_csum_offload = false; 549 int ret, tc_index; 550 uint32_t max_rx_pktlen; 551 552 PMD_INIT_FUNC_TRACE(); 553 554 /* Rx offloads which are enabled by default */ 555 if (dev_rx_offloads_nodis & ~rx_offloads) { 556 DPAA2_PMD_INFO( 557 "Some of rx offloads enabled by default - requested 0x%" PRIx64 558 " fixed are 0x%" PRIx64, 559 rx_offloads, dev_rx_offloads_nodis); 560 } 561 562 /* Tx offloads which are enabled by default */ 563 if (dev_tx_offloads_nodis & ~tx_offloads) { 564 DPAA2_PMD_INFO( 565 "Some of tx offloads enabled by default - requested 0x%" PRIx64 566 " fixed are 0x%" PRIx64, 567 tx_offloads, dev_tx_offloads_nodis); 568 } 569 570 max_rx_pktlen = eth_conf->rxmode.mtu + RTE_ETHER_HDR_LEN + 571 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE; 572 if (max_rx_pktlen <= DPAA2_MAX_RX_PKT_LEN) { 573 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, 574 priv->token, max_rx_pktlen - RTE_ETHER_CRC_LEN); 575 if (ret != 0) { 576 DPAA2_PMD_ERR("Unable to set mtu. check config"); 577 return ret; 578 } 579 DPAA2_PMD_INFO("MTU configured for the device: %d", 580 dev->data->mtu); 581 } else { 582 return -1; 583 } 584 585 if (eth_conf->rxmode.mq_mode == RTE_ETH_MQ_RX_RSS) { 586 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) { 587 ret = dpaa2_setup_flow_dist(dev, 588 eth_conf->rx_adv_conf.rss_conf.rss_hf, 589 tc_index); 590 if (ret) { 591 DPAA2_PMD_ERR( 592 "Unable to set flow distribution on tc%d." 593 "Check queue config", tc_index); 594 return ret; 595 } 596 } 597 } 598 599 if (rx_offloads & RTE_ETH_RX_OFFLOAD_IPV4_CKSUM) 600 rx_l3_csum_offload = true; 601 602 if ((rx_offloads & RTE_ETH_RX_OFFLOAD_UDP_CKSUM) || 603 (rx_offloads & RTE_ETH_RX_OFFLOAD_TCP_CKSUM) || 604 (rx_offloads & RTE_ETH_RX_OFFLOAD_SCTP_CKSUM)) 605 rx_l4_csum_offload = true; 606 607 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 608 DPNI_OFF_RX_L3_CSUM, rx_l3_csum_offload); 609 if (ret) { 610 DPAA2_PMD_ERR("Error to set RX l3 csum:Error = %d", ret); 611 return ret; 612 } 613 614 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 615 DPNI_OFF_RX_L4_CSUM, rx_l4_csum_offload); 616 if (ret) { 617 DPAA2_PMD_ERR("Error to get RX l4 csum:Error = %d", ret); 618 return ret; 619 } 620 621 #if !defined(RTE_LIBRTE_IEEE1588) 622 if (rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) 623 #endif 624 { 625 ret = rte_mbuf_dyn_rx_timestamp_register( 626 &dpaa2_timestamp_dynfield_offset, 627 &dpaa2_timestamp_rx_dynflag); 628 if (ret != 0) { 629 DPAA2_PMD_ERR("Error to register timestamp field/flag"); 630 return -rte_errno; 631 } 632 dpaa2_enable_ts[dev->data->port_id] = true; 633 } 634 635 if (tx_offloads & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM) 636 tx_l3_csum_offload = true; 637 638 if ((tx_offloads & RTE_ETH_TX_OFFLOAD_UDP_CKSUM) || 639 (tx_offloads & RTE_ETH_TX_OFFLOAD_TCP_CKSUM) || 640 (tx_offloads & RTE_ETH_TX_OFFLOAD_SCTP_CKSUM)) 641 tx_l4_csum_offload = true; 642 643 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 644 DPNI_OFF_TX_L3_CSUM, tx_l3_csum_offload); 645 if (ret) { 646 DPAA2_PMD_ERR("Error to set TX l3 csum:Error = %d", ret); 647 return ret; 648 } 649 650 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 651 DPNI_OFF_TX_L4_CSUM, tx_l4_csum_offload); 652 if (ret) { 653 DPAA2_PMD_ERR("Error to get TX l4 csum:Error = %d", ret); 654 return ret; 655 } 656 657 /* Enabling hash results in FD requires setting DPNI_FLCTYPE_HASH in 658 * dpni_set_offload API. Setting this FLCTYPE for DPNI sets the FD[SC] 659 * to 0 for LS2 in the hardware thus disabling data/annotation 660 * stashing. For LX2 this is fixed in hardware and thus hash result and 661 * parse results can be received in FD using this option. 662 */ 663 if (dpaa2_svr_family == SVR_LX2160A) { 664 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 665 DPNI_FLCTYPE_HASH, true); 666 if (ret) { 667 DPAA2_PMD_ERR("Error setting FLCTYPE: Err = %d", ret); 668 return ret; 669 } 670 } 671 672 if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) 673 dpaa2_vlan_offload_set(dev, RTE_ETH_VLAN_FILTER_MASK); 674 675 if (eth_conf->lpbk_mode) { 676 ret = dpaa2_dev_recycle_config(dev); 677 if (ret) { 678 DPAA2_PMD_ERR("Error to configure %s to recycle port.", 679 dev->data->name); 680 681 return ret; 682 } 683 } else { 684 /** User may disable loopback mode by calling 685 * "dev_configure" with lpbk_mode cleared. 686 * No matter the port was configured recycle or not, 687 * recycle de-configure is called here. 688 * If port is not recycled, the de-configure will return directly. 689 */ 690 ret = dpaa2_dev_recycle_deconfig(dev); 691 if (ret) { 692 DPAA2_PMD_ERR("Error to de-configure recycle port %s.", 693 dev->data->name); 694 695 return ret; 696 } 697 } 698 699 dpaa2_tm_init(dev); 700 701 return 0; 702 } 703 704 /* Function to setup RX flow information. It contains traffic class ID, 705 * flow ID, destination configuration etc. 706 */ 707 static int 708 dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev, 709 uint16_t rx_queue_id, 710 uint16_t nb_rx_desc, 711 unsigned int socket_id __rte_unused, 712 const struct rte_eth_rxconf *rx_conf, 713 struct rte_mempool *mb_pool) 714 { 715 struct dpaa2_dev_priv *priv = dev->data->dev_private; 716 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 717 struct dpaa2_queue *dpaa2_q; 718 struct dpni_queue cfg; 719 uint8_t options = 0; 720 uint8_t flow_id; 721 uint32_t bpid; 722 int i, ret; 723 724 PMD_INIT_FUNC_TRACE(); 725 726 DPAA2_PMD_DEBUG("dev =%p, queue =%d, pool = %p, conf =%p", 727 dev, rx_queue_id, mb_pool, rx_conf); 728 729 total_nb_rx_desc += nb_rx_desc; 730 if (total_nb_rx_desc > MAX_NB_RX_DESC) { 731 DPAA2_PMD_WARN("\nTotal nb_rx_desc exceeds %d limit. Please use Normal buffers", 732 MAX_NB_RX_DESC); 733 DPAA2_PMD_WARN("To use Normal buffers, run 'export DPNI_NORMAL_BUF=1' before running dynamic_dpl.sh script"); 734 } 735 736 /* Rx deferred start is not supported */ 737 if (rx_conf->rx_deferred_start) { 738 DPAA2_PMD_ERR("%p:Rx deferred start not supported", 739 (void *)dev); 740 return -EINVAL; 741 } 742 743 if (!priv->bp_list || priv->bp_list->mp != mb_pool) { 744 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 745 ret = rte_dpaa2_bpid_info_init(mb_pool); 746 if (ret) 747 return ret; 748 } 749 bpid = mempool_to_bpid(mb_pool); 750 ret = dpaa2_attach_bp_list(priv, dpni, 751 rte_dpaa2_bpid_info[bpid].bp_list); 752 if (ret) 753 return ret; 754 } 755 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id]; 756 dpaa2_q->mb_pool = mb_pool; /**< mbuf pool to populate RX ring. */ 757 dpaa2_q->bp_array = rte_dpaa2_bpid_info; 758 dpaa2_q->nb_desc = UINT16_MAX; 759 dpaa2_q->offloads = rx_conf->offloads; 760 761 /*Get the flow id from given VQ id*/ 762 flow_id = dpaa2_q->flow_id; 763 memset(&cfg, 0, sizeof(struct dpni_queue)); 764 765 options = options | DPNI_QUEUE_OPT_USER_CTX; 766 cfg.user_context = (size_t)(dpaa2_q); 767 768 /* check if a private cgr available. */ 769 for (i = 0; i < priv->max_cgs; i++) { 770 if (!priv->cgid_in_use[i]) { 771 priv->cgid_in_use[i] = 1; 772 break; 773 } 774 } 775 776 if (i < priv->max_cgs) { 777 options |= DPNI_QUEUE_OPT_SET_CGID; 778 cfg.cgid = i; 779 dpaa2_q->cgid = cfg.cgid; 780 } else { 781 dpaa2_q->cgid = 0xff; 782 } 783 784 /*if ls2088 or rev2 device, enable the stashing */ 785 786 if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) { 787 options |= DPNI_QUEUE_OPT_FLC; 788 cfg.flc.stash_control = true; 789 cfg.flc.value &= 0xFFFFFFFFFFFFFFC0; 790 /* 00 00 00 - last 6 bit represent annotation, context stashing, 791 * data stashing setting 01 01 00 (0x14) 792 * (in following order ->DS AS CS) 793 * to enable 1 line data, 1 line annotation. 794 * For LX2, this setting should be 01 00 00 (0x10) 795 */ 796 if ((dpaa2_svr_family & 0xffff0000) == SVR_LX2160A) 797 cfg.flc.value |= 0x10; 798 else 799 cfg.flc.value |= 0x14; 800 } 801 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX, 802 dpaa2_q->tc_index, flow_id, options, &cfg); 803 if (ret) { 804 DPAA2_PMD_ERR("Error in setting the rx flow: = %d", ret); 805 return -1; 806 } 807 808 if (!(priv->flags & DPAA2_RX_TAILDROP_OFF)) { 809 struct dpni_taildrop taildrop; 810 811 taildrop.enable = 1; 812 dpaa2_q->nb_desc = nb_rx_desc; 813 /* Private CGR will use tail drop length as nb_rx_desc. 814 * for rest cases we can use standard byte based tail drop. 815 * There is no HW restriction, but number of CGRs are limited, 816 * hence this restriction is placed. 817 */ 818 if (dpaa2_q->cgid != 0xff) { 819 /*enabling per rx queue congestion control */ 820 taildrop.threshold = nb_rx_desc; 821 taildrop.units = DPNI_CONGESTION_UNIT_FRAMES; 822 taildrop.oal = 0; 823 DPAA2_PMD_DEBUG("Enabling CG Tail Drop on queue = %d", 824 rx_queue_id); 825 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token, 826 DPNI_CP_CONGESTION_GROUP, 827 DPNI_QUEUE_RX, 828 dpaa2_q->tc_index, 829 dpaa2_q->cgid, &taildrop); 830 } else { 831 /*enabling per rx queue congestion control */ 832 taildrop.threshold = CONG_THRESHOLD_RX_BYTES_Q; 833 taildrop.units = DPNI_CONGESTION_UNIT_BYTES; 834 taildrop.oal = CONG_RX_OAL; 835 DPAA2_PMD_DEBUG("Enabling Byte based Drop on queue= %d", 836 rx_queue_id); 837 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token, 838 DPNI_CP_QUEUE, DPNI_QUEUE_RX, 839 dpaa2_q->tc_index, flow_id, 840 &taildrop); 841 } 842 if (ret) { 843 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)", 844 ret); 845 return -1; 846 } 847 } else { /* Disable tail Drop */ 848 struct dpni_taildrop taildrop = {0}; 849 DPAA2_PMD_INFO("Tail drop is disabled on queue"); 850 851 taildrop.enable = 0; 852 if (dpaa2_q->cgid != 0xff) { 853 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token, 854 DPNI_CP_CONGESTION_GROUP, DPNI_QUEUE_RX, 855 dpaa2_q->tc_index, 856 dpaa2_q->cgid, &taildrop); 857 } else { 858 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token, 859 DPNI_CP_QUEUE, DPNI_QUEUE_RX, 860 dpaa2_q->tc_index, flow_id, &taildrop); 861 } 862 if (ret) { 863 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)", 864 ret); 865 return -1; 866 } 867 } 868 869 dev->data->rx_queues[rx_queue_id] = dpaa2_q; 870 return 0; 871 } 872 873 static int 874 dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev, 875 uint16_t tx_queue_id, 876 uint16_t nb_tx_desc, 877 unsigned int socket_id __rte_unused, 878 const struct rte_eth_txconf *tx_conf) 879 { 880 struct dpaa2_dev_priv *priv = dev->data->dev_private; 881 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *) 882 priv->tx_vq[tx_queue_id]; 883 struct dpaa2_queue *dpaa2_tx_conf_q = (struct dpaa2_queue *) 884 priv->tx_conf_vq[tx_queue_id]; 885 struct fsl_mc_io *dpni = dev->process_private; 886 struct dpni_queue tx_conf_cfg; 887 struct dpni_queue tx_flow_cfg; 888 uint8_t options = 0, flow_id; 889 uint16_t channel_id; 890 struct dpni_queue_id qid; 891 uint32_t tc_id; 892 int ret; 893 894 PMD_INIT_FUNC_TRACE(); 895 896 /* Tx deferred start is not supported */ 897 if (tx_conf->tx_deferred_start) { 898 DPAA2_PMD_ERR("%p:Tx deferred start not supported", 899 (void *)dev); 900 return -EINVAL; 901 } 902 903 dpaa2_q->nb_desc = UINT16_MAX; 904 dpaa2_q->offloads = tx_conf->offloads; 905 906 /* Return if queue already configured */ 907 if (dpaa2_q->flow_id != 0xffff) { 908 dev->data->tx_queues[tx_queue_id] = dpaa2_q; 909 return 0; 910 } 911 912 memset(&tx_conf_cfg, 0, sizeof(struct dpni_queue)); 913 memset(&tx_flow_cfg, 0, sizeof(struct dpni_queue)); 914 915 if (tx_queue_id == 0) { 916 /*Set tx-conf and error configuration*/ 917 if (priv->flags & DPAA2_TX_CONF_ENABLE) 918 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW, 919 priv->token, 920 DPNI_CONF_AFFINE); 921 else 922 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW, 923 priv->token, 924 DPNI_CONF_DISABLE); 925 if (ret) { 926 DPAA2_PMD_ERR("Error in set tx conf mode settings: " 927 "err=%d", ret); 928 return -1; 929 } 930 } 931 932 tc_id = tx_queue_id % priv->num_tx_tc; 933 channel_id = (uint8_t)(tx_queue_id / priv->num_tx_tc) % priv->num_channels; 934 flow_id = 0; 935 936 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX, 937 ((channel_id << 8) | tc_id), flow_id, options, &tx_flow_cfg); 938 if (ret) { 939 DPAA2_PMD_ERR("Error in setting the tx flow: " 940 "tc_id=%d, flow=%d err=%d", 941 tc_id, flow_id, ret); 942 return -1; 943 } 944 945 dpaa2_q->flow_id = flow_id; 946 947 dpaa2_q->tc_index = tc_id; 948 949 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token, 950 DPNI_QUEUE_TX, ((channel_id << 8) | dpaa2_q->tc_index), 951 dpaa2_q->flow_id, &tx_flow_cfg, &qid); 952 if (ret) { 953 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret); 954 return -1; 955 } 956 dpaa2_q->fqid = qid.fqid; 957 958 if (!(priv->flags & DPAA2_TX_CGR_OFF)) { 959 struct dpni_congestion_notification_cfg cong_notif_cfg = {0}; 960 961 dpaa2_q->nb_desc = nb_tx_desc; 962 963 cong_notif_cfg.units = DPNI_CONGESTION_UNIT_FRAMES; 964 cong_notif_cfg.threshold_entry = nb_tx_desc; 965 /* Notify that the queue is not congested when the data in 966 * the queue is below this threshold.(90% of value) 967 */ 968 cong_notif_cfg.threshold_exit = (nb_tx_desc * 9) / 10; 969 cong_notif_cfg.message_ctx = 0; 970 cong_notif_cfg.message_iova = 971 (size_t)DPAA2_VADDR_TO_IOVA(dpaa2_q->cscn); 972 cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE; 973 cong_notif_cfg.notification_mode = 974 DPNI_CONG_OPT_WRITE_MEM_ON_ENTER | 975 DPNI_CONG_OPT_WRITE_MEM_ON_EXIT | 976 DPNI_CONG_OPT_COHERENT_WRITE; 977 cong_notif_cfg.cg_point = DPNI_CP_QUEUE; 978 979 ret = dpni_set_congestion_notification(dpni, CMD_PRI_LOW, 980 priv->token, 981 DPNI_QUEUE_TX, 982 ((channel_id << 8) | tc_id), 983 &cong_notif_cfg); 984 if (ret) { 985 DPAA2_PMD_ERR( 986 "Error in setting tx congestion notification: " 987 "err=%d", ret); 988 return -ret; 989 } 990 } 991 dpaa2_q->cb_eqresp_free = dpaa2_dev_free_eqresp_buf; 992 dev->data->tx_queues[tx_queue_id] = dpaa2_q; 993 994 if (priv->flags & DPAA2_TX_CONF_ENABLE) { 995 dpaa2_q->tx_conf_queue = dpaa2_tx_conf_q; 996 options = options | DPNI_QUEUE_OPT_USER_CTX; 997 tx_conf_cfg.user_context = (size_t)(dpaa2_q); 998 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, 999 DPNI_QUEUE_TX_CONFIRM, ((channel_id << 8) | dpaa2_tx_conf_q->tc_index), 1000 dpaa2_tx_conf_q->flow_id, options, &tx_conf_cfg); 1001 if (ret) { 1002 DPAA2_PMD_ERR("Error in setting the tx conf flow: " 1003 "tc_index=%d, flow=%d err=%d", 1004 dpaa2_tx_conf_q->tc_index, 1005 dpaa2_tx_conf_q->flow_id, ret); 1006 return -1; 1007 } 1008 1009 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token, 1010 DPNI_QUEUE_TX_CONFIRM, ((channel_id << 8) | dpaa2_tx_conf_q->tc_index), 1011 dpaa2_tx_conf_q->flow_id, &tx_conf_cfg, &qid); 1012 if (ret) { 1013 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret); 1014 return -1; 1015 } 1016 dpaa2_tx_conf_q->fqid = qid.fqid; 1017 } 1018 return 0; 1019 } 1020 1021 static void 1022 dpaa2_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t rx_queue_id) 1023 { 1024 struct dpaa2_queue *dpaa2_q = dev->data->rx_queues[rx_queue_id]; 1025 struct dpaa2_dev_priv *priv = dpaa2_q->eth_data->dev_private; 1026 struct fsl_mc_io *dpni = 1027 (struct fsl_mc_io *)priv->eth_dev->process_private; 1028 uint8_t options = 0; 1029 int ret; 1030 struct dpni_queue cfg; 1031 1032 memset(&cfg, 0, sizeof(struct dpni_queue)); 1033 PMD_INIT_FUNC_TRACE(); 1034 1035 total_nb_rx_desc -= dpaa2_q->nb_desc; 1036 1037 if (dpaa2_q->cgid != 0xff) { 1038 options = DPNI_QUEUE_OPT_CLEAR_CGID; 1039 cfg.cgid = dpaa2_q->cgid; 1040 1041 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, 1042 DPNI_QUEUE_RX, 1043 dpaa2_q->tc_index, dpaa2_q->flow_id, 1044 options, &cfg); 1045 if (ret) 1046 DPAA2_PMD_ERR("Unable to clear CGR from q=%u err=%d", 1047 dpaa2_q->fqid, ret); 1048 priv->cgid_in_use[dpaa2_q->cgid] = 0; 1049 dpaa2_q->cgid = 0xff; 1050 } 1051 } 1052 1053 static uint32_t 1054 dpaa2_dev_rx_queue_count(void *rx_queue) 1055 { 1056 int32_t ret; 1057 struct dpaa2_queue *dpaa2_q; 1058 struct qbman_swp *swp; 1059 struct qbman_fq_query_np_rslt state; 1060 uint32_t frame_cnt = 0; 1061 1062 if (unlikely(!DPAA2_PER_LCORE_DPIO)) { 1063 ret = dpaa2_affine_qbman_swp(); 1064 if (ret) { 1065 DPAA2_PMD_ERR( 1066 "Failed to allocate IO portal, tid: %d\n", 1067 rte_gettid()); 1068 return -EINVAL; 1069 } 1070 } 1071 swp = DPAA2_PER_LCORE_PORTAL; 1072 1073 dpaa2_q = rx_queue; 1074 1075 if (qbman_fq_query_state(swp, dpaa2_q->fqid, &state) == 0) { 1076 frame_cnt = qbman_fq_state_frame_count(&state); 1077 DPAA2_PMD_DP_DEBUG("RX frame count for q(%p) is %u", 1078 rx_queue, frame_cnt); 1079 } 1080 return frame_cnt; 1081 } 1082 1083 static const uint32_t * 1084 dpaa2_supported_ptypes_get(struct rte_eth_dev *dev, size_t *no_of_elements) 1085 { 1086 static const uint32_t ptypes[] = { 1087 /*todo -= add more types */ 1088 RTE_PTYPE_L2_ETHER, 1089 RTE_PTYPE_L3_IPV4, 1090 RTE_PTYPE_L3_IPV4_EXT, 1091 RTE_PTYPE_L3_IPV6, 1092 RTE_PTYPE_L3_IPV6_EXT, 1093 RTE_PTYPE_L4_TCP, 1094 RTE_PTYPE_L4_UDP, 1095 RTE_PTYPE_L4_SCTP, 1096 RTE_PTYPE_L4_ICMP, 1097 }; 1098 1099 if (dev->rx_pkt_burst == dpaa2_dev_prefetch_rx || 1100 dev->rx_pkt_burst == dpaa2_dev_rx || 1101 dev->rx_pkt_burst == dpaa2_dev_loopback_rx) { 1102 *no_of_elements = RTE_DIM(ptypes); 1103 return ptypes; 1104 } 1105 return NULL; 1106 } 1107 1108 /** 1109 * Dpaa2 link Interrupt handler 1110 * 1111 * @param param 1112 * The address of parameter (struct rte_eth_dev *) registered before. 1113 * 1114 * @return 1115 * void 1116 */ 1117 static void 1118 dpaa2_interrupt_handler(void *param) 1119 { 1120 struct rte_eth_dev *dev = param; 1121 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1122 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1123 int ret; 1124 int irq_index = DPNI_IRQ_INDEX; 1125 unsigned int status = 0, clear = 0; 1126 1127 PMD_INIT_FUNC_TRACE(); 1128 1129 if (dpni == NULL) { 1130 DPAA2_PMD_ERR("dpni is NULL"); 1131 return; 1132 } 1133 1134 ret = dpni_get_irq_status(dpni, CMD_PRI_LOW, priv->token, 1135 irq_index, &status); 1136 if (unlikely(ret)) { 1137 DPAA2_PMD_ERR("Can't get irq status (err %d)", ret); 1138 clear = 0xffffffff; 1139 goto out; 1140 } 1141 1142 if (status & DPNI_IRQ_EVENT_LINK_CHANGED) { 1143 clear = DPNI_IRQ_EVENT_LINK_CHANGED; 1144 dpaa2_dev_link_update(dev, 0); 1145 /* calling all the apps registered for link status event */ 1146 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL); 1147 } 1148 out: 1149 ret = dpni_clear_irq_status(dpni, CMD_PRI_LOW, priv->token, 1150 irq_index, clear); 1151 if (unlikely(ret)) 1152 DPAA2_PMD_ERR("Can't clear irq status (err %d)", ret); 1153 } 1154 1155 static int 1156 dpaa2_eth_setup_irqs(struct rte_eth_dev *dev, int enable) 1157 { 1158 int err = 0; 1159 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1160 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1161 int irq_index = DPNI_IRQ_INDEX; 1162 unsigned int mask = DPNI_IRQ_EVENT_LINK_CHANGED; 1163 1164 PMD_INIT_FUNC_TRACE(); 1165 1166 err = dpni_set_irq_mask(dpni, CMD_PRI_LOW, priv->token, 1167 irq_index, mask); 1168 if (err < 0) { 1169 DPAA2_PMD_ERR("Error: dpni_set_irq_mask():%d (%s)", err, 1170 strerror(-err)); 1171 return err; 1172 } 1173 1174 err = dpni_set_irq_enable(dpni, CMD_PRI_LOW, priv->token, 1175 irq_index, enable); 1176 if (err < 0) 1177 DPAA2_PMD_ERR("Error: dpni_set_irq_enable():%d (%s)", err, 1178 strerror(-err)); 1179 1180 return err; 1181 } 1182 1183 static int 1184 dpaa2_dev_start(struct rte_eth_dev *dev) 1185 { 1186 struct rte_device *rdev = dev->device; 1187 struct rte_dpaa2_device *dpaa2_dev; 1188 struct rte_eth_dev_data *data = dev->data; 1189 struct dpaa2_dev_priv *priv = data->dev_private; 1190 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1191 struct dpni_queue cfg; 1192 struct dpni_error_cfg err_cfg; 1193 struct dpni_queue_id qid; 1194 struct dpaa2_queue *dpaa2_q; 1195 int ret, i; 1196 struct rte_intr_handle *intr_handle; 1197 1198 dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device); 1199 intr_handle = dpaa2_dev->intr_handle; 1200 1201 PMD_INIT_FUNC_TRACE(); 1202 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token); 1203 if (ret) { 1204 DPAA2_PMD_ERR("Failure in enabling dpni %d device: err=%d", 1205 priv->hw_id, ret); 1206 return ret; 1207 } 1208 1209 /* Power up the phy. Needed to make the link go UP */ 1210 dpaa2_dev_set_link_up(dev); 1211 1212 for (i = 0; i < data->nb_rx_queues; i++) { 1213 dpaa2_q = (struct dpaa2_queue *)data->rx_queues[i]; 1214 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token, 1215 DPNI_QUEUE_RX, dpaa2_q->tc_index, 1216 dpaa2_q->flow_id, &cfg, &qid); 1217 if (ret) { 1218 DPAA2_PMD_ERR("Error in getting flow information: " 1219 "err=%d", ret); 1220 return ret; 1221 } 1222 dpaa2_q->fqid = qid.fqid; 1223 } 1224 1225 if (dpaa2_enable_err_queue) { 1226 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token, 1227 DPNI_QUEUE_RX_ERR, 0, 0, &cfg, &qid); 1228 if (ret) { 1229 DPAA2_PMD_ERR("Error getting rx err flow information: err=%d", 1230 ret); 1231 return ret; 1232 } 1233 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq; 1234 dpaa2_q->fqid = qid.fqid; 1235 dpaa2_q->eth_data = dev->data; 1236 1237 err_cfg.errors = DPNI_ERROR_DISC; 1238 err_cfg.error_action = DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE; 1239 } else { 1240 /* checksum errors, send them to normal path 1241 * and set it in annotation 1242 */ 1243 err_cfg.errors = DPNI_ERROR_L3CE | DPNI_ERROR_L4CE; 1244 1245 /* if packet with parse error are not to be dropped */ 1246 err_cfg.errors |= DPNI_ERROR_PHE; 1247 1248 err_cfg.error_action = DPNI_ERROR_ACTION_CONTINUE; 1249 } 1250 err_cfg.set_frame_annotation = true; 1251 1252 ret = dpni_set_errors_behavior(dpni, CMD_PRI_LOW, 1253 priv->token, &err_cfg); 1254 if (ret) { 1255 DPAA2_PMD_ERR("Error to dpni_set_errors_behavior: code = %d", 1256 ret); 1257 return ret; 1258 } 1259 1260 /* if the interrupts were configured on this devices*/ 1261 if (intr_handle && rte_intr_fd_get(intr_handle) && 1262 dev->data->dev_conf.intr_conf.lsc != 0) { 1263 /* Registering LSC interrupt handler */ 1264 rte_intr_callback_register(intr_handle, 1265 dpaa2_interrupt_handler, 1266 (void *)dev); 1267 1268 /* enable vfio intr/eventfd mapping 1269 * Interrupt index 0 is required, so we can not use 1270 * rte_intr_enable. 1271 */ 1272 rte_dpaa2_intr_enable(intr_handle, DPNI_IRQ_INDEX); 1273 1274 /* enable dpni_irqs */ 1275 dpaa2_eth_setup_irqs(dev, 1); 1276 } 1277 1278 /* Change the tx burst function if ordered queues are used */ 1279 if (priv->en_ordered) 1280 dev->tx_pkt_burst = dpaa2_dev_tx_ordered; 1281 1282 for (i = 0; i < dev->data->nb_rx_queues; i++) 1283 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED; 1284 for (i = 0; i < dev->data->nb_tx_queues; i++) 1285 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED; 1286 1287 return 0; 1288 } 1289 1290 /** 1291 * This routine disables all traffic on the adapter by issuing a 1292 * global reset on the MAC. 1293 */ 1294 static int 1295 dpaa2_dev_stop(struct rte_eth_dev *dev) 1296 { 1297 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1298 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1299 int ret; 1300 struct rte_eth_link link; 1301 struct rte_device *rdev = dev->device; 1302 struct rte_intr_handle *intr_handle; 1303 struct rte_dpaa2_device *dpaa2_dev; 1304 uint16_t i; 1305 1306 dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device); 1307 intr_handle = dpaa2_dev->intr_handle; 1308 1309 PMD_INIT_FUNC_TRACE(); 1310 1311 /* reset interrupt callback */ 1312 if (intr_handle && rte_intr_fd_get(intr_handle) && 1313 dev->data->dev_conf.intr_conf.lsc != 0) { 1314 /*disable dpni irqs */ 1315 dpaa2_eth_setup_irqs(dev, 0); 1316 1317 /* disable vfio intr before callback unregister */ 1318 rte_dpaa2_intr_disable(intr_handle, DPNI_IRQ_INDEX); 1319 1320 /* Unregistering LSC interrupt handler */ 1321 rte_intr_callback_unregister(intr_handle, 1322 dpaa2_interrupt_handler, 1323 (void *)dev); 1324 } 1325 1326 dpaa2_dev_set_link_down(dev); 1327 1328 ret = dpni_disable(dpni, CMD_PRI_LOW, priv->token); 1329 if (ret) { 1330 DPAA2_PMD_ERR("Failure (ret %d) in disabling dpni %d dev", 1331 ret, priv->hw_id); 1332 return ret; 1333 } 1334 1335 /* clear the recorded link status */ 1336 memset(&link, 0, sizeof(link)); 1337 rte_eth_linkstatus_set(dev, &link); 1338 1339 for (i = 0; i < dev->data->nb_rx_queues; i++) 1340 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED; 1341 for (i = 0; i < dev->data->nb_tx_queues; i++) 1342 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED; 1343 1344 return 0; 1345 } 1346 1347 static int 1348 dpaa2_dev_close(struct rte_eth_dev *dev) 1349 { 1350 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1351 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1352 int i, ret; 1353 struct rte_eth_link link; 1354 1355 PMD_INIT_FUNC_TRACE(); 1356 1357 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1358 return 0; 1359 1360 if (!dpni) { 1361 DPAA2_PMD_WARN("Already closed or not started"); 1362 return -1; 1363 } 1364 1365 dpaa2_tm_deinit(dev); 1366 dpaa2_flow_clean(dev); 1367 /* Clean the device first */ 1368 ret = dpni_reset(dpni, CMD_PRI_LOW, priv->token); 1369 if (ret) { 1370 DPAA2_PMD_ERR("Failure cleaning dpni device: err=%d", ret); 1371 return -1; 1372 } 1373 1374 memset(&link, 0, sizeof(link)); 1375 rte_eth_linkstatus_set(dev, &link); 1376 1377 /* Free private queues memory */ 1378 dpaa2_free_rx_tx_queues(dev); 1379 /* Close the device at underlying layer*/ 1380 ret = dpni_close(dpni, CMD_PRI_LOW, priv->token); 1381 if (ret) { 1382 DPAA2_PMD_ERR("Failure closing dpni device with err code %d", 1383 ret); 1384 } 1385 1386 /* Free the allocated memory for ethernet private data and dpni*/ 1387 priv->hw = NULL; 1388 dev->process_private = NULL; 1389 rte_free(dpni); 1390 1391 for (i = 0; i < MAX_TCS; i++) 1392 rte_free((void *)(size_t)priv->extract.tc_extract_param[i]); 1393 1394 if (priv->extract.qos_extract_param) 1395 rte_free((void *)(size_t)priv->extract.qos_extract_param); 1396 1397 DPAA2_PMD_INFO("%s: netdev deleted", dev->data->name); 1398 return 0; 1399 } 1400 1401 static int 1402 dpaa2_dev_promiscuous_enable( 1403 struct rte_eth_dev *dev) 1404 { 1405 int ret; 1406 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1407 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1408 1409 PMD_INIT_FUNC_TRACE(); 1410 1411 if (dpni == NULL) { 1412 DPAA2_PMD_ERR("dpni is NULL"); 1413 return -ENODEV; 1414 } 1415 1416 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, true); 1417 if (ret < 0) 1418 DPAA2_PMD_ERR("Unable to enable U promisc mode %d", ret); 1419 1420 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true); 1421 if (ret < 0) 1422 DPAA2_PMD_ERR("Unable to enable M promisc mode %d", ret); 1423 1424 return ret; 1425 } 1426 1427 static int 1428 dpaa2_dev_promiscuous_disable( 1429 struct rte_eth_dev *dev) 1430 { 1431 int ret; 1432 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1433 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1434 1435 PMD_INIT_FUNC_TRACE(); 1436 1437 if (dpni == NULL) { 1438 DPAA2_PMD_ERR("dpni is NULL"); 1439 return -ENODEV; 1440 } 1441 1442 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, false); 1443 if (ret < 0) 1444 DPAA2_PMD_ERR("Unable to disable U promisc mode %d", ret); 1445 1446 if (dev->data->all_multicast == 0) { 1447 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, 1448 priv->token, false); 1449 if (ret < 0) 1450 DPAA2_PMD_ERR("Unable to disable M promisc mode %d", 1451 ret); 1452 } 1453 1454 return ret; 1455 } 1456 1457 static int 1458 dpaa2_dev_allmulticast_enable( 1459 struct rte_eth_dev *dev) 1460 { 1461 int ret; 1462 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1463 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1464 1465 PMD_INIT_FUNC_TRACE(); 1466 1467 if (dpni == NULL) { 1468 DPAA2_PMD_ERR("dpni is NULL"); 1469 return -ENODEV; 1470 } 1471 1472 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true); 1473 if (ret < 0) 1474 DPAA2_PMD_ERR("Unable to enable multicast mode %d", ret); 1475 1476 return ret; 1477 } 1478 1479 static int 1480 dpaa2_dev_allmulticast_disable(struct rte_eth_dev *dev) 1481 { 1482 int ret; 1483 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1484 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1485 1486 PMD_INIT_FUNC_TRACE(); 1487 1488 if (dpni == NULL) { 1489 DPAA2_PMD_ERR("dpni is NULL"); 1490 return -ENODEV; 1491 } 1492 1493 /* must remain on for all promiscuous */ 1494 if (dev->data->promiscuous == 1) 1495 return 0; 1496 1497 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, false); 1498 if (ret < 0) 1499 DPAA2_PMD_ERR("Unable to disable multicast mode %d", ret); 1500 1501 return ret; 1502 } 1503 1504 static int 1505 dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 1506 { 1507 int ret; 1508 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1509 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1510 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN 1511 + VLAN_TAG_SIZE; 1512 1513 PMD_INIT_FUNC_TRACE(); 1514 1515 if (dpni == NULL) { 1516 DPAA2_PMD_ERR("dpni is NULL"); 1517 return -EINVAL; 1518 } 1519 1520 /* Set the Max Rx frame length as 'mtu' + 1521 * Maximum Ethernet header length 1522 */ 1523 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, priv->token, 1524 frame_size - RTE_ETHER_CRC_LEN); 1525 if (ret) { 1526 DPAA2_PMD_ERR("Setting the max frame length failed"); 1527 return -1; 1528 } 1529 DPAA2_PMD_INFO("MTU configured for the device: %d", mtu); 1530 return 0; 1531 } 1532 1533 static int 1534 dpaa2_dev_add_mac_addr(struct rte_eth_dev *dev, 1535 struct rte_ether_addr *addr, 1536 __rte_unused uint32_t index, 1537 __rte_unused uint32_t pool) 1538 { 1539 int ret; 1540 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1541 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1542 1543 PMD_INIT_FUNC_TRACE(); 1544 1545 if (dpni == NULL) { 1546 DPAA2_PMD_ERR("dpni is NULL"); 1547 return -1; 1548 } 1549 1550 ret = dpni_add_mac_addr(dpni, CMD_PRI_LOW, priv->token, 1551 addr->addr_bytes, 0, 0, 0); 1552 if (ret) 1553 DPAA2_PMD_ERR( 1554 "error: Adding the MAC ADDR failed: err = %d", ret); 1555 return 0; 1556 } 1557 1558 static void 1559 dpaa2_dev_remove_mac_addr(struct rte_eth_dev *dev, 1560 uint32_t index) 1561 { 1562 int ret; 1563 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1564 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1565 struct rte_eth_dev_data *data = dev->data; 1566 struct rte_ether_addr *macaddr; 1567 1568 PMD_INIT_FUNC_TRACE(); 1569 1570 macaddr = &data->mac_addrs[index]; 1571 1572 if (dpni == NULL) { 1573 DPAA2_PMD_ERR("dpni is NULL"); 1574 return; 1575 } 1576 1577 ret = dpni_remove_mac_addr(dpni, CMD_PRI_LOW, 1578 priv->token, macaddr->addr_bytes); 1579 if (ret) 1580 DPAA2_PMD_ERR( 1581 "error: Removing the MAC ADDR failed: err = %d", ret); 1582 } 1583 1584 static int 1585 dpaa2_dev_set_mac_addr(struct rte_eth_dev *dev, 1586 struct rte_ether_addr *addr) 1587 { 1588 int ret; 1589 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1590 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1591 1592 PMD_INIT_FUNC_TRACE(); 1593 1594 if (dpni == NULL) { 1595 DPAA2_PMD_ERR("dpni is NULL"); 1596 return -EINVAL; 1597 } 1598 1599 ret = dpni_set_primary_mac_addr(dpni, CMD_PRI_LOW, 1600 priv->token, addr->addr_bytes); 1601 1602 if (ret) 1603 DPAA2_PMD_ERR( 1604 "error: Setting the MAC ADDR failed %d", ret); 1605 1606 return ret; 1607 } 1608 1609 static 1610 int dpaa2_dev_stats_get(struct rte_eth_dev *dev, 1611 struct rte_eth_stats *stats) 1612 { 1613 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1614 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1615 int32_t retcode; 1616 uint8_t page0 = 0, page1 = 1, page2 = 2; 1617 union dpni_statistics value; 1618 int i; 1619 struct dpaa2_queue *dpaa2_rxq, *dpaa2_txq; 1620 1621 memset(&value, 0, sizeof(union dpni_statistics)); 1622 1623 PMD_INIT_FUNC_TRACE(); 1624 1625 if (!dpni) { 1626 DPAA2_PMD_ERR("dpni is NULL"); 1627 return -EINVAL; 1628 } 1629 1630 if (!stats) { 1631 DPAA2_PMD_ERR("stats is NULL"); 1632 return -EINVAL; 1633 } 1634 1635 /*Get Counters from page_0*/ 1636 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1637 page0, 0, &value); 1638 if (retcode) 1639 goto err; 1640 1641 stats->ipackets = value.page_0.ingress_all_frames; 1642 stats->ibytes = value.page_0.ingress_all_bytes; 1643 1644 /*Get Counters from page_1*/ 1645 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1646 page1, 0, &value); 1647 if (retcode) 1648 goto err; 1649 1650 stats->opackets = value.page_1.egress_all_frames; 1651 stats->obytes = value.page_1.egress_all_bytes; 1652 1653 /*Get Counters from page_2*/ 1654 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1655 page2, 0, &value); 1656 if (retcode) 1657 goto err; 1658 1659 /* Ingress drop frame count due to configured rules */ 1660 stats->ierrors = value.page_2.ingress_filtered_frames; 1661 /* Ingress drop frame count due to error */ 1662 stats->ierrors += value.page_2.ingress_discarded_frames; 1663 1664 stats->oerrors = value.page_2.egress_discarded_frames; 1665 stats->imissed = value.page_2.ingress_nobuffer_discards; 1666 1667 /* Fill in per queue stats */ 1668 for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) && 1669 (i < priv->nb_rx_queues || i < priv->nb_tx_queues); ++i) { 1670 dpaa2_rxq = (struct dpaa2_queue *)priv->rx_vq[i]; 1671 dpaa2_txq = (struct dpaa2_queue *)priv->tx_vq[i]; 1672 if (dpaa2_rxq) 1673 stats->q_ipackets[i] = dpaa2_rxq->rx_pkts; 1674 if (dpaa2_txq) 1675 stats->q_opackets[i] = dpaa2_txq->tx_pkts; 1676 1677 /* Byte counting is not implemented */ 1678 stats->q_ibytes[i] = 0; 1679 stats->q_obytes[i] = 0; 1680 } 1681 1682 return 0; 1683 1684 err: 1685 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode); 1686 return retcode; 1687 }; 1688 1689 static int 1690 dpaa2_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 1691 unsigned int n) 1692 { 1693 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1694 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1695 int32_t retcode; 1696 union dpni_statistics value[5] = {}; 1697 unsigned int i = 0, num = RTE_DIM(dpaa2_xstats_strings); 1698 1699 if (n < num) 1700 return num; 1701 1702 if (xstats == NULL) 1703 return 0; 1704 1705 /* Get Counters from page_0*/ 1706 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1707 0, 0, &value[0]); 1708 if (retcode) 1709 goto err; 1710 1711 /* Get Counters from page_1*/ 1712 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1713 1, 0, &value[1]); 1714 if (retcode) 1715 goto err; 1716 1717 /* Get Counters from page_2*/ 1718 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1719 2, 0, &value[2]); 1720 if (retcode) 1721 goto err; 1722 1723 for (i = 0; i < priv->max_cgs; i++) { 1724 if (!priv->cgid_in_use[i]) { 1725 /* Get Counters from page_4*/ 1726 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, 1727 priv->token, 1728 4, 0, &value[4]); 1729 if (retcode) 1730 goto err; 1731 break; 1732 } 1733 } 1734 1735 for (i = 0; i < num; i++) { 1736 xstats[i].id = i; 1737 xstats[i].value = value[dpaa2_xstats_strings[i].page_id]. 1738 raw.counter[dpaa2_xstats_strings[i].stats_id]; 1739 } 1740 return i; 1741 err: 1742 DPAA2_PMD_ERR("Error in obtaining extended stats (%d)", retcode); 1743 return retcode; 1744 } 1745 1746 static int 1747 dpaa2_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 1748 struct rte_eth_xstat_name *xstats_names, 1749 unsigned int limit) 1750 { 1751 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings); 1752 1753 if (limit < stat_cnt) 1754 return stat_cnt; 1755 1756 if (xstats_names != NULL) 1757 for (i = 0; i < stat_cnt; i++) 1758 strlcpy(xstats_names[i].name, 1759 dpaa2_xstats_strings[i].name, 1760 sizeof(xstats_names[i].name)); 1761 1762 return stat_cnt; 1763 } 1764 1765 static int 1766 dpaa2_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 1767 uint64_t *values, unsigned int n) 1768 { 1769 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings); 1770 uint64_t values_copy[stat_cnt]; 1771 1772 if (!ids) { 1773 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1774 struct fsl_mc_io *dpni = 1775 (struct fsl_mc_io *)dev->process_private; 1776 int32_t retcode; 1777 union dpni_statistics value[5] = {}; 1778 1779 if (n < stat_cnt) 1780 return stat_cnt; 1781 1782 if (!values) 1783 return 0; 1784 1785 /* Get Counters from page_0*/ 1786 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1787 0, 0, &value[0]); 1788 if (retcode) 1789 return 0; 1790 1791 /* Get Counters from page_1*/ 1792 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1793 1, 0, &value[1]); 1794 if (retcode) 1795 return 0; 1796 1797 /* Get Counters from page_2*/ 1798 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1799 2, 0, &value[2]); 1800 if (retcode) 1801 return 0; 1802 1803 /* Get Counters from page_4*/ 1804 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1805 4, 0, &value[4]); 1806 if (retcode) 1807 return 0; 1808 1809 for (i = 0; i < stat_cnt; i++) { 1810 values[i] = value[dpaa2_xstats_strings[i].page_id]. 1811 raw.counter[dpaa2_xstats_strings[i].stats_id]; 1812 } 1813 return stat_cnt; 1814 } 1815 1816 dpaa2_xstats_get_by_id(dev, NULL, values_copy, stat_cnt); 1817 1818 for (i = 0; i < n; i++) { 1819 if (ids[i] >= stat_cnt) { 1820 DPAA2_PMD_ERR("xstats id value isn't valid"); 1821 return -1; 1822 } 1823 values[i] = values_copy[ids[i]]; 1824 } 1825 return n; 1826 } 1827 1828 static int 1829 dpaa2_xstats_get_names_by_id( 1830 struct rte_eth_dev *dev, 1831 const uint64_t *ids, 1832 struct rte_eth_xstat_name *xstats_names, 1833 unsigned int limit) 1834 { 1835 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings); 1836 struct rte_eth_xstat_name xstats_names_copy[stat_cnt]; 1837 1838 if (!ids) 1839 return dpaa2_xstats_get_names(dev, xstats_names, limit); 1840 1841 dpaa2_xstats_get_names(dev, xstats_names_copy, limit); 1842 1843 for (i = 0; i < limit; i++) { 1844 if (ids[i] >= stat_cnt) { 1845 DPAA2_PMD_ERR("xstats id value isn't valid"); 1846 return -1; 1847 } 1848 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 1849 } 1850 return limit; 1851 } 1852 1853 static int 1854 dpaa2_dev_stats_reset(struct rte_eth_dev *dev) 1855 { 1856 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1857 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1858 int retcode; 1859 int i; 1860 struct dpaa2_queue *dpaa2_q; 1861 1862 PMD_INIT_FUNC_TRACE(); 1863 1864 if (dpni == NULL) { 1865 DPAA2_PMD_ERR("dpni is NULL"); 1866 return -EINVAL; 1867 } 1868 1869 retcode = dpni_reset_statistics(dpni, CMD_PRI_LOW, priv->token); 1870 if (retcode) 1871 goto error; 1872 1873 /* Reset the per queue stats in dpaa2_queue structure */ 1874 for (i = 0; i < priv->nb_rx_queues; i++) { 1875 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i]; 1876 if (dpaa2_q) 1877 dpaa2_q->rx_pkts = 0; 1878 } 1879 1880 for (i = 0; i < priv->nb_tx_queues; i++) { 1881 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; 1882 if (dpaa2_q) 1883 dpaa2_q->tx_pkts = 0; 1884 } 1885 1886 return 0; 1887 1888 error: 1889 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode); 1890 return retcode; 1891 }; 1892 1893 /* return 0 means link status changed, -1 means not changed */ 1894 static int 1895 dpaa2_dev_link_update(struct rte_eth_dev *dev, 1896 int wait_to_complete) 1897 { 1898 int ret; 1899 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1900 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1901 struct rte_eth_link link; 1902 struct dpni_link_state state = {0}; 1903 uint8_t count; 1904 1905 if (dpni == NULL) { 1906 DPAA2_PMD_ERR("dpni is NULL"); 1907 return 0; 1908 } 1909 1910 for (count = 0; count <= MAX_REPEAT_TIME; count++) { 1911 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, 1912 &state); 1913 if (ret < 0) { 1914 DPAA2_PMD_DEBUG("error: dpni_get_link_state %d", ret); 1915 return -1; 1916 } 1917 if (state.up == RTE_ETH_LINK_DOWN && 1918 wait_to_complete) 1919 rte_delay_ms(CHECK_INTERVAL); 1920 else 1921 break; 1922 } 1923 1924 memset(&link, 0, sizeof(struct rte_eth_link)); 1925 link.link_status = state.up; 1926 link.link_speed = state.rate; 1927 1928 if (state.options & DPNI_LINK_OPT_HALF_DUPLEX) 1929 link.link_duplex = RTE_ETH_LINK_HALF_DUPLEX; 1930 else 1931 link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX; 1932 1933 ret = rte_eth_linkstatus_set(dev, &link); 1934 if (ret == -1) 1935 DPAA2_PMD_DEBUG("No change in status"); 1936 else 1937 DPAA2_PMD_INFO("Port %d Link is %s\n", dev->data->port_id, 1938 link.link_status ? "Up" : "Down"); 1939 1940 return ret; 1941 } 1942 1943 /** 1944 * Toggle the DPNI to enable, if not already enabled. 1945 * This is not strictly PHY up/down - it is more of logical toggling. 1946 */ 1947 static int 1948 dpaa2_dev_set_link_up(struct rte_eth_dev *dev) 1949 { 1950 int ret = -EINVAL; 1951 struct dpaa2_dev_priv *priv; 1952 struct fsl_mc_io *dpni; 1953 int en = 0; 1954 struct dpni_link_state state = {0}; 1955 1956 priv = dev->data->dev_private; 1957 dpni = (struct fsl_mc_io *)dev->process_private; 1958 1959 if (dpni == NULL) { 1960 DPAA2_PMD_ERR("dpni is NULL"); 1961 return ret; 1962 } 1963 1964 /* Check if DPNI is currently enabled */ 1965 ret = dpni_is_enabled(dpni, CMD_PRI_LOW, priv->token, &en); 1966 if (ret) { 1967 /* Unable to obtain dpni status; Not continuing */ 1968 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret); 1969 return -EINVAL; 1970 } 1971 1972 /* Enable link if not already enabled */ 1973 if (!en) { 1974 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token); 1975 if (ret) { 1976 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret); 1977 return -EINVAL; 1978 } 1979 } 1980 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state); 1981 if (ret < 0) { 1982 DPAA2_PMD_DEBUG("Unable to get link state (%d)", ret); 1983 return -1; 1984 } 1985 1986 /* changing tx burst function to start enqueues */ 1987 dev->tx_pkt_burst = dpaa2_dev_tx; 1988 dev->data->dev_link.link_status = state.up; 1989 dev->data->dev_link.link_speed = state.rate; 1990 1991 if (state.up) 1992 DPAA2_PMD_INFO("Port %d Link is Up", dev->data->port_id); 1993 else 1994 DPAA2_PMD_INFO("Port %d Link is Down", dev->data->port_id); 1995 return ret; 1996 } 1997 1998 /** 1999 * Toggle the DPNI to disable, if not already disabled. 2000 * This is not strictly PHY up/down - it is more of logical toggling. 2001 */ 2002 static int 2003 dpaa2_dev_set_link_down(struct rte_eth_dev *dev) 2004 { 2005 int ret = -EINVAL; 2006 struct dpaa2_dev_priv *priv; 2007 struct fsl_mc_io *dpni; 2008 int dpni_enabled = 0; 2009 int retries = 10; 2010 2011 PMD_INIT_FUNC_TRACE(); 2012 2013 priv = dev->data->dev_private; 2014 dpni = (struct fsl_mc_io *)dev->process_private; 2015 2016 if (dpni == NULL) { 2017 DPAA2_PMD_ERR("Device has not yet been configured"); 2018 return ret; 2019 } 2020 2021 /*changing tx burst function to avoid any more enqueues */ 2022 dev->tx_pkt_burst = rte_eth_pkt_burst_dummy; 2023 2024 /* Loop while dpni_disable() attempts to drain the egress FQs 2025 * and confirm them back to us. 2026 */ 2027 do { 2028 ret = dpni_disable(dpni, 0, priv->token); 2029 if (ret) { 2030 DPAA2_PMD_ERR("dpni disable failed (%d)", ret); 2031 return ret; 2032 } 2033 ret = dpni_is_enabled(dpni, 0, priv->token, &dpni_enabled); 2034 if (ret) { 2035 DPAA2_PMD_ERR("dpni enable check failed (%d)", ret); 2036 return ret; 2037 } 2038 if (dpni_enabled) 2039 /* Allow the MC some slack */ 2040 rte_delay_us(100 * 1000); 2041 } while (dpni_enabled && --retries); 2042 2043 if (!retries) { 2044 DPAA2_PMD_WARN("Retry count exceeded disabling dpni"); 2045 /* todo- we may have to manually cleanup queues. 2046 */ 2047 } else { 2048 DPAA2_PMD_INFO("Port %d Link DOWN successful", 2049 dev->data->port_id); 2050 } 2051 2052 dev->data->dev_link.link_status = 0; 2053 2054 return ret; 2055 } 2056 2057 static int 2058 dpaa2_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 2059 { 2060 int ret = -EINVAL; 2061 struct dpaa2_dev_priv *priv; 2062 struct fsl_mc_io *dpni; 2063 struct dpni_link_state state = {0}; 2064 2065 PMD_INIT_FUNC_TRACE(); 2066 2067 priv = dev->data->dev_private; 2068 dpni = (struct fsl_mc_io *)dev->process_private; 2069 2070 if (dpni == NULL || fc_conf == NULL) { 2071 DPAA2_PMD_ERR("device not configured"); 2072 return ret; 2073 } 2074 2075 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state); 2076 if (ret) { 2077 DPAA2_PMD_ERR("error: dpni_get_link_state %d", ret); 2078 return ret; 2079 } 2080 2081 memset(fc_conf, 0, sizeof(struct rte_eth_fc_conf)); 2082 if (state.options & DPNI_LINK_OPT_PAUSE) { 2083 /* DPNI_LINK_OPT_PAUSE set 2084 * if ASYM_PAUSE not set, 2085 * RX Side flow control (handle received Pause frame) 2086 * TX side flow control (send Pause frame) 2087 * if ASYM_PAUSE set, 2088 * RX Side flow control (handle received Pause frame) 2089 * No TX side flow control (send Pause frame disabled) 2090 */ 2091 if (!(state.options & DPNI_LINK_OPT_ASYM_PAUSE)) 2092 fc_conf->mode = RTE_ETH_FC_FULL; 2093 else 2094 fc_conf->mode = RTE_ETH_FC_RX_PAUSE; 2095 } else { 2096 /* DPNI_LINK_OPT_PAUSE not set 2097 * if ASYM_PAUSE set, 2098 * TX side flow control (send Pause frame) 2099 * No RX side flow control (No action on pause frame rx) 2100 * if ASYM_PAUSE not set, 2101 * Flow control disabled 2102 */ 2103 if (state.options & DPNI_LINK_OPT_ASYM_PAUSE) 2104 fc_conf->mode = RTE_ETH_FC_TX_PAUSE; 2105 else 2106 fc_conf->mode = RTE_ETH_FC_NONE; 2107 } 2108 2109 return ret; 2110 } 2111 2112 static int 2113 dpaa2_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 2114 { 2115 int ret = -EINVAL; 2116 struct dpaa2_dev_priv *priv; 2117 struct fsl_mc_io *dpni; 2118 struct dpni_link_state state = {0}; 2119 struct dpni_link_cfg cfg = {0}; 2120 2121 PMD_INIT_FUNC_TRACE(); 2122 2123 priv = dev->data->dev_private; 2124 dpni = (struct fsl_mc_io *)dev->process_private; 2125 2126 if (dpni == NULL) { 2127 DPAA2_PMD_ERR("dpni is NULL"); 2128 return ret; 2129 } 2130 2131 /* It is necessary to obtain the current state before setting fc_conf 2132 * as MC would return error in case rate, autoneg or duplex values are 2133 * different. 2134 */ 2135 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state); 2136 if (ret) { 2137 DPAA2_PMD_ERR("Unable to get link state (err=%d)", ret); 2138 return -1; 2139 } 2140 2141 /* Disable link before setting configuration */ 2142 dpaa2_dev_set_link_down(dev); 2143 2144 /* Based on fc_conf, update cfg */ 2145 cfg.rate = state.rate; 2146 cfg.options = state.options; 2147 2148 /* update cfg with fc_conf */ 2149 switch (fc_conf->mode) { 2150 case RTE_ETH_FC_FULL: 2151 /* Full flow control; 2152 * OPT_PAUSE set, ASYM_PAUSE not set 2153 */ 2154 cfg.options |= DPNI_LINK_OPT_PAUSE; 2155 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE; 2156 break; 2157 case RTE_ETH_FC_TX_PAUSE: 2158 /* Enable RX flow control 2159 * OPT_PAUSE not set; 2160 * ASYM_PAUSE set; 2161 */ 2162 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE; 2163 cfg.options &= ~DPNI_LINK_OPT_PAUSE; 2164 break; 2165 case RTE_ETH_FC_RX_PAUSE: 2166 /* Enable TX Flow control 2167 * OPT_PAUSE set 2168 * ASYM_PAUSE set 2169 */ 2170 cfg.options |= DPNI_LINK_OPT_PAUSE; 2171 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE; 2172 break; 2173 case RTE_ETH_FC_NONE: 2174 /* Disable Flow control 2175 * OPT_PAUSE not set 2176 * ASYM_PAUSE not set 2177 */ 2178 cfg.options &= ~DPNI_LINK_OPT_PAUSE; 2179 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE; 2180 break; 2181 default: 2182 DPAA2_PMD_ERR("Incorrect Flow control flag (%d)", 2183 fc_conf->mode); 2184 return -1; 2185 } 2186 2187 ret = dpni_set_link_cfg(dpni, CMD_PRI_LOW, priv->token, &cfg); 2188 if (ret) 2189 DPAA2_PMD_ERR("Unable to set Link configuration (err=%d)", 2190 ret); 2191 2192 /* Enable link */ 2193 dpaa2_dev_set_link_up(dev); 2194 2195 return ret; 2196 } 2197 2198 static int 2199 dpaa2_dev_rss_hash_update(struct rte_eth_dev *dev, 2200 struct rte_eth_rss_conf *rss_conf) 2201 { 2202 struct rte_eth_dev_data *data = dev->data; 2203 struct dpaa2_dev_priv *priv = data->dev_private; 2204 struct rte_eth_conf *eth_conf = &data->dev_conf; 2205 int ret, tc_index; 2206 2207 PMD_INIT_FUNC_TRACE(); 2208 2209 if (rss_conf->rss_hf) { 2210 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) { 2211 ret = dpaa2_setup_flow_dist(dev, rss_conf->rss_hf, 2212 tc_index); 2213 if (ret) { 2214 DPAA2_PMD_ERR("Unable to set flow dist on tc%d", 2215 tc_index); 2216 return ret; 2217 } 2218 } 2219 } else { 2220 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) { 2221 ret = dpaa2_remove_flow_dist(dev, tc_index); 2222 if (ret) { 2223 DPAA2_PMD_ERR( 2224 "Unable to remove flow dist on tc%d", 2225 tc_index); 2226 return ret; 2227 } 2228 } 2229 } 2230 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf; 2231 return 0; 2232 } 2233 2234 static int 2235 dpaa2_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 2236 struct rte_eth_rss_conf *rss_conf) 2237 { 2238 struct rte_eth_dev_data *data = dev->data; 2239 struct rte_eth_conf *eth_conf = &data->dev_conf; 2240 2241 /* dpaa2 does not support rss_key, so length should be 0*/ 2242 rss_conf->rss_key_len = 0; 2243 rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf; 2244 return 0; 2245 } 2246 2247 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev, 2248 int eth_rx_queue_id, 2249 struct dpaa2_dpcon_dev *dpcon, 2250 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf) 2251 { 2252 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private; 2253 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 2254 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id]; 2255 uint8_t flow_id = dpaa2_ethq->flow_id; 2256 struct dpni_queue cfg; 2257 uint8_t options, priority; 2258 int ret; 2259 2260 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_PARALLEL) 2261 dpaa2_ethq->cb = dpaa2_dev_process_parallel_event; 2262 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) 2263 dpaa2_ethq->cb = dpaa2_dev_process_atomic_event; 2264 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED) 2265 dpaa2_ethq->cb = dpaa2_dev_process_ordered_event; 2266 else 2267 return -EINVAL; 2268 2269 priority = (RTE_EVENT_DEV_PRIORITY_LOWEST / queue_conf->ev.priority) * 2270 (dpcon->num_priorities - 1); 2271 2272 memset(&cfg, 0, sizeof(struct dpni_queue)); 2273 options = DPNI_QUEUE_OPT_DEST; 2274 cfg.destination.type = DPNI_DEST_DPCON; 2275 cfg.destination.id = dpcon->dpcon_id; 2276 cfg.destination.priority = priority; 2277 2278 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) { 2279 options |= DPNI_QUEUE_OPT_HOLD_ACTIVE; 2280 cfg.destination.hold_active = 1; 2281 } 2282 2283 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED && 2284 !eth_priv->en_ordered) { 2285 struct opr_cfg ocfg; 2286 2287 /* Restoration window size = 256 frames */ 2288 ocfg.oprrws = 3; 2289 /* Restoration window size = 512 frames for LX2 */ 2290 if (dpaa2_svr_family == SVR_LX2160A) 2291 ocfg.oprrws = 4; 2292 /* Auto advance NESN window enabled */ 2293 ocfg.oa = 1; 2294 /* Late arrival window size disabled */ 2295 ocfg.olws = 0; 2296 /* ORL resource exhaustion advance NESN disabled */ 2297 ocfg.oeane = 0; 2298 /* Loose ordering enabled */ 2299 ocfg.oloe = 1; 2300 eth_priv->en_loose_ordered = 1; 2301 /* Strict ordering enabled if explicitly set */ 2302 if (getenv("DPAA2_STRICT_ORDERING_ENABLE")) { 2303 ocfg.oloe = 0; 2304 eth_priv->en_loose_ordered = 0; 2305 } 2306 2307 ret = dpni_set_opr(dpni, CMD_PRI_LOW, eth_priv->token, 2308 dpaa2_ethq->tc_index, flow_id, 2309 OPR_OPT_CREATE, &ocfg, 0); 2310 if (ret) { 2311 DPAA2_PMD_ERR("Error setting opr: ret: %d\n", ret); 2312 return ret; 2313 } 2314 2315 eth_priv->en_ordered = 1; 2316 } 2317 2318 options |= DPNI_QUEUE_OPT_USER_CTX; 2319 cfg.user_context = (size_t)(dpaa2_ethq); 2320 2321 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX, 2322 dpaa2_ethq->tc_index, flow_id, options, &cfg); 2323 if (ret) { 2324 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret); 2325 return ret; 2326 } 2327 2328 memcpy(&dpaa2_ethq->ev, &queue_conf->ev, sizeof(struct rte_event)); 2329 2330 return 0; 2331 } 2332 2333 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev, 2334 int eth_rx_queue_id) 2335 { 2336 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private; 2337 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 2338 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id]; 2339 uint8_t flow_id = dpaa2_ethq->flow_id; 2340 struct dpni_queue cfg; 2341 uint8_t options; 2342 int ret; 2343 2344 memset(&cfg, 0, sizeof(struct dpni_queue)); 2345 options = DPNI_QUEUE_OPT_DEST; 2346 cfg.destination.type = DPNI_DEST_NONE; 2347 2348 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX, 2349 dpaa2_ethq->tc_index, flow_id, options, &cfg); 2350 if (ret) 2351 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret); 2352 2353 return ret; 2354 } 2355 2356 static int 2357 dpaa2_dev_flow_ops_get(struct rte_eth_dev *dev, 2358 const struct rte_flow_ops **ops) 2359 { 2360 if (!dev) 2361 return -ENODEV; 2362 2363 *ops = &dpaa2_flow_ops; 2364 return 0; 2365 } 2366 2367 static void 2368 dpaa2_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 2369 struct rte_eth_rxq_info *qinfo) 2370 { 2371 struct dpaa2_queue *rxq; 2372 struct dpaa2_dev_priv *priv = dev->data->dev_private; 2373 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 2374 uint16_t max_frame_length; 2375 2376 rxq = (struct dpaa2_queue *)dev->data->rx_queues[queue_id]; 2377 2378 qinfo->mp = rxq->mb_pool; 2379 qinfo->scattered_rx = dev->data->scattered_rx; 2380 qinfo->nb_desc = rxq->nb_desc; 2381 if (dpni_get_max_frame_length(dpni, CMD_PRI_LOW, priv->token, 2382 &max_frame_length) == 0) 2383 qinfo->rx_buf_size = max_frame_length; 2384 2385 qinfo->conf.rx_free_thresh = 1; 2386 qinfo->conf.rx_drop_en = 1; 2387 qinfo->conf.rx_deferred_start = 0; 2388 qinfo->conf.offloads = rxq->offloads; 2389 } 2390 2391 static void 2392 dpaa2_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 2393 struct rte_eth_txq_info *qinfo) 2394 { 2395 struct dpaa2_queue *txq; 2396 2397 txq = dev->data->tx_queues[queue_id]; 2398 2399 qinfo->nb_desc = txq->nb_desc; 2400 qinfo->conf.tx_thresh.pthresh = 0; 2401 qinfo->conf.tx_thresh.hthresh = 0; 2402 qinfo->conf.tx_thresh.wthresh = 0; 2403 2404 qinfo->conf.tx_free_thresh = 0; 2405 qinfo->conf.tx_rs_thresh = 0; 2406 qinfo->conf.offloads = txq->offloads; 2407 qinfo->conf.tx_deferred_start = 0; 2408 } 2409 2410 static int 2411 dpaa2_tm_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops) 2412 { 2413 *(const void **)ops = &dpaa2_tm_ops; 2414 2415 return 0; 2416 } 2417 2418 void 2419 rte_pmd_dpaa2_thread_init(void) 2420 { 2421 int ret; 2422 2423 if (unlikely(!DPAA2_PER_LCORE_DPIO)) { 2424 ret = dpaa2_affine_qbman_swp(); 2425 if (ret) { 2426 DPAA2_PMD_ERR( 2427 "Failed to allocate IO portal, tid: %d\n", 2428 rte_gettid()); 2429 return; 2430 } 2431 } 2432 } 2433 2434 static struct eth_dev_ops dpaa2_ethdev_ops = { 2435 .dev_configure = dpaa2_eth_dev_configure, 2436 .dev_start = dpaa2_dev_start, 2437 .dev_stop = dpaa2_dev_stop, 2438 .dev_close = dpaa2_dev_close, 2439 .promiscuous_enable = dpaa2_dev_promiscuous_enable, 2440 .promiscuous_disable = dpaa2_dev_promiscuous_disable, 2441 .allmulticast_enable = dpaa2_dev_allmulticast_enable, 2442 .allmulticast_disable = dpaa2_dev_allmulticast_disable, 2443 .dev_set_link_up = dpaa2_dev_set_link_up, 2444 .dev_set_link_down = dpaa2_dev_set_link_down, 2445 .link_update = dpaa2_dev_link_update, 2446 .stats_get = dpaa2_dev_stats_get, 2447 .xstats_get = dpaa2_dev_xstats_get, 2448 .xstats_get_by_id = dpaa2_xstats_get_by_id, 2449 .xstats_get_names_by_id = dpaa2_xstats_get_names_by_id, 2450 .xstats_get_names = dpaa2_xstats_get_names, 2451 .stats_reset = dpaa2_dev_stats_reset, 2452 .xstats_reset = dpaa2_dev_stats_reset, 2453 .fw_version_get = dpaa2_fw_version_get, 2454 .dev_infos_get = dpaa2_dev_info_get, 2455 .dev_supported_ptypes_get = dpaa2_supported_ptypes_get, 2456 .mtu_set = dpaa2_dev_mtu_set, 2457 .vlan_filter_set = dpaa2_vlan_filter_set, 2458 .vlan_offload_set = dpaa2_vlan_offload_set, 2459 .vlan_tpid_set = dpaa2_vlan_tpid_set, 2460 .rx_queue_setup = dpaa2_dev_rx_queue_setup, 2461 .rx_queue_release = dpaa2_dev_rx_queue_release, 2462 .tx_queue_setup = dpaa2_dev_tx_queue_setup, 2463 .rx_burst_mode_get = dpaa2_dev_rx_burst_mode_get, 2464 .tx_burst_mode_get = dpaa2_dev_tx_burst_mode_get, 2465 .flow_ctrl_get = dpaa2_flow_ctrl_get, 2466 .flow_ctrl_set = dpaa2_flow_ctrl_set, 2467 .mac_addr_add = dpaa2_dev_add_mac_addr, 2468 .mac_addr_remove = dpaa2_dev_remove_mac_addr, 2469 .mac_addr_set = dpaa2_dev_set_mac_addr, 2470 .rss_hash_update = dpaa2_dev_rss_hash_update, 2471 .rss_hash_conf_get = dpaa2_dev_rss_hash_conf_get, 2472 .flow_ops_get = dpaa2_dev_flow_ops_get, 2473 .rxq_info_get = dpaa2_rxq_info_get, 2474 .txq_info_get = dpaa2_txq_info_get, 2475 .tm_ops_get = dpaa2_tm_ops_get, 2476 #if defined(RTE_LIBRTE_IEEE1588) 2477 .timesync_enable = dpaa2_timesync_enable, 2478 .timesync_disable = dpaa2_timesync_disable, 2479 .timesync_read_time = dpaa2_timesync_read_time, 2480 .timesync_write_time = dpaa2_timesync_write_time, 2481 .timesync_adjust_time = dpaa2_timesync_adjust_time, 2482 .timesync_read_rx_timestamp = dpaa2_timesync_read_rx_timestamp, 2483 .timesync_read_tx_timestamp = dpaa2_timesync_read_tx_timestamp, 2484 #endif 2485 }; 2486 2487 /* Populate the mac address from physically available (u-boot/firmware) and/or 2488 * one set by higher layers like MC (restool) etc. 2489 * Returns the table of MAC entries (multiple entries) 2490 */ 2491 static int 2492 populate_mac_addr(struct fsl_mc_io *dpni_dev, struct dpaa2_dev_priv *priv, 2493 struct rte_ether_addr *mac_entry) 2494 { 2495 int ret; 2496 struct rte_ether_addr phy_mac, prime_mac; 2497 2498 memset(&phy_mac, 0, sizeof(struct rte_ether_addr)); 2499 memset(&prime_mac, 0, sizeof(struct rte_ether_addr)); 2500 2501 /* Get the physical device MAC address */ 2502 ret = dpni_get_port_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token, 2503 phy_mac.addr_bytes); 2504 if (ret) { 2505 DPAA2_PMD_ERR("DPNI get physical port MAC failed: %d", ret); 2506 goto cleanup; 2507 } 2508 2509 ret = dpni_get_primary_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token, 2510 prime_mac.addr_bytes); 2511 if (ret) { 2512 DPAA2_PMD_ERR("DPNI get Prime port MAC failed: %d", ret); 2513 goto cleanup; 2514 } 2515 2516 /* Now that both MAC have been obtained, do: 2517 * if not_empty_mac(phy) && phy != Prime, overwrite prime with Phy 2518 * and return phy 2519 * If empty_mac(phy), return prime. 2520 * if both are empty, create random MAC, set as prime and return 2521 */ 2522 if (!rte_is_zero_ether_addr(&phy_mac)) { 2523 /* If the addresses are not same, overwrite prime */ 2524 if (!rte_is_same_ether_addr(&phy_mac, &prime_mac)) { 2525 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW, 2526 priv->token, 2527 phy_mac.addr_bytes); 2528 if (ret) { 2529 DPAA2_PMD_ERR("Unable to set MAC Address: %d", 2530 ret); 2531 goto cleanup; 2532 } 2533 memcpy(&prime_mac, &phy_mac, 2534 sizeof(struct rte_ether_addr)); 2535 } 2536 } else if (rte_is_zero_ether_addr(&prime_mac)) { 2537 /* In case phys and prime, both are zero, create random MAC */ 2538 rte_eth_random_addr(prime_mac.addr_bytes); 2539 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW, 2540 priv->token, 2541 prime_mac.addr_bytes); 2542 if (ret) { 2543 DPAA2_PMD_ERR("Unable to set MAC Address: %d", ret); 2544 goto cleanup; 2545 } 2546 } 2547 2548 /* prime_mac the final MAC address */ 2549 memcpy(mac_entry, &prime_mac, sizeof(struct rte_ether_addr)); 2550 return 0; 2551 2552 cleanup: 2553 return -1; 2554 } 2555 2556 static int 2557 check_devargs_handler(__rte_unused const char *key, const char *value, 2558 __rte_unused void *opaque) 2559 { 2560 if (strcmp(value, "1")) 2561 return -1; 2562 2563 return 0; 2564 } 2565 2566 static int 2567 dpaa2_get_devargs(struct rte_devargs *devargs, const char *key) 2568 { 2569 struct rte_kvargs *kvlist; 2570 2571 if (!devargs) 2572 return 0; 2573 2574 kvlist = rte_kvargs_parse(devargs->args, NULL); 2575 if (!kvlist) 2576 return 0; 2577 2578 if (!rte_kvargs_count(kvlist, key)) { 2579 rte_kvargs_free(kvlist); 2580 return 0; 2581 } 2582 2583 if (rte_kvargs_process(kvlist, key, 2584 check_devargs_handler, NULL) < 0) { 2585 rte_kvargs_free(kvlist); 2586 return 0; 2587 } 2588 rte_kvargs_free(kvlist); 2589 2590 return 1; 2591 } 2592 2593 static int 2594 dpaa2_dev_init(struct rte_eth_dev *eth_dev) 2595 { 2596 struct rte_device *dev = eth_dev->device; 2597 struct rte_dpaa2_device *dpaa2_dev; 2598 struct fsl_mc_io *dpni_dev; 2599 struct dpni_attr attr; 2600 struct dpaa2_dev_priv *priv = eth_dev->data->dev_private; 2601 struct dpni_buffer_layout layout; 2602 int ret, hw_id, i; 2603 2604 PMD_INIT_FUNC_TRACE(); 2605 2606 dpni_dev = rte_malloc(NULL, sizeof(struct fsl_mc_io), 0); 2607 if (!dpni_dev) { 2608 DPAA2_PMD_ERR("Memory allocation failed for dpni device"); 2609 return -1; 2610 } 2611 dpni_dev->regs = dpaa2_get_mcp_ptr(MC_PORTAL_INDEX); 2612 eth_dev->process_private = (void *)dpni_dev; 2613 2614 /* For secondary processes, the primary has done all the work */ 2615 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2616 /* In case of secondary, only burst and ops API need to be 2617 * plugged. 2618 */ 2619 eth_dev->dev_ops = &dpaa2_ethdev_ops; 2620 eth_dev->rx_queue_count = dpaa2_dev_rx_queue_count; 2621 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) 2622 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx; 2623 else if (dpaa2_get_devargs(dev->devargs, 2624 DRIVER_NO_PREFETCH_MODE)) 2625 eth_dev->rx_pkt_burst = dpaa2_dev_rx; 2626 else 2627 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx; 2628 eth_dev->tx_pkt_burst = dpaa2_dev_tx; 2629 return 0; 2630 } 2631 2632 dpaa2_dev = container_of(dev, struct rte_dpaa2_device, device); 2633 2634 hw_id = dpaa2_dev->object_id; 2635 ret = dpni_open(dpni_dev, CMD_PRI_LOW, hw_id, &priv->token); 2636 if (ret) { 2637 DPAA2_PMD_ERR( 2638 "Failure in opening dpni@%d with err code %d", 2639 hw_id, ret); 2640 rte_free(dpni_dev); 2641 return -1; 2642 } 2643 2644 if (eth_dev->data->dev_conf.lpbk_mode) 2645 dpaa2_dev_recycle_deconfig(eth_dev); 2646 2647 /* Clean the device first */ 2648 ret = dpni_reset(dpni_dev, CMD_PRI_LOW, priv->token); 2649 if (ret) { 2650 DPAA2_PMD_ERR("Failure cleaning dpni@%d with err code %d", 2651 hw_id, ret); 2652 goto init_err; 2653 } 2654 2655 ret = dpni_get_attributes(dpni_dev, CMD_PRI_LOW, priv->token, &attr); 2656 if (ret) { 2657 DPAA2_PMD_ERR( 2658 "Failure in get dpni@%d attribute, err code %d", 2659 hw_id, ret); 2660 goto init_err; 2661 } 2662 2663 priv->num_rx_tc = attr.num_rx_tcs; 2664 priv->num_tx_tc = attr.num_tx_tcs; 2665 priv->qos_entries = attr.qos_entries; 2666 priv->fs_entries = attr.fs_entries; 2667 priv->dist_queues = attr.num_queues; 2668 priv->num_channels = attr.num_channels; 2669 priv->channel_inuse = 0; 2670 rte_spinlock_init(&priv->lpbk_qp_lock); 2671 2672 /* only if the custom CG is enabled */ 2673 if (attr.options & DPNI_OPT_CUSTOM_CG) 2674 priv->max_cgs = attr.num_cgs; 2675 else 2676 priv->max_cgs = 0; 2677 2678 for (i = 0; i < priv->max_cgs; i++) 2679 priv->cgid_in_use[i] = 0; 2680 2681 for (i = 0; i < attr.num_rx_tcs; i++) 2682 priv->nb_rx_queues += attr.num_queues; 2683 2684 priv->nb_tx_queues = attr.num_tx_tcs * attr.num_channels; 2685 2686 DPAA2_PMD_DEBUG("RX-TC= %d, rx_queues= %d, tx_queues=%d, max_cgs=%d", 2687 priv->num_rx_tc, priv->nb_rx_queues, 2688 priv->nb_tx_queues, priv->max_cgs); 2689 2690 priv->hw = dpni_dev; 2691 priv->hw_id = hw_id; 2692 priv->options = attr.options; 2693 priv->max_mac_filters = attr.mac_filter_entries; 2694 priv->max_vlan_filters = attr.vlan_filter_entries; 2695 priv->flags = 0; 2696 #if defined(RTE_LIBRTE_IEEE1588) 2697 DPAA2_PMD_INFO("DPDK IEEE1588 is enabled"); 2698 priv->flags |= DPAA2_TX_CONF_ENABLE; 2699 #endif 2700 /* Used with ``fslmc:dpni.1,drv_tx_conf=1`` */ 2701 if (dpaa2_get_devargs(dev->devargs, DRIVER_TX_CONF)) { 2702 priv->flags |= DPAA2_TX_CONF_ENABLE; 2703 DPAA2_PMD_INFO("TX_CONF Enabled"); 2704 } 2705 2706 if (dpaa2_get_devargs(dev->devargs, DRIVER_ERROR_QUEUE)) { 2707 dpaa2_enable_err_queue = 1; 2708 DPAA2_PMD_INFO("Enable error queue"); 2709 } 2710 2711 /* Allocate memory for hardware structure for queues */ 2712 ret = dpaa2_alloc_rx_tx_queues(eth_dev); 2713 if (ret) { 2714 DPAA2_PMD_ERR("Queue allocation Failed"); 2715 goto init_err; 2716 } 2717 2718 /* Allocate memory for storing MAC addresses. 2719 * Table of mac_filter_entries size is allocated so that RTE ether lib 2720 * can add MAC entries when rte_eth_dev_mac_addr_add is called. 2721 */ 2722 eth_dev->data->mac_addrs = rte_zmalloc("dpni", 2723 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries, 0); 2724 if (eth_dev->data->mac_addrs == NULL) { 2725 DPAA2_PMD_ERR( 2726 "Failed to allocate %d bytes needed to store MAC addresses", 2727 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries); 2728 ret = -ENOMEM; 2729 goto init_err; 2730 } 2731 2732 ret = populate_mac_addr(dpni_dev, priv, ð_dev->data->mac_addrs[0]); 2733 if (ret) { 2734 DPAA2_PMD_ERR("Unable to fetch MAC Address for device"); 2735 rte_free(eth_dev->data->mac_addrs); 2736 eth_dev->data->mac_addrs = NULL; 2737 goto init_err; 2738 } 2739 2740 /* ... tx buffer layout ... */ 2741 memset(&layout, 0, sizeof(struct dpni_buffer_layout)); 2742 if (priv->flags & DPAA2_TX_CONF_ENABLE) { 2743 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS | 2744 DPNI_BUF_LAYOUT_OPT_TIMESTAMP; 2745 layout.pass_timestamp = true; 2746 } else { 2747 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS; 2748 } 2749 layout.pass_frame_status = 1; 2750 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token, 2751 DPNI_QUEUE_TX, &layout); 2752 if (ret) { 2753 DPAA2_PMD_ERR("Error (%d) in setting tx buffer layout", ret); 2754 goto init_err; 2755 } 2756 2757 /* ... tx-conf and error buffer layout ... */ 2758 memset(&layout, 0, sizeof(struct dpni_buffer_layout)); 2759 if (priv->flags & DPAA2_TX_CONF_ENABLE) { 2760 layout.options = DPNI_BUF_LAYOUT_OPT_TIMESTAMP; 2761 layout.pass_timestamp = true; 2762 } 2763 layout.options |= DPNI_BUF_LAYOUT_OPT_FRAME_STATUS; 2764 layout.pass_frame_status = 1; 2765 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token, 2766 DPNI_QUEUE_TX_CONFIRM, &layout); 2767 if (ret) { 2768 DPAA2_PMD_ERR("Error (%d) in setting tx-conf buffer layout", 2769 ret); 2770 goto init_err; 2771 } 2772 2773 eth_dev->dev_ops = &dpaa2_ethdev_ops; 2774 2775 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) { 2776 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx; 2777 DPAA2_PMD_INFO("Loopback mode"); 2778 } else if (dpaa2_get_devargs(dev->devargs, DRIVER_NO_PREFETCH_MODE)) { 2779 eth_dev->rx_pkt_burst = dpaa2_dev_rx; 2780 DPAA2_PMD_INFO("No Prefetch mode"); 2781 } else { 2782 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx; 2783 } 2784 eth_dev->tx_pkt_burst = dpaa2_dev_tx; 2785 2786 /* Init fields w.r.t. classification */ 2787 memset(&priv->extract.qos_key_extract, 0, 2788 sizeof(struct dpaa2_key_extract)); 2789 priv->extract.qos_extract_param = (size_t)rte_malloc(NULL, 256, 64); 2790 if (!priv->extract.qos_extract_param) { 2791 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow " 2792 " classification ", ret); 2793 goto init_err; 2794 } 2795 priv->extract.qos_key_extract.key_info.ipv4_src_offset = 2796 IP_ADDRESS_OFFSET_INVALID; 2797 priv->extract.qos_key_extract.key_info.ipv4_dst_offset = 2798 IP_ADDRESS_OFFSET_INVALID; 2799 priv->extract.qos_key_extract.key_info.ipv6_src_offset = 2800 IP_ADDRESS_OFFSET_INVALID; 2801 priv->extract.qos_key_extract.key_info.ipv6_dst_offset = 2802 IP_ADDRESS_OFFSET_INVALID; 2803 2804 for (i = 0; i < MAX_TCS; i++) { 2805 memset(&priv->extract.tc_key_extract[i], 0, 2806 sizeof(struct dpaa2_key_extract)); 2807 priv->extract.tc_extract_param[i] = 2808 (size_t)rte_malloc(NULL, 256, 64); 2809 if (!priv->extract.tc_extract_param[i]) { 2810 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow classification", 2811 ret); 2812 goto init_err; 2813 } 2814 priv->extract.tc_key_extract[i].key_info.ipv4_src_offset = 2815 IP_ADDRESS_OFFSET_INVALID; 2816 priv->extract.tc_key_extract[i].key_info.ipv4_dst_offset = 2817 IP_ADDRESS_OFFSET_INVALID; 2818 priv->extract.tc_key_extract[i].key_info.ipv6_src_offset = 2819 IP_ADDRESS_OFFSET_INVALID; 2820 priv->extract.tc_key_extract[i].key_info.ipv6_dst_offset = 2821 IP_ADDRESS_OFFSET_INVALID; 2822 } 2823 2824 ret = dpni_set_max_frame_length(dpni_dev, CMD_PRI_LOW, priv->token, 2825 RTE_ETHER_MAX_LEN - RTE_ETHER_CRC_LEN 2826 + VLAN_TAG_SIZE); 2827 if (ret) { 2828 DPAA2_PMD_ERR("Unable to set mtu. check config"); 2829 goto init_err; 2830 } 2831 2832 /*TODO To enable soft parser support DPAA2 driver needs to integrate 2833 * with external entity to receive byte code for software sequence 2834 * and same will be offload to the H/W using MC interface. 2835 * Currently it is assumed that DPAA2 driver has byte code by some 2836 * mean and same if offloaded to H/W. 2837 */ 2838 if (getenv("DPAA2_ENABLE_SOFT_PARSER")) { 2839 WRIOP_SS_INITIALIZER(priv); 2840 ret = dpaa2_eth_load_wriop_soft_parser(priv, DPNI_SS_INGRESS); 2841 if (ret < 0) { 2842 DPAA2_PMD_ERR(" Error(%d) in loading softparser\n", 2843 ret); 2844 return ret; 2845 } 2846 2847 ret = dpaa2_eth_enable_wriop_soft_parser(priv, 2848 DPNI_SS_INGRESS); 2849 if (ret < 0) { 2850 DPAA2_PMD_ERR(" Error(%d) in enabling softparser\n", 2851 ret); 2852 return ret; 2853 } 2854 } 2855 DPAA2_PMD_INFO("%s: netdev created, connected to %s", 2856 eth_dev->data->name, dpaa2_dev->ep_name); 2857 2858 return 0; 2859 init_err: 2860 dpaa2_dev_close(eth_dev); 2861 2862 return ret; 2863 } 2864 2865 int dpaa2_dev_is_dpaa2(struct rte_eth_dev *dev) 2866 { 2867 return dev->device->driver == &rte_dpaa2_pmd.driver; 2868 } 2869 2870 static int 2871 rte_dpaa2_probe(struct rte_dpaa2_driver *dpaa2_drv, 2872 struct rte_dpaa2_device *dpaa2_dev) 2873 { 2874 struct rte_eth_dev *eth_dev; 2875 struct dpaa2_dev_priv *dev_priv; 2876 int diag; 2877 2878 if ((DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) > 2879 RTE_PKTMBUF_HEADROOM) { 2880 DPAA2_PMD_ERR( 2881 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA2 Annotation req(%d)", 2882 RTE_PKTMBUF_HEADROOM, 2883 DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE); 2884 2885 return -1; 2886 } 2887 2888 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 2889 eth_dev = rte_eth_dev_allocate(dpaa2_dev->device.name); 2890 if (!eth_dev) 2891 return -ENODEV; 2892 dev_priv = rte_zmalloc("ethdev private structure", 2893 sizeof(struct dpaa2_dev_priv), 2894 RTE_CACHE_LINE_SIZE); 2895 if (dev_priv == NULL) { 2896 DPAA2_PMD_CRIT( 2897 "Unable to allocate memory for private data"); 2898 rte_eth_dev_release_port(eth_dev); 2899 return -ENOMEM; 2900 } 2901 eth_dev->data->dev_private = (void *)dev_priv; 2902 /* Store a pointer to eth_dev in dev_private */ 2903 dev_priv->eth_dev = eth_dev; 2904 } else { 2905 eth_dev = rte_eth_dev_attach_secondary(dpaa2_dev->device.name); 2906 if (!eth_dev) { 2907 DPAA2_PMD_DEBUG("returning enodev"); 2908 return -ENODEV; 2909 } 2910 } 2911 2912 eth_dev->device = &dpaa2_dev->device; 2913 2914 dpaa2_dev->eth_dev = eth_dev; 2915 eth_dev->data->rx_mbuf_alloc_failed = 0; 2916 2917 if (dpaa2_drv->drv_flags & RTE_DPAA2_DRV_INTR_LSC) 2918 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC; 2919 2920 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 2921 2922 /* Invoke PMD device initialization function */ 2923 diag = dpaa2_dev_init(eth_dev); 2924 if (diag == 0) { 2925 if (!dpaa2_tx_sg_pool) { 2926 dpaa2_tx_sg_pool = 2927 rte_pktmbuf_pool_create("dpaa2_mbuf_tx_sg_pool", 2928 DPAA2_POOL_SIZE, 2929 DPAA2_POOL_CACHE_SIZE, 0, 2930 DPAA2_MAX_SGS * sizeof(struct qbman_sge), 2931 rte_socket_id()); 2932 if (dpaa2_tx_sg_pool == NULL) { 2933 DPAA2_PMD_ERR("SG pool creation failed\n"); 2934 return -ENOMEM; 2935 } 2936 } 2937 rte_eth_dev_probing_finish(eth_dev); 2938 dpaa2_valid_dev++; 2939 return 0; 2940 } 2941 2942 rte_eth_dev_release_port(eth_dev); 2943 return diag; 2944 } 2945 2946 static int 2947 rte_dpaa2_remove(struct rte_dpaa2_device *dpaa2_dev) 2948 { 2949 struct rte_eth_dev *eth_dev; 2950 int ret; 2951 2952 eth_dev = dpaa2_dev->eth_dev; 2953 dpaa2_dev_close(eth_dev); 2954 dpaa2_valid_dev--; 2955 if (!dpaa2_valid_dev) 2956 rte_mempool_free(dpaa2_tx_sg_pool); 2957 ret = rte_eth_dev_release_port(eth_dev); 2958 2959 return ret; 2960 } 2961 2962 static struct rte_dpaa2_driver rte_dpaa2_pmd = { 2963 .drv_flags = RTE_DPAA2_DRV_INTR_LSC | RTE_DPAA2_DRV_IOVA_AS_VA, 2964 .drv_type = DPAA2_ETH, 2965 .probe = rte_dpaa2_probe, 2966 .remove = rte_dpaa2_remove, 2967 }; 2968 2969 RTE_PMD_REGISTER_DPAA2(NET_DPAA2_PMD_DRIVER_NAME, rte_dpaa2_pmd); 2970 RTE_PMD_REGISTER_PARAM_STRING(NET_DPAA2_PMD_DRIVER_NAME, 2971 DRIVER_LOOPBACK_MODE "=<int> " 2972 DRIVER_NO_PREFETCH_MODE "=<int>" 2973 DRIVER_TX_CONF "=<int>" 2974 DRIVER_ERROR_QUEUE "=<int>"); 2975 RTE_LOG_REGISTER_DEFAULT(dpaa2_logtype_pmd, NOTICE); 2976