1 /* * SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved. 4 * Copyright 2016 NXP 5 * 6 */ 7 8 #include <time.h> 9 #include <net/if.h> 10 11 #include <rte_mbuf.h> 12 #include <rte_ethdev_driver.h> 13 #include <rte_malloc.h> 14 #include <rte_memcpy.h> 15 #include <rte_string_fns.h> 16 #include <rte_cycles.h> 17 #include <rte_kvargs.h> 18 #include <rte_dev.h> 19 #include <rte_fslmc.h> 20 #include <rte_flow_driver.h> 21 22 #include "dpaa2_pmd_logs.h" 23 #include <fslmc_vfio.h> 24 #include <dpaa2_hw_pvt.h> 25 #include <dpaa2_hw_mempool.h> 26 #include <dpaa2_hw_dpio.h> 27 #include <mc/fsl_dpmng.h> 28 #include "dpaa2_ethdev.h" 29 #include "dpaa2_sparser.h" 30 #include <fsl_qbman_debug.h> 31 32 #define DRIVER_LOOPBACK_MODE "drv_loopback" 33 #define DRIVER_NO_PREFETCH_MODE "drv_no_prefetch" 34 35 /* Supported Rx offloads */ 36 static uint64_t dev_rx_offloads_sup = 37 DEV_RX_OFFLOAD_CHECKSUM | 38 DEV_RX_OFFLOAD_SCTP_CKSUM | 39 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 40 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | 41 DEV_RX_OFFLOAD_VLAN_STRIP | 42 DEV_RX_OFFLOAD_VLAN_FILTER | 43 DEV_RX_OFFLOAD_JUMBO_FRAME | 44 DEV_RX_OFFLOAD_TIMESTAMP; 45 46 /* Rx offloads which cannot be disabled */ 47 static uint64_t dev_rx_offloads_nodis = 48 DEV_RX_OFFLOAD_RSS_HASH | 49 DEV_RX_OFFLOAD_SCATTER; 50 51 /* Supported Tx offloads */ 52 static uint64_t dev_tx_offloads_sup = 53 DEV_TX_OFFLOAD_VLAN_INSERT | 54 DEV_TX_OFFLOAD_IPV4_CKSUM | 55 DEV_TX_OFFLOAD_UDP_CKSUM | 56 DEV_TX_OFFLOAD_TCP_CKSUM | 57 DEV_TX_OFFLOAD_SCTP_CKSUM | 58 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 59 DEV_TX_OFFLOAD_MT_LOCKFREE | 60 DEV_TX_OFFLOAD_MBUF_FAST_FREE; 61 62 /* Tx offloads which cannot be disabled */ 63 static uint64_t dev_tx_offloads_nodis = 64 DEV_TX_OFFLOAD_MULTI_SEGS; 65 66 /* enable timestamp in mbuf */ 67 enum pmd_dpaa2_ts dpaa2_enable_ts; 68 69 struct rte_dpaa2_xstats_name_off { 70 char name[RTE_ETH_XSTATS_NAME_SIZE]; 71 uint8_t page_id; /* dpni statistics page id */ 72 uint8_t stats_id; /* stats id in the given page */ 73 }; 74 75 static const struct rte_dpaa2_xstats_name_off dpaa2_xstats_strings[] = { 76 {"ingress_multicast_frames", 0, 2}, 77 {"ingress_multicast_bytes", 0, 3}, 78 {"ingress_broadcast_frames", 0, 4}, 79 {"ingress_broadcast_bytes", 0, 5}, 80 {"egress_multicast_frames", 1, 2}, 81 {"egress_multicast_bytes", 1, 3}, 82 {"egress_broadcast_frames", 1, 4}, 83 {"egress_broadcast_bytes", 1, 5}, 84 {"ingress_filtered_frames", 2, 0}, 85 {"ingress_discarded_frames", 2, 1}, 86 {"ingress_nobuffer_discards", 2, 2}, 87 {"egress_discarded_frames", 2, 3}, 88 {"egress_confirmed_frames", 2, 4}, 89 {"cgr_reject_frames", 4, 0}, 90 {"cgr_reject_bytes", 4, 1}, 91 }; 92 93 static const enum rte_filter_op dpaa2_supported_filter_ops[] = { 94 RTE_ETH_FILTER_ADD, 95 RTE_ETH_FILTER_DELETE, 96 RTE_ETH_FILTER_UPDATE, 97 RTE_ETH_FILTER_FLUSH, 98 RTE_ETH_FILTER_GET 99 }; 100 101 static struct rte_dpaa2_driver rte_dpaa2_pmd; 102 static int dpaa2_dev_uninit(struct rte_eth_dev *eth_dev); 103 static int dpaa2_dev_link_update(struct rte_eth_dev *dev, 104 int wait_to_complete); 105 static int dpaa2_dev_set_link_up(struct rte_eth_dev *dev); 106 static int dpaa2_dev_set_link_down(struct rte_eth_dev *dev); 107 static int dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 108 109 int dpaa2_logtype_pmd; 110 111 void 112 rte_pmd_dpaa2_set_timestamp(enum pmd_dpaa2_ts enable) 113 { 114 dpaa2_enable_ts = enable; 115 } 116 117 static int 118 dpaa2_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 119 { 120 int ret; 121 struct dpaa2_dev_priv *priv = dev->data->dev_private; 122 struct fsl_mc_io *dpni = dev->process_private; 123 124 PMD_INIT_FUNC_TRACE(); 125 126 if (dpni == NULL) { 127 DPAA2_PMD_ERR("dpni is NULL"); 128 return -1; 129 } 130 131 if (on) 132 ret = dpni_add_vlan_id(dpni, CMD_PRI_LOW, priv->token, 133 vlan_id, 0, 0, 0); 134 else 135 ret = dpni_remove_vlan_id(dpni, CMD_PRI_LOW, 136 priv->token, vlan_id); 137 138 if (ret < 0) 139 DPAA2_PMD_ERR("ret = %d Unable to add/rem vlan %d hwid =%d", 140 ret, vlan_id, priv->hw_id); 141 142 return ret; 143 } 144 145 static int 146 dpaa2_vlan_offload_set(struct rte_eth_dev *dev, int mask) 147 { 148 struct dpaa2_dev_priv *priv = dev->data->dev_private; 149 struct fsl_mc_io *dpni = dev->process_private; 150 int ret; 151 152 PMD_INIT_FUNC_TRACE(); 153 154 if (mask & ETH_VLAN_FILTER_MASK) { 155 /* VLAN Filter not avaialble */ 156 if (!priv->max_vlan_filters) { 157 DPAA2_PMD_INFO("VLAN filter not available"); 158 goto next_mask; 159 } 160 161 if (dev->data->dev_conf.rxmode.offloads & 162 DEV_RX_OFFLOAD_VLAN_FILTER) 163 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW, 164 priv->token, true); 165 else 166 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW, 167 priv->token, false); 168 if (ret < 0) 169 DPAA2_PMD_INFO("Unable to set vlan filter = %d", ret); 170 } 171 next_mask: 172 if (mask & ETH_VLAN_EXTEND_MASK) { 173 if (dev->data->dev_conf.rxmode.offloads & 174 DEV_RX_OFFLOAD_VLAN_EXTEND) 175 DPAA2_PMD_INFO("VLAN extend offload not supported"); 176 } 177 178 return 0; 179 } 180 181 static int 182 dpaa2_vlan_tpid_set(struct rte_eth_dev *dev, 183 enum rte_vlan_type vlan_type __rte_unused, 184 uint16_t tpid) 185 { 186 struct dpaa2_dev_priv *priv = dev->data->dev_private; 187 struct fsl_mc_io *dpni = dev->process_private; 188 int ret = -ENOTSUP; 189 190 PMD_INIT_FUNC_TRACE(); 191 192 /* nothing to be done for standard vlan tpids */ 193 if (tpid == 0x8100 || tpid == 0x88A8) 194 return 0; 195 196 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW, 197 priv->token, tpid); 198 if (ret < 0) 199 DPAA2_PMD_INFO("Unable to set vlan tpid = %d", ret); 200 /* if already configured tpids, remove them first */ 201 if (ret == -EBUSY) { 202 struct dpni_custom_tpid_cfg tpid_list = {0}; 203 204 ret = dpni_get_custom_tpid(dpni, CMD_PRI_LOW, 205 priv->token, &tpid_list); 206 if (ret < 0) 207 goto fail; 208 ret = dpni_remove_custom_tpid(dpni, CMD_PRI_LOW, 209 priv->token, tpid_list.tpid1); 210 if (ret < 0) 211 goto fail; 212 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW, 213 priv->token, tpid); 214 } 215 fail: 216 return ret; 217 } 218 219 static int 220 dpaa2_fw_version_get(struct rte_eth_dev *dev, 221 char *fw_version, 222 size_t fw_size) 223 { 224 int ret; 225 struct fsl_mc_io *dpni = dev->process_private; 226 struct mc_soc_version mc_plat_info = {0}; 227 struct mc_version mc_ver_info = {0}; 228 229 PMD_INIT_FUNC_TRACE(); 230 231 if (mc_get_soc_version(dpni, CMD_PRI_LOW, &mc_plat_info)) 232 DPAA2_PMD_WARN("\tmc_get_soc_version failed"); 233 234 if (mc_get_version(dpni, CMD_PRI_LOW, &mc_ver_info)) 235 DPAA2_PMD_WARN("\tmc_get_version failed"); 236 237 ret = snprintf(fw_version, fw_size, 238 "%x-%d.%d.%d", 239 mc_plat_info.svr, 240 mc_ver_info.major, 241 mc_ver_info.minor, 242 mc_ver_info.revision); 243 244 ret += 1; /* add the size of '\0' */ 245 if (fw_size < (uint32_t)ret) 246 return ret; 247 else 248 return 0; 249 } 250 251 static int 252 dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 253 { 254 struct dpaa2_dev_priv *priv = dev->data->dev_private; 255 256 PMD_INIT_FUNC_TRACE(); 257 258 dev_info->if_index = priv->hw_id; 259 260 dev_info->max_mac_addrs = priv->max_mac_filters; 261 dev_info->max_rx_pktlen = DPAA2_MAX_RX_PKT_LEN; 262 dev_info->min_rx_bufsize = DPAA2_MIN_RX_BUF_SIZE; 263 dev_info->max_rx_queues = (uint16_t)priv->nb_rx_queues; 264 dev_info->max_tx_queues = (uint16_t)priv->nb_tx_queues; 265 dev_info->rx_offload_capa = dev_rx_offloads_sup | 266 dev_rx_offloads_nodis; 267 dev_info->tx_offload_capa = dev_tx_offloads_sup | 268 dev_tx_offloads_nodis; 269 dev_info->speed_capa = ETH_LINK_SPEED_1G | 270 ETH_LINK_SPEED_2_5G | 271 ETH_LINK_SPEED_10G; 272 273 dev_info->max_hash_mac_addrs = 0; 274 dev_info->max_vfs = 0; 275 dev_info->max_vmdq_pools = ETH_16_POOLS; 276 dev_info->flow_type_rss_offloads = DPAA2_RSS_OFFLOAD_ALL; 277 278 dev_info->default_rxportconf.burst_size = dpaa2_dqrr_size; 279 /* same is rx size for best perf */ 280 dev_info->default_txportconf.burst_size = dpaa2_dqrr_size; 281 282 dev_info->default_rxportconf.nb_queues = 1; 283 dev_info->default_txportconf.nb_queues = 1; 284 dev_info->default_txportconf.ring_size = CONG_ENTER_TX_THRESHOLD; 285 dev_info->default_rxportconf.ring_size = DPAA2_RX_DEFAULT_NBDESC; 286 287 if (dpaa2_svr_family == SVR_LX2160A) { 288 dev_info->speed_capa |= ETH_LINK_SPEED_25G | 289 ETH_LINK_SPEED_40G | 290 ETH_LINK_SPEED_50G | 291 ETH_LINK_SPEED_100G; 292 } 293 294 return 0; 295 } 296 297 static int 298 dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev) 299 { 300 struct dpaa2_dev_priv *priv = dev->data->dev_private; 301 uint16_t dist_idx; 302 uint32_t vq_id; 303 uint8_t num_rxqueue_per_tc; 304 struct dpaa2_queue *mc_q, *mcq; 305 uint32_t tot_queues; 306 int i; 307 struct dpaa2_queue *dpaa2_q; 308 309 PMD_INIT_FUNC_TRACE(); 310 311 num_rxqueue_per_tc = (priv->nb_rx_queues / priv->num_rx_tc); 312 if (priv->tx_conf_en) 313 tot_queues = priv->nb_rx_queues + 2 * priv->nb_tx_queues; 314 else 315 tot_queues = priv->nb_rx_queues + priv->nb_tx_queues; 316 mc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues, 317 RTE_CACHE_LINE_SIZE); 318 if (!mc_q) { 319 DPAA2_PMD_ERR("Memory allocation failed for rx/tx queues"); 320 return -1; 321 } 322 323 for (i = 0; i < priv->nb_rx_queues; i++) { 324 mc_q->eth_data = dev->data; 325 priv->rx_vq[i] = mc_q++; 326 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i]; 327 dpaa2_q->q_storage = rte_malloc("dq_storage", 328 sizeof(struct queue_storage_info_t), 329 RTE_CACHE_LINE_SIZE); 330 if (!dpaa2_q->q_storage) 331 goto fail; 332 333 memset(dpaa2_q->q_storage, 0, 334 sizeof(struct queue_storage_info_t)); 335 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage)) 336 goto fail; 337 } 338 339 for (i = 0; i < priv->nb_tx_queues; i++) { 340 mc_q->eth_data = dev->data; 341 mc_q->flow_id = 0xffff; 342 priv->tx_vq[i] = mc_q++; 343 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; 344 dpaa2_q->cscn = rte_malloc(NULL, 345 sizeof(struct qbman_result), 16); 346 if (!dpaa2_q->cscn) 347 goto fail_tx; 348 } 349 350 if (priv->tx_conf_en) { 351 /*Setup tx confirmation queues*/ 352 for (i = 0; i < priv->nb_tx_queues; i++) { 353 mc_q->eth_data = dev->data; 354 mc_q->tc_index = i; 355 mc_q->flow_id = 0; 356 priv->tx_conf_vq[i] = mc_q++; 357 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i]; 358 dpaa2_q->q_storage = 359 rte_malloc("dq_storage", 360 sizeof(struct queue_storage_info_t), 361 RTE_CACHE_LINE_SIZE); 362 if (!dpaa2_q->q_storage) 363 goto fail_tx_conf; 364 365 memset(dpaa2_q->q_storage, 0, 366 sizeof(struct queue_storage_info_t)); 367 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage)) 368 goto fail_tx_conf; 369 } 370 } 371 372 vq_id = 0; 373 for (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) { 374 mcq = (struct dpaa2_queue *)priv->rx_vq[vq_id]; 375 mcq->tc_index = dist_idx / num_rxqueue_per_tc; 376 mcq->flow_id = dist_idx % num_rxqueue_per_tc; 377 vq_id++; 378 } 379 380 return 0; 381 fail_tx_conf: 382 i -= 1; 383 while (i >= 0) { 384 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i]; 385 rte_free(dpaa2_q->q_storage); 386 priv->tx_conf_vq[i--] = NULL; 387 } 388 i = priv->nb_tx_queues; 389 fail_tx: 390 i -= 1; 391 while (i >= 0) { 392 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; 393 rte_free(dpaa2_q->cscn); 394 priv->tx_vq[i--] = NULL; 395 } 396 i = priv->nb_rx_queues; 397 fail: 398 i -= 1; 399 mc_q = priv->rx_vq[0]; 400 while (i >= 0) { 401 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i]; 402 dpaa2_free_dq_storage(dpaa2_q->q_storage); 403 rte_free(dpaa2_q->q_storage); 404 priv->rx_vq[i--] = NULL; 405 } 406 rte_free(mc_q); 407 return -1; 408 } 409 410 static void 411 dpaa2_free_rx_tx_queues(struct rte_eth_dev *dev) 412 { 413 struct dpaa2_dev_priv *priv = dev->data->dev_private; 414 struct dpaa2_queue *dpaa2_q; 415 int i; 416 417 PMD_INIT_FUNC_TRACE(); 418 419 /* Queue allocation base */ 420 if (priv->rx_vq[0]) { 421 /* cleaning up queue storage */ 422 for (i = 0; i < priv->nb_rx_queues; i++) { 423 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i]; 424 if (dpaa2_q->q_storage) 425 rte_free(dpaa2_q->q_storage); 426 } 427 /* cleanup tx queue cscn */ 428 for (i = 0; i < priv->nb_tx_queues; i++) { 429 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; 430 rte_free(dpaa2_q->cscn); 431 } 432 if (priv->tx_conf_en) { 433 /* cleanup tx conf queue storage */ 434 for (i = 0; i < priv->nb_tx_queues; i++) { 435 dpaa2_q = (struct dpaa2_queue *) 436 priv->tx_conf_vq[i]; 437 rte_free(dpaa2_q->q_storage); 438 } 439 } 440 /*free memory for all queues (RX+TX) */ 441 rte_free(priv->rx_vq[0]); 442 priv->rx_vq[0] = NULL; 443 } 444 } 445 446 static int 447 dpaa2_eth_dev_configure(struct rte_eth_dev *dev) 448 { 449 struct dpaa2_dev_priv *priv = dev->data->dev_private; 450 struct fsl_mc_io *dpni = dev->process_private; 451 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 452 uint64_t rx_offloads = eth_conf->rxmode.offloads; 453 uint64_t tx_offloads = eth_conf->txmode.offloads; 454 int rx_l3_csum_offload = false; 455 int rx_l4_csum_offload = false; 456 int tx_l3_csum_offload = false; 457 int tx_l4_csum_offload = false; 458 int ret; 459 460 PMD_INIT_FUNC_TRACE(); 461 462 /* Rx offloads which are enabled by default */ 463 if (dev_rx_offloads_nodis & ~rx_offloads) { 464 DPAA2_PMD_INFO( 465 "Some of rx offloads enabled by default - requested 0x%" PRIx64 466 " fixed are 0x%" PRIx64, 467 rx_offloads, dev_rx_offloads_nodis); 468 } 469 470 /* Tx offloads which are enabled by default */ 471 if (dev_tx_offloads_nodis & ~tx_offloads) { 472 DPAA2_PMD_INFO( 473 "Some of tx offloads enabled by default - requested 0x%" PRIx64 474 " fixed are 0x%" PRIx64, 475 tx_offloads, dev_tx_offloads_nodis); 476 } 477 478 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 479 if (eth_conf->rxmode.max_rx_pkt_len <= DPAA2_MAX_RX_PKT_LEN) { 480 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, 481 priv->token, eth_conf->rxmode.max_rx_pkt_len 482 - RTE_ETHER_CRC_LEN); 483 if (ret) { 484 DPAA2_PMD_ERR( 485 "Unable to set mtu. check config"); 486 return ret; 487 } 488 dev->data->mtu = 489 dev->data->dev_conf.rxmode.max_rx_pkt_len - 490 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - 491 VLAN_TAG_SIZE; 492 } else { 493 return -1; 494 } 495 } 496 497 if (eth_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) { 498 ret = dpaa2_setup_flow_dist(dev, 499 eth_conf->rx_adv_conf.rss_conf.rss_hf); 500 if (ret) { 501 DPAA2_PMD_ERR("Unable to set flow distribution." 502 "Check queue config"); 503 return ret; 504 } 505 } 506 507 if (rx_offloads & DEV_RX_OFFLOAD_IPV4_CKSUM) 508 rx_l3_csum_offload = true; 509 510 if ((rx_offloads & DEV_RX_OFFLOAD_UDP_CKSUM) || 511 (rx_offloads & DEV_RX_OFFLOAD_TCP_CKSUM) || 512 (rx_offloads & DEV_RX_OFFLOAD_SCTP_CKSUM)) 513 rx_l4_csum_offload = true; 514 515 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 516 DPNI_OFF_RX_L3_CSUM, rx_l3_csum_offload); 517 if (ret) { 518 DPAA2_PMD_ERR("Error to set RX l3 csum:Error = %d", ret); 519 return ret; 520 } 521 522 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 523 DPNI_OFF_RX_L4_CSUM, rx_l4_csum_offload); 524 if (ret) { 525 DPAA2_PMD_ERR("Error to get RX l4 csum:Error = %d", ret); 526 return ret; 527 } 528 529 if (rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) 530 dpaa2_enable_ts = true; 531 532 if (tx_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM) 533 tx_l3_csum_offload = true; 534 535 if ((tx_offloads & DEV_TX_OFFLOAD_UDP_CKSUM) || 536 (tx_offloads & DEV_TX_OFFLOAD_TCP_CKSUM) || 537 (tx_offloads & DEV_TX_OFFLOAD_SCTP_CKSUM)) 538 tx_l4_csum_offload = true; 539 540 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 541 DPNI_OFF_TX_L3_CSUM, tx_l3_csum_offload); 542 if (ret) { 543 DPAA2_PMD_ERR("Error to set TX l3 csum:Error = %d", ret); 544 return ret; 545 } 546 547 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 548 DPNI_OFF_TX_L4_CSUM, tx_l4_csum_offload); 549 if (ret) { 550 DPAA2_PMD_ERR("Error to get TX l4 csum:Error = %d", ret); 551 return ret; 552 } 553 554 /* Enabling hash results in FD requires setting DPNI_FLCTYPE_HASH in 555 * dpni_set_offload API. Setting this FLCTYPE for DPNI sets the FD[SC] 556 * to 0 for LS2 in the hardware thus disabling data/annotation 557 * stashing. For LX2 this is fixed in hardware and thus hash result and 558 * parse results can be received in FD using this option. 559 */ 560 if (dpaa2_svr_family == SVR_LX2160A) { 561 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 562 DPNI_FLCTYPE_HASH, true); 563 if (ret) { 564 DPAA2_PMD_ERR("Error setting FLCTYPE: Err = %d", ret); 565 return ret; 566 } 567 } 568 569 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 570 dpaa2_vlan_offload_set(dev, ETH_VLAN_FILTER_MASK); 571 572 return 0; 573 } 574 575 /* Function to setup RX flow information. It contains traffic class ID, 576 * flow ID, destination configuration etc. 577 */ 578 static int 579 dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev, 580 uint16_t rx_queue_id, 581 uint16_t nb_rx_desc, 582 unsigned int socket_id __rte_unused, 583 const struct rte_eth_rxconf *rx_conf __rte_unused, 584 struct rte_mempool *mb_pool) 585 { 586 struct dpaa2_dev_priv *priv = dev->data->dev_private; 587 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 588 struct dpaa2_queue *dpaa2_q; 589 struct dpni_queue cfg; 590 uint8_t options = 0; 591 uint8_t flow_id; 592 uint32_t bpid; 593 int i, ret; 594 595 PMD_INIT_FUNC_TRACE(); 596 597 DPAA2_PMD_DEBUG("dev =%p, queue =%d, pool = %p, conf =%p", 598 dev, rx_queue_id, mb_pool, rx_conf); 599 600 if (!priv->bp_list || priv->bp_list->mp != mb_pool) { 601 bpid = mempool_to_bpid(mb_pool); 602 ret = dpaa2_attach_bp_list(priv, 603 rte_dpaa2_bpid_info[bpid].bp_list); 604 if (ret) 605 return ret; 606 } 607 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id]; 608 dpaa2_q->mb_pool = mb_pool; /**< mbuf pool to populate RX ring. */ 609 dpaa2_q->bp_array = rte_dpaa2_bpid_info; 610 611 /*Get the flow id from given VQ id*/ 612 flow_id = dpaa2_q->flow_id; 613 memset(&cfg, 0, sizeof(struct dpni_queue)); 614 615 options = options | DPNI_QUEUE_OPT_USER_CTX; 616 cfg.user_context = (size_t)(dpaa2_q); 617 618 /* check if a private cgr available. */ 619 for (i = 0; i < priv->max_cgs; i++) { 620 if (!priv->cgid_in_use[i]) { 621 priv->cgid_in_use[i] = 1; 622 break; 623 } 624 } 625 626 if (i < priv->max_cgs) { 627 options |= DPNI_QUEUE_OPT_SET_CGID; 628 cfg.cgid = i; 629 dpaa2_q->cgid = cfg.cgid; 630 } else { 631 dpaa2_q->cgid = 0xff; 632 } 633 634 /*if ls2088 or rev2 device, enable the stashing */ 635 636 if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) { 637 options |= DPNI_QUEUE_OPT_FLC; 638 cfg.flc.stash_control = true; 639 cfg.flc.value &= 0xFFFFFFFFFFFFFFC0; 640 /* 00 00 00 - last 6 bit represent annotation, context stashing, 641 * data stashing setting 01 01 00 (0x14) 642 * (in following order ->DS AS CS) 643 * to enable 1 line data, 1 line annotation. 644 * For LX2, this setting should be 01 00 00 (0x10) 645 */ 646 if ((dpaa2_svr_family & 0xffff0000) == SVR_LX2160A) 647 cfg.flc.value |= 0x10; 648 else 649 cfg.flc.value |= 0x14; 650 } 651 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX, 652 dpaa2_q->tc_index, flow_id, options, &cfg); 653 if (ret) { 654 DPAA2_PMD_ERR("Error in setting the rx flow: = %d", ret); 655 return -1; 656 } 657 658 if (!(priv->flags & DPAA2_RX_TAILDROP_OFF)) { 659 struct dpni_taildrop taildrop; 660 661 taildrop.enable = 1; 662 663 /* Private CGR will use tail drop length as nb_rx_desc. 664 * for rest cases we can use standard byte based tail drop. 665 * There is no HW restriction, but number of CGRs are limited, 666 * hence this restriction is placed. 667 */ 668 if (dpaa2_q->cgid != 0xff) { 669 /*enabling per rx queue congestion control */ 670 taildrop.threshold = nb_rx_desc; 671 taildrop.units = DPNI_CONGESTION_UNIT_FRAMES; 672 taildrop.oal = 0; 673 DPAA2_PMD_DEBUG("Enabling CG Tail Drop on queue = %d", 674 rx_queue_id); 675 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token, 676 DPNI_CP_CONGESTION_GROUP, 677 DPNI_QUEUE_RX, 678 dpaa2_q->tc_index, 679 dpaa2_q->cgid, &taildrop); 680 } else { 681 /*enabling per rx queue congestion control */ 682 taildrop.threshold = CONG_THRESHOLD_RX_BYTES_Q; 683 taildrop.units = DPNI_CONGESTION_UNIT_BYTES; 684 taildrop.oal = CONG_RX_OAL; 685 DPAA2_PMD_DEBUG("Enabling Byte based Drop on queue= %d", 686 rx_queue_id); 687 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token, 688 DPNI_CP_QUEUE, DPNI_QUEUE_RX, 689 dpaa2_q->tc_index, flow_id, 690 &taildrop); 691 } 692 if (ret) { 693 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)", 694 ret); 695 return -1; 696 } 697 } else { /* Disable tail Drop */ 698 struct dpni_taildrop taildrop = {0}; 699 DPAA2_PMD_INFO("Tail drop is disabled on queue"); 700 701 taildrop.enable = 0; 702 if (dpaa2_q->cgid != 0xff) { 703 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token, 704 DPNI_CP_CONGESTION_GROUP, DPNI_QUEUE_RX, 705 dpaa2_q->tc_index, 706 dpaa2_q->cgid, &taildrop); 707 } else { 708 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token, 709 DPNI_CP_QUEUE, DPNI_QUEUE_RX, 710 dpaa2_q->tc_index, flow_id, &taildrop); 711 } 712 if (ret) { 713 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)", 714 ret); 715 return -1; 716 } 717 } 718 719 dev->data->rx_queues[rx_queue_id] = dpaa2_q; 720 return 0; 721 } 722 723 static int 724 dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev, 725 uint16_t tx_queue_id, 726 uint16_t nb_tx_desc __rte_unused, 727 unsigned int socket_id __rte_unused, 728 const struct rte_eth_txconf *tx_conf __rte_unused) 729 { 730 struct dpaa2_dev_priv *priv = dev->data->dev_private; 731 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *) 732 priv->tx_vq[tx_queue_id]; 733 struct dpaa2_queue *dpaa2_tx_conf_q = (struct dpaa2_queue *) 734 priv->tx_conf_vq[tx_queue_id]; 735 struct fsl_mc_io *dpni = dev->process_private; 736 struct dpni_queue tx_conf_cfg; 737 struct dpni_queue tx_flow_cfg; 738 uint8_t options = 0, flow_id; 739 struct dpni_queue_id qid; 740 uint32_t tc_id; 741 int ret; 742 743 PMD_INIT_FUNC_TRACE(); 744 745 /* Return if queue already configured */ 746 if (dpaa2_q->flow_id != 0xffff) { 747 dev->data->tx_queues[tx_queue_id] = dpaa2_q; 748 return 0; 749 } 750 751 memset(&tx_conf_cfg, 0, sizeof(struct dpni_queue)); 752 memset(&tx_flow_cfg, 0, sizeof(struct dpni_queue)); 753 754 tc_id = tx_queue_id; 755 flow_id = 0; 756 757 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX, 758 tc_id, flow_id, options, &tx_flow_cfg); 759 if (ret) { 760 DPAA2_PMD_ERR("Error in setting the tx flow: " 761 "tc_id=%d, flow=%d err=%d", 762 tc_id, flow_id, ret); 763 return -1; 764 } 765 766 dpaa2_q->flow_id = flow_id; 767 768 if (tx_queue_id == 0) { 769 /*Set tx-conf and error configuration*/ 770 if (priv->tx_conf_en) 771 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW, 772 priv->token, 773 DPNI_CONF_AFFINE); 774 else 775 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW, 776 priv->token, 777 DPNI_CONF_DISABLE); 778 if (ret) { 779 DPAA2_PMD_ERR("Error in set tx conf mode settings: " 780 "err=%d", ret); 781 return -1; 782 } 783 } 784 dpaa2_q->tc_index = tc_id; 785 786 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token, 787 DPNI_QUEUE_TX, dpaa2_q->tc_index, 788 dpaa2_q->flow_id, &tx_flow_cfg, &qid); 789 if (ret) { 790 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret); 791 return -1; 792 } 793 dpaa2_q->fqid = qid.fqid; 794 795 if (!(priv->flags & DPAA2_TX_CGR_OFF)) { 796 struct dpni_congestion_notification_cfg cong_notif_cfg = {0}; 797 798 cong_notif_cfg.units = DPNI_CONGESTION_UNIT_FRAMES; 799 cong_notif_cfg.threshold_entry = CONG_ENTER_TX_THRESHOLD; 800 /* Notify that the queue is not congested when the data in 801 * the queue is below this thershold. 802 */ 803 cong_notif_cfg.threshold_exit = CONG_EXIT_TX_THRESHOLD; 804 cong_notif_cfg.message_ctx = 0; 805 cong_notif_cfg.message_iova = 806 (size_t)DPAA2_VADDR_TO_IOVA(dpaa2_q->cscn); 807 cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE; 808 cong_notif_cfg.notification_mode = 809 DPNI_CONG_OPT_WRITE_MEM_ON_ENTER | 810 DPNI_CONG_OPT_WRITE_MEM_ON_EXIT | 811 DPNI_CONG_OPT_COHERENT_WRITE; 812 cong_notif_cfg.cg_point = DPNI_CP_QUEUE; 813 814 ret = dpni_set_congestion_notification(dpni, CMD_PRI_LOW, 815 priv->token, 816 DPNI_QUEUE_TX, 817 tc_id, 818 &cong_notif_cfg); 819 if (ret) { 820 DPAA2_PMD_ERR( 821 "Error in setting tx congestion notification: " 822 "err=%d", ret); 823 return -ret; 824 } 825 } 826 dpaa2_q->cb_eqresp_free = dpaa2_dev_free_eqresp_buf; 827 dev->data->tx_queues[tx_queue_id] = dpaa2_q; 828 829 if (priv->tx_conf_en) { 830 dpaa2_q->tx_conf_queue = dpaa2_tx_conf_q; 831 options = options | DPNI_QUEUE_OPT_USER_CTX; 832 tx_conf_cfg.user_context = (size_t)(dpaa2_q); 833 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, 834 DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index, 835 dpaa2_tx_conf_q->flow_id, options, &tx_conf_cfg); 836 if (ret) { 837 DPAA2_PMD_ERR("Error in setting the tx conf flow: " 838 "tc_index=%d, flow=%d err=%d", 839 dpaa2_tx_conf_q->tc_index, 840 dpaa2_tx_conf_q->flow_id, ret); 841 return -1; 842 } 843 844 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token, 845 DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index, 846 dpaa2_tx_conf_q->flow_id, &tx_conf_cfg, &qid); 847 if (ret) { 848 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret); 849 return -1; 850 } 851 dpaa2_tx_conf_q->fqid = qid.fqid; 852 } 853 return 0; 854 } 855 856 static void 857 dpaa2_dev_rx_queue_release(void *q __rte_unused) 858 { 859 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)q; 860 struct dpaa2_dev_priv *priv = dpaa2_q->eth_data->dev_private; 861 struct fsl_mc_io *dpni = 862 (struct fsl_mc_io *)priv->eth_dev->process_private; 863 uint8_t options = 0; 864 int ret; 865 struct dpni_queue cfg; 866 867 memset(&cfg, 0, sizeof(struct dpni_queue)); 868 PMD_INIT_FUNC_TRACE(); 869 if (dpaa2_q->cgid != 0xff) { 870 options = DPNI_QUEUE_OPT_CLEAR_CGID; 871 cfg.cgid = dpaa2_q->cgid; 872 873 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, 874 DPNI_QUEUE_RX, 875 dpaa2_q->tc_index, dpaa2_q->flow_id, 876 options, &cfg); 877 if (ret) 878 DPAA2_PMD_ERR("Unable to clear CGR from q=%u err=%d", 879 dpaa2_q->fqid, ret); 880 priv->cgid_in_use[dpaa2_q->cgid] = 0; 881 dpaa2_q->cgid = 0xff; 882 } 883 } 884 885 static void 886 dpaa2_dev_tx_queue_release(void *q __rte_unused) 887 { 888 PMD_INIT_FUNC_TRACE(); 889 } 890 891 static uint32_t 892 dpaa2_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id) 893 { 894 int32_t ret; 895 struct dpaa2_dev_priv *priv = dev->data->dev_private; 896 struct dpaa2_queue *dpaa2_q; 897 struct qbman_swp *swp; 898 struct qbman_fq_query_np_rslt state; 899 uint32_t frame_cnt = 0; 900 901 if (unlikely(!DPAA2_PER_LCORE_DPIO)) { 902 ret = dpaa2_affine_qbman_swp(); 903 if (ret) { 904 DPAA2_PMD_ERR( 905 "Failed to allocate IO portal, tid: %d\n", 906 rte_gettid()); 907 return -EINVAL; 908 } 909 } 910 swp = DPAA2_PER_LCORE_PORTAL; 911 912 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id]; 913 914 if (qbman_fq_query_state(swp, dpaa2_q->fqid, &state) == 0) { 915 frame_cnt = qbman_fq_state_frame_count(&state); 916 DPAA2_PMD_DP_DEBUG("RX frame count for q(%d) is %u", 917 rx_queue_id, frame_cnt); 918 } 919 return frame_cnt; 920 } 921 922 static const uint32_t * 923 dpaa2_supported_ptypes_get(struct rte_eth_dev *dev) 924 { 925 static const uint32_t ptypes[] = { 926 /*todo -= add more types */ 927 RTE_PTYPE_L2_ETHER, 928 RTE_PTYPE_L3_IPV4, 929 RTE_PTYPE_L3_IPV4_EXT, 930 RTE_PTYPE_L3_IPV6, 931 RTE_PTYPE_L3_IPV6_EXT, 932 RTE_PTYPE_L4_TCP, 933 RTE_PTYPE_L4_UDP, 934 RTE_PTYPE_L4_SCTP, 935 RTE_PTYPE_L4_ICMP, 936 RTE_PTYPE_UNKNOWN 937 }; 938 939 if (dev->rx_pkt_burst == dpaa2_dev_prefetch_rx || 940 dev->rx_pkt_burst == dpaa2_dev_rx || 941 dev->rx_pkt_burst == dpaa2_dev_loopback_rx) 942 return ptypes; 943 return NULL; 944 } 945 946 /** 947 * Dpaa2 link Interrupt handler 948 * 949 * @param param 950 * The address of parameter (struct rte_eth_dev *) regsitered before. 951 * 952 * @return 953 * void 954 */ 955 static void 956 dpaa2_interrupt_handler(void *param) 957 { 958 struct rte_eth_dev *dev = param; 959 struct dpaa2_dev_priv *priv = dev->data->dev_private; 960 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 961 int ret; 962 int irq_index = DPNI_IRQ_INDEX; 963 unsigned int status = 0, clear = 0; 964 965 PMD_INIT_FUNC_TRACE(); 966 967 if (dpni == NULL) { 968 DPAA2_PMD_ERR("dpni is NULL"); 969 return; 970 } 971 972 ret = dpni_get_irq_status(dpni, CMD_PRI_LOW, priv->token, 973 irq_index, &status); 974 if (unlikely(ret)) { 975 DPAA2_PMD_ERR("Can't get irq status (err %d)", ret); 976 clear = 0xffffffff; 977 goto out; 978 } 979 980 if (status & DPNI_IRQ_EVENT_LINK_CHANGED) { 981 clear = DPNI_IRQ_EVENT_LINK_CHANGED; 982 dpaa2_dev_link_update(dev, 0); 983 /* calling all the apps registered for link status event */ 984 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, 985 NULL); 986 } 987 out: 988 ret = dpni_clear_irq_status(dpni, CMD_PRI_LOW, priv->token, 989 irq_index, clear); 990 if (unlikely(ret)) 991 DPAA2_PMD_ERR("Can't clear irq status (err %d)", ret); 992 } 993 994 static int 995 dpaa2_eth_setup_irqs(struct rte_eth_dev *dev, int enable) 996 { 997 int err = 0; 998 struct dpaa2_dev_priv *priv = dev->data->dev_private; 999 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1000 int irq_index = DPNI_IRQ_INDEX; 1001 unsigned int mask = DPNI_IRQ_EVENT_LINK_CHANGED; 1002 1003 PMD_INIT_FUNC_TRACE(); 1004 1005 err = dpni_set_irq_mask(dpni, CMD_PRI_LOW, priv->token, 1006 irq_index, mask); 1007 if (err < 0) { 1008 DPAA2_PMD_ERR("Error: dpni_set_irq_mask():%d (%s)", err, 1009 strerror(-err)); 1010 return err; 1011 } 1012 1013 err = dpni_set_irq_enable(dpni, CMD_PRI_LOW, priv->token, 1014 irq_index, enable); 1015 if (err < 0) 1016 DPAA2_PMD_ERR("Error: dpni_set_irq_enable():%d (%s)", err, 1017 strerror(-err)); 1018 1019 return err; 1020 } 1021 1022 static int 1023 dpaa2_dev_start(struct rte_eth_dev *dev) 1024 { 1025 struct rte_device *rdev = dev->device; 1026 struct rte_dpaa2_device *dpaa2_dev; 1027 struct rte_eth_dev_data *data = dev->data; 1028 struct dpaa2_dev_priv *priv = data->dev_private; 1029 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1030 struct dpni_queue cfg; 1031 struct dpni_error_cfg err_cfg; 1032 uint16_t qdid; 1033 struct dpni_queue_id qid; 1034 struct dpaa2_queue *dpaa2_q; 1035 int ret, i; 1036 struct rte_intr_handle *intr_handle; 1037 1038 dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device); 1039 intr_handle = &dpaa2_dev->intr_handle; 1040 1041 PMD_INIT_FUNC_TRACE(); 1042 1043 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token); 1044 if (ret) { 1045 DPAA2_PMD_ERR("Failure in enabling dpni %d device: err=%d", 1046 priv->hw_id, ret); 1047 return ret; 1048 } 1049 1050 /* Power up the phy. Needed to make the link go UP */ 1051 dpaa2_dev_set_link_up(dev); 1052 1053 ret = dpni_get_qdid(dpni, CMD_PRI_LOW, priv->token, 1054 DPNI_QUEUE_TX, &qdid); 1055 if (ret) { 1056 DPAA2_PMD_ERR("Error in getting qdid: err=%d", ret); 1057 return ret; 1058 } 1059 priv->qdid = qdid; 1060 1061 for (i = 0; i < data->nb_rx_queues; i++) { 1062 dpaa2_q = (struct dpaa2_queue *)data->rx_queues[i]; 1063 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token, 1064 DPNI_QUEUE_RX, dpaa2_q->tc_index, 1065 dpaa2_q->flow_id, &cfg, &qid); 1066 if (ret) { 1067 DPAA2_PMD_ERR("Error in getting flow information: " 1068 "err=%d", ret); 1069 return ret; 1070 } 1071 dpaa2_q->fqid = qid.fqid; 1072 } 1073 1074 /*checksum errors, send them to normal path and set it in annotation */ 1075 err_cfg.errors = DPNI_ERROR_L3CE | DPNI_ERROR_L4CE; 1076 err_cfg.errors |= DPNI_ERROR_PHE; 1077 1078 err_cfg.error_action = DPNI_ERROR_ACTION_CONTINUE; 1079 err_cfg.set_frame_annotation = true; 1080 1081 ret = dpni_set_errors_behavior(dpni, CMD_PRI_LOW, 1082 priv->token, &err_cfg); 1083 if (ret) { 1084 DPAA2_PMD_ERR("Error to dpni_set_errors_behavior: code = %d", 1085 ret); 1086 return ret; 1087 } 1088 1089 /* if the interrupts were configured on this devices*/ 1090 if (intr_handle && (intr_handle->fd) && 1091 (dev->data->dev_conf.intr_conf.lsc != 0)) { 1092 /* Registering LSC interrupt handler */ 1093 rte_intr_callback_register(intr_handle, 1094 dpaa2_interrupt_handler, 1095 (void *)dev); 1096 1097 /* enable vfio intr/eventfd mapping 1098 * Interrupt index 0 is required, so we can not use 1099 * rte_intr_enable. 1100 */ 1101 rte_dpaa2_intr_enable(intr_handle, DPNI_IRQ_INDEX); 1102 1103 /* enable dpni_irqs */ 1104 dpaa2_eth_setup_irqs(dev, 1); 1105 } 1106 1107 /* Change the tx burst function if ordered queues are used */ 1108 if (priv->en_ordered) 1109 dev->tx_pkt_burst = dpaa2_dev_tx_ordered; 1110 1111 return 0; 1112 } 1113 1114 /** 1115 * This routine disables all traffic on the adapter by issuing a 1116 * global reset on the MAC. 1117 */ 1118 static void 1119 dpaa2_dev_stop(struct rte_eth_dev *dev) 1120 { 1121 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1122 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1123 int ret; 1124 struct rte_eth_link link; 1125 struct rte_intr_handle *intr_handle = dev->intr_handle; 1126 1127 PMD_INIT_FUNC_TRACE(); 1128 1129 /* reset interrupt callback */ 1130 if (intr_handle && (intr_handle->fd) && 1131 (dev->data->dev_conf.intr_conf.lsc != 0)) { 1132 /*disable dpni irqs */ 1133 dpaa2_eth_setup_irqs(dev, 0); 1134 1135 /* disable vfio intr before callback unregister */ 1136 rte_dpaa2_intr_disable(intr_handle, DPNI_IRQ_INDEX); 1137 1138 /* Unregistering LSC interrupt handler */ 1139 rte_intr_callback_unregister(intr_handle, 1140 dpaa2_interrupt_handler, 1141 (void *)dev); 1142 } 1143 1144 dpaa2_dev_set_link_down(dev); 1145 1146 ret = dpni_disable(dpni, CMD_PRI_LOW, priv->token); 1147 if (ret) { 1148 DPAA2_PMD_ERR("Failure (ret %d) in disabling dpni %d dev", 1149 ret, priv->hw_id); 1150 return; 1151 } 1152 1153 /* clear the recorded link status */ 1154 memset(&link, 0, sizeof(link)); 1155 rte_eth_linkstatus_set(dev, &link); 1156 } 1157 1158 static void 1159 dpaa2_dev_close(struct rte_eth_dev *dev) 1160 { 1161 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1162 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1163 int ret; 1164 struct rte_eth_link link; 1165 1166 PMD_INIT_FUNC_TRACE(); 1167 1168 dpaa2_flow_clean(dev); 1169 1170 /* Clean the device first */ 1171 ret = dpni_reset(dpni, CMD_PRI_LOW, priv->token); 1172 if (ret) { 1173 DPAA2_PMD_ERR("Failure cleaning dpni device: err=%d", ret); 1174 return; 1175 } 1176 1177 memset(&link, 0, sizeof(link)); 1178 rte_eth_linkstatus_set(dev, &link); 1179 } 1180 1181 static int 1182 dpaa2_dev_promiscuous_enable( 1183 struct rte_eth_dev *dev) 1184 { 1185 int ret; 1186 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1187 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1188 1189 PMD_INIT_FUNC_TRACE(); 1190 1191 if (dpni == NULL) { 1192 DPAA2_PMD_ERR("dpni is NULL"); 1193 return -ENODEV; 1194 } 1195 1196 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, true); 1197 if (ret < 0) 1198 DPAA2_PMD_ERR("Unable to enable U promisc mode %d", ret); 1199 1200 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true); 1201 if (ret < 0) 1202 DPAA2_PMD_ERR("Unable to enable M promisc mode %d", ret); 1203 1204 return ret; 1205 } 1206 1207 static int 1208 dpaa2_dev_promiscuous_disable( 1209 struct rte_eth_dev *dev) 1210 { 1211 int ret; 1212 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1213 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1214 1215 PMD_INIT_FUNC_TRACE(); 1216 1217 if (dpni == NULL) { 1218 DPAA2_PMD_ERR("dpni is NULL"); 1219 return -ENODEV; 1220 } 1221 1222 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, false); 1223 if (ret < 0) 1224 DPAA2_PMD_ERR("Unable to disable U promisc mode %d", ret); 1225 1226 if (dev->data->all_multicast == 0) { 1227 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, 1228 priv->token, false); 1229 if (ret < 0) 1230 DPAA2_PMD_ERR("Unable to disable M promisc mode %d", 1231 ret); 1232 } 1233 1234 return ret; 1235 } 1236 1237 static int 1238 dpaa2_dev_allmulticast_enable( 1239 struct rte_eth_dev *dev) 1240 { 1241 int ret; 1242 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1243 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1244 1245 PMD_INIT_FUNC_TRACE(); 1246 1247 if (dpni == NULL) { 1248 DPAA2_PMD_ERR("dpni is NULL"); 1249 return -ENODEV; 1250 } 1251 1252 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true); 1253 if (ret < 0) 1254 DPAA2_PMD_ERR("Unable to enable multicast mode %d", ret); 1255 1256 return ret; 1257 } 1258 1259 static int 1260 dpaa2_dev_allmulticast_disable(struct rte_eth_dev *dev) 1261 { 1262 int ret; 1263 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1264 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1265 1266 PMD_INIT_FUNC_TRACE(); 1267 1268 if (dpni == NULL) { 1269 DPAA2_PMD_ERR("dpni is NULL"); 1270 return -ENODEV; 1271 } 1272 1273 /* must remain on for all promiscuous */ 1274 if (dev->data->promiscuous == 1) 1275 return 0; 1276 1277 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, false); 1278 if (ret < 0) 1279 DPAA2_PMD_ERR("Unable to disable multicast mode %d", ret); 1280 1281 return ret; 1282 } 1283 1284 static int 1285 dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 1286 { 1287 int ret; 1288 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1289 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1290 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN 1291 + VLAN_TAG_SIZE; 1292 1293 PMD_INIT_FUNC_TRACE(); 1294 1295 if (dpni == NULL) { 1296 DPAA2_PMD_ERR("dpni is NULL"); 1297 return -EINVAL; 1298 } 1299 1300 /* check that mtu is within the allowed range */ 1301 if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA2_MAX_RX_PKT_LEN) 1302 return -EINVAL; 1303 1304 if (frame_size > RTE_ETHER_MAX_LEN) 1305 dev->data->dev_conf.rxmode.offloads |= 1306 DEV_RX_OFFLOAD_JUMBO_FRAME; 1307 else 1308 dev->data->dev_conf.rxmode.offloads &= 1309 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 1310 1311 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 1312 1313 /* Set the Max Rx frame length as 'mtu' + 1314 * Maximum Ethernet header length 1315 */ 1316 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, priv->token, 1317 frame_size - RTE_ETHER_CRC_LEN); 1318 if (ret) { 1319 DPAA2_PMD_ERR("Setting the max frame length failed"); 1320 return -1; 1321 } 1322 DPAA2_PMD_INFO("MTU configured for the device: %d", mtu); 1323 return 0; 1324 } 1325 1326 static int 1327 dpaa2_dev_add_mac_addr(struct rte_eth_dev *dev, 1328 struct rte_ether_addr *addr, 1329 __rte_unused uint32_t index, 1330 __rte_unused uint32_t pool) 1331 { 1332 int ret; 1333 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1334 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1335 1336 PMD_INIT_FUNC_TRACE(); 1337 1338 if (dpni == NULL) { 1339 DPAA2_PMD_ERR("dpni is NULL"); 1340 return -1; 1341 } 1342 1343 ret = dpni_add_mac_addr(dpni, CMD_PRI_LOW, priv->token, 1344 addr->addr_bytes, 0, 0, 0); 1345 if (ret) 1346 DPAA2_PMD_ERR( 1347 "error: Adding the MAC ADDR failed: err = %d", ret); 1348 return 0; 1349 } 1350 1351 static void 1352 dpaa2_dev_remove_mac_addr(struct rte_eth_dev *dev, 1353 uint32_t index) 1354 { 1355 int ret; 1356 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1357 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1358 struct rte_eth_dev_data *data = dev->data; 1359 struct rte_ether_addr *macaddr; 1360 1361 PMD_INIT_FUNC_TRACE(); 1362 1363 macaddr = &data->mac_addrs[index]; 1364 1365 if (dpni == NULL) { 1366 DPAA2_PMD_ERR("dpni is NULL"); 1367 return; 1368 } 1369 1370 ret = dpni_remove_mac_addr(dpni, CMD_PRI_LOW, 1371 priv->token, macaddr->addr_bytes); 1372 if (ret) 1373 DPAA2_PMD_ERR( 1374 "error: Removing the MAC ADDR failed: err = %d", ret); 1375 } 1376 1377 static int 1378 dpaa2_dev_set_mac_addr(struct rte_eth_dev *dev, 1379 struct rte_ether_addr *addr) 1380 { 1381 int ret; 1382 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1383 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1384 1385 PMD_INIT_FUNC_TRACE(); 1386 1387 if (dpni == NULL) { 1388 DPAA2_PMD_ERR("dpni is NULL"); 1389 return -EINVAL; 1390 } 1391 1392 ret = dpni_set_primary_mac_addr(dpni, CMD_PRI_LOW, 1393 priv->token, addr->addr_bytes); 1394 1395 if (ret) 1396 DPAA2_PMD_ERR( 1397 "error: Setting the MAC ADDR failed %d", ret); 1398 1399 return ret; 1400 } 1401 1402 static 1403 int dpaa2_dev_stats_get(struct rte_eth_dev *dev, 1404 struct rte_eth_stats *stats) 1405 { 1406 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1407 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1408 int32_t retcode; 1409 uint8_t page0 = 0, page1 = 1, page2 = 2; 1410 union dpni_statistics value; 1411 int i; 1412 struct dpaa2_queue *dpaa2_rxq, *dpaa2_txq; 1413 1414 memset(&value, 0, sizeof(union dpni_statistics)); 1415 1416 PMD_INIT_FUNC_TRACE(); 1417 1418 if (!dpni) { 1419 DPAA2_PMD_ERR("dpni is NULL"); 1420 return -EINVAL; 1421 } 1422 1423 if (!stats) { 1424 DPAA2_PMD_ERR("stats is NULL"); 1425 return -EINVAL; 1426 } 1427 1428 /*Get Counters from page_0*/ 1429 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1430 page0, 0, &value); 1431 if (retcode) 1432 goto err; 1433 1434 stats->ipackets = value.page_0.ingress_all_frames; 1435 stats->ibytes = value.page_0.ingress_all_bytes; 1436 1437 /*Get Counters from page_1*/ 1438 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1439 page1, 0, &value); 1440 if (retcode) 1441 goto err; 1442 1443 stats->opackets = value.page_1.egress_all_frames; 1444 stats->obytes = value.page_1.egress_all_bytes; 1445 1446 /*Get Counters from page_2*/ 1447 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1448 page2, 0, &value); 1449 if (retcode) 1450 goto err; 1451 1452 /* Ingress drop frame count due to configured rules */ 1453 stats->ierrors = value.page_2.ingress_filtered_frames; 1454 /* Ingress drop frame count due to error */ 1455 stats->ierrors += value.page_2.ingress_discarded_frames; 1456 1457 stats->oerrors = value.page_2.egress_discarded_frames; 1458 stats->imissed = value.page_2.ingress_nobuffer_discards; 1459 1460 /* Fill in per queue stats */ 1461 for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) && 1462 (i < priv->nb_rx_queues || i < priv->nb_tx_queues); ++i) { 1463 dpaa2_rxq = (struct dpaa2_queue *)priv->rx_vq[i]; 1464 dpaa2_txq = (struct dpaa2_queue *)priv->tx_vq[i]; 1465 if (dpaa2_rxq) 1466 stats->q_ipackets[i] = dpaa2_rxq->rx_pkts; 1467 if (dpaa2_txq) 1468 stats->q_opackets[i] = dpaa2_txq->tx_pkts; 1469 1470 /* Byte counting is not implemented */ 1471 stats->q_ibytes[i] = 0; 1472 stats->q_obytes[i] = 0; 1473 } 1474 1475 return 0; 1476 1477 err: 1478 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode); 1479 return retcode; 1480 }; 1481 1482 static int 1483 dpaa2_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 1484 unsigned int n) 1485 { 1486 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1487 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1488 int32_t retcode; 1489 union dpni_statistics value[5] = {}; 1490 unsigned int i = 0, num = RTE_DIM(dpaa2_xstats_strings); 1491 1492 if (n < num) 1493 return num; 1494 1495 if (xstats == NULL) 1496 return 0; 1497 1498 /* Get Counters from page_0*/ 1499 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1500 0, 0, &value[0]); 1501 if (retcode) 1502 goto err; 1503 1504 /* Get Counters from page_1*/ 1505 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1506 1, 0, &value[1]); 1507 if (retcode) 1508 goto err; 1509 1510 /* Get Counters from page_2*/ 1511 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1512 2, 0, &value[2]); 1513 if (retcode) 1514 goto err; 1515 1516 for (i = 0; i < priv->max_cgs; i++) { 1517 if (!priv->cgid_in_use[i]) { 1518 /* Get Counters from page_4*/ 1519 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, 1520 priv->token, 1521 4, 0, &value[4]); 1522 if (retcode) 1523 goto err; 1524 break; 1525 } 1526 } 1527 1528 for (i = 0; i < num; i++) { 1529 xstats[i].id = i; 1530 xstats[i].value = value[dpaa2_xstats_strings[i].page_id]. 1531 raw.counter[dpaa2_xstats_strings[i].stats_id]; 1532 } 1533 return i; 1534 err: 1535 DPAA2_PMD_ERR("Error in obtaining extended stats (%d)", retcode); 1536 return retcode; 1537 } 1538 1539 static int 1540 dpaa2_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 1541 struct rte_eth_xstat_name *xstats_names, 1542 unsigned int limit) 1543 { 1544 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings); 1545 1546 if (limit < stat_cnt) 1547 return stat_cnt; 1548 1549 if (xstats_names != NULL) 1550 for (i = 0; i < stat_cnt; i++) 1551 strlcpy(xstats_names[i].name, 1552 dpaa2_xstats_strings[i].name, 1553 sizeof(xstats_names[i].name)); 1554 1555 return stat_cnt; 1556 } 1557 1558 static int 1559 dpaa2_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 1560 uint64_t *values, unsigned int n) 1561 { 1562 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings); 1563 uint64_t values_copy[stat_cnt]; 1564 1565 if (!ids) { 1566 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1567 struct fsl_mc_io *dpni = 1568 (struct fsl_mc_io *)dev->process_private; 1569 int32_t retcode; 1570 union dpni_statistics value[5] = {}; 1571 1572 if (n < stat_cnt) 1573 return stat_cnt; 1574 1575 if (!values) 1576 return 0; 1577 1578 /* Get Counters from page_0*/ 1579 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1580 0, 0, &value[0]); 1581 if (retcode) 1582 return 0; 1583 1584 /* Get Counters from page_1*/ 1585 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1586 1, 0, &value[1]); 1587 if (retcode) 1588 return 0; 1589 1590 /* Get Counters from page_2*/ 1591 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1592 2, 0, &value[2]); 1593 if (retcode) 1594 return 0; 1595 1596 /* Get Counters from page_4*/ 1597 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1598 4, 0, &value[4]); 1599 if (retcode) 1600 return 0; 1601 1602 for (i = 0; i < stat_cnt; i++) { 1603 values[i] = value[dpaa2_xstats_strings[i].page_id]. 1604 raw.counter[dpaa2_xstats_strings[i].stats_id]; 1605 } 1606 return stat_cnt; 1607 } 1608 1609 dpaa2_xstats_get_by_id(dev, NULL, values_copy, stat_cnt); 1610 1611 for (i = 0; i < n; i++) { 1612 if (ids[i] >= stat_cnt) { 1613 DPAA2_PMD_ERR("xstats id value isn't valid"); 1614 return -1; 1615 } 1616 values[i] = values_copy[ids[i]]; 1617 } 1618 return n; 1619 } 1620 1621 static int 1622 dpaa2_xstats_get_names_by_id( 1623 struct rte_eth_dev *dev, 1624 struct rte_eth_xstat_name *xstats_names, 1625 const uint64_t *ids, 1626 unsigned int limit) 1627 { 1628 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings); 1629 struct rte_eth_xstat_name xstats_names_copy[stat_cnt]; 1630 1631 if (!ids) 1632 return dpaa2_xstats_get_names(dev, xstats_names, limit); 1633 1634 dpaa2_xstats_get_names(dev, xstats_names_copy, limit); 1635 1636 for (i = 0; i < limit; i++) { 1637 if (ids[i] >= stat_cnt) { 1638 DPAA2_PMD_ERR("xstats id value isn't valid"); 1639 return -1; 1640 } 1641 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 1642 } 1643 return limit; 1644 } 1645 1646 static int 1647 dpaa2_dev_stats_reset(struct rte_eth_dev *dev) 1648 { 1649 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1650 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1651 int retcode; 1652 int i; 1653 struct dpaa2_queue *dpaa2_q; 1654 1655 PMD_INIT_FUNC_TRACE(); 1656 1657 if (dpni == NULL) { 1658 DPAA2_PMD_ERR("dpni is NULL"); 1659 return -EINVAL; 1660 } 1661 1662 retcode = dpni_reset_statistics(dpni, CMD_PRI_LOW, priv->token); 1663 if (retcode) 1664 goto error; 1665 1666 /* Reset the per queue stats in dpaa2_queue structure */ 1667 for (i = 0; i < priv->nb_rx_queues; i++) { 1668 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i]; 1669 if (dpaa2_q) 1670 dpaa2_q->rx_pkts = 0; 1671 } 1672 1673 for (i = 0; i < priv->nb_tx_queues; i++) { 1674 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; 1675 if (dpaa2_q) 1676 dpaa2_q->tx_pkts = 0; 1677 } 1678 1679 return 0; 1680 1681 error: 1682 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode); 1683 return retcode; 1684 }; 1685 1686 /* return 0 means link status changed, -1 means not changed */ 1687 static int 1688 dpaa2_dev_link_update(struct rte_eth_dev *dev, 1689 int wait_to_complete __rte_unused) 1690 { 1691 int ret; 1692 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1693 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1694 struct rte_eth_link link; 1695 struct dpni_link_state state = {0}; 1696 1697 if (dpni == NULL) { 1698 DPAA2_PMD_ERR("dpni is NULL"); 1699 return 0; 1700 } 1701 1702 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state); 1703 if (ret < 0) { 1704 DPAA2_PMD_DEBUG("error: dpni_get_link_state %d", ret); 1705 return -1; 1706 } 1707 1708 memset(&link, 0, sizeof(struct rte_eth_link)); 1709 link.link_status = state.up; 1710 link.link_speed = state.rate; 1711 1712 if (state.options & DPNI_LINK_OPT_HALF_DUPLEX) 1713 link.link_duplex = ETH_LINK_HALF_DUPLEX; 1714 else 1715 link.link_duplex = ETH_LINK_FULL_DUPLEX; 1716 1717 ret = rte_eth_linkstatus_set(dev, &link); 1718 if (ret == -1) 1719 DPAA2_PMD_DEBUG("No change in status"); 1720 else 1721 DPAA2_PMD_INFO("Port %d Link is %s\n", dev->data->port_id, 1722 link.link_status ? "Up" : "Down"); 1723 1724 return ret; 1725 } 1726 1727 /** 1728 * Toggle the DPNI to enable, if not already enabled. 1729 * This is not strictly PHY up/down - it is more of logical toggling. 1730 */ 1731 static int 1732 dpaa2_dev_set_link_up(struct rte_eth_dev *dev) 1733 { 1734 int ret = -EINVAL; 1735 struct dpaa2_dev_priv *priv; 1736 struct fsl_mc_io *dpni; 1737 int en = 0; 1738 struct dpni_link_state state = {0}; 1739 1740 priv = dev->data->dev_private; 1741 dpni = (struct fsl_mc_io *)dev->process_private; 1742 1743 if (dpni == NULL) { 1744 DPAA2_PMD_ERR("dpni is NULL"); 1745 return ret; 1746 } 1747 1748 /* Check if DPNI is currently enabled */ 1749 ret = dpni_is_enabled(dpni, CMD_PRI_LOW, priv->token, &en); 1750 if (ret) { 1751 /* Unable to obtain dpni status; Not continuing */ 1752 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret); 1753 return -EINVAL; 1754 } 1755 1756 /* Enable link if not already enabled */ 1757 if (!en) { 1758 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token); 1759 if (ret) { 1760 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret); 1761 return -EINVAL; 1762 } 1763 } 1764 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state); 1765 if (ret < 0) { 1766 DPAA2_PMD_DEBUG("Unable to get link state (%d)", ret); 1767 return -1; 1768 } 1769 1770 /* changing tx burst function to start enqueues */ 1771 dev->tx_pkt_burst = dpaa2_dev_tx; 1772 dev->data->dev_link.link_status = state.up; 1773 dev->data->dev_link.link_speed = state.rate; 1774 1775 if (state.up) 1776 DPAA2_PMD_INFO("Port %d Link is Up", dev->data->port_id); 1777 else 1778 DPAA2_PMD_INFO("Port %d Link is Down", dev->data->port_id); 1779 return ret; 1780 } 1781 1782 /** 1783 * Toggle the DPNI to disable, if not already disabled. 1784 * This is not strictly PHY up/down - it is more of logical toggling. 1785 */ 1786 static int 1787 dpaa2_dev_set_link_down(struct rte_eth_dev *dev) 1788 { 1789 int ret = -EINVAL; 1790 struct dpaa2_dev_priv *priv; 1791 struct fsl_mc_io *dpni; 1792 int dpni_enabled = 0; 1793 int retries = 10; 1794 1795 PMD_INIT_FUNC_TRACE(); 1796 1797 priv = dev->data->dev_private; 1798 dpni = (struct fsl_mc_io *)dev->process_private; 1799 1800 if (dpni == NULL) { 1801 DPAA2_PMD_ERR("Device has not yet been configured"); 1802 return ret; 1803 } 1804 1805 /*changing tx burst function to avoid any more enqueues */ 1806 dev->tx_pkt_burst = dummy_dev_tx; 1807 1808 /* Loop while dpni_disable() attempts to drain the egress FQs 1809 * and confirm them back to us. 1810 */ 1811 do { 1812 ret = dpni_disable(dpni, 0, priv->token); 1813 if (ret) { 1814 DPAA2_PMD_ERR("dpni disable failed (%d)", ret); 1815 return ret; 1816 } 1817 ret = dpni_is_enabled(dpni, 0, priv->token, &dpni_enabled); 1818 if (ret) { 1819 DPAA2_PMD_ERR("dpni enable check failed (%d)", ret); 1820 return ret; 1821 } 1822 if (dpni_enabled) 1823 /* Allow the MC some slack */ 1824 rte_delay_us(100 * 1000); 1825 } while (dpni_enabled && --retries); 1826 1827 if (!retries) { 1828 DPAA2_PMD_WARN("Retry count exceeded disabling dpni"); 1829 /* todo- we may have to manually cleanup queues. 1830 */ 1831 } else { 1832 DPAA2_PMD_INFO("Port %d Link DOWN successful", 1833 dev->data->port_id); 1834 } 1835 1836 dev->data->dev_link.link_status = 0; 1837 1838 return ret; 1839 } 1840 1841 static int 1842 dpaa2_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 1843 { 1844 int ret = -EINVAL; 1845 struct dpaa2_dev_priv *priv; 1846 struct fsl_mc_io *dpni; 1847 struct dpni_link_state state = {0}; 1848 1849 PMD_INIT_FUNC_TRACE(); 1850 1851 priv = dev->data->dev_private; 1852 dpni = (struct fsl_mc_io *)dev->process_private; 1853 1854 if (dpni == NULL || fc_conf == NULL) { 1855 DPAA2_PMD_ERR("device not configured"); 1856 return ret; 1857 } 1858 1859 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state); 1860 if (ret) { 1861 DPAA2_PMD_ERR("error: dpni_get_link_state %d", ret); 1862 return ret; 1863 } 1864 1865 memset(fc_conf, 0, sizeof(struct rte_eth_fc_conf)); 1866 if (state.options & DPNI_LINK_OPT_PAUSE) { 1867 /* DPNI_LINK_OPT_PAUSE set 1868 * if ASYM_PAUSE not set, 1869 * RX Side flow control (handle received Pause frame) 1870 * TX side flow control (send Pause frame) 1871 * if ASYM_PAUSE set, 1872 * RX Side flow control (handle received Pause frame) 1873 * No TX side flow control (send Pause frame disabled) 1874 */ 1875 if (!(state.options & DPNI_LINK_OPT_ASYM_PAUSE)) 1876 fc_conf->mode = RTE_FC_FULL; 1877 else 1878 fc_conf->mode = RTE_FC_RX_PAUSE; 1879 } else { 1880 /* DPNI_LINK_OPT_PAUSE not set 1881 * if ASYM_PAUSE set, 1882 * TX side flow control (send Pause frame) 1883 * No RX side flow control (No action on pause frame rx) 1884 * if ASYM_PAUSE not set, 1885 * Flow control disabled 1886 */ 1887 if (state.options & DPNI_LINK_OPT_ASYM_PAUSE) 1888 fc_conf->mode = RTE_FC_TX_PAUSE; 1889 else 1890 fc_conf->mode = RTE_FC_NONE; 1891 } 1892 1893 return ret; 1894 } 1895 1896 static int 1897 dpaa2_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 1898 { 1899 int ret = -EINVAL; 1900 struct dpaa2_dev_priv *priv; 1901 struct fsl_mc_io *dpni; 1902 struct dpni_link_state state = {0}; 1903 struct dpni_link_cfg cfg = {0}; 1904 1905 PMD_INIT_FUNC_TRACE(); 1906 1907 priv = dev->data->dev_private; 1908 dpni = (struct fsl_mc_io *)dev->process_private; 1909 1910 if (dpni == NULL) { 1911 DPAA2_PMD_ERR("dpni is NULL"); 1912 return ret; 1913 } 1914 1915 /* It is necessary to obtain the current state before setting fc_conf 1916 * as MC would return error in case rate, autoneg or duplex values are 1917 * different. 1918 */ 1919 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state); 1920 if (ret) { 1921 DPAA2_PMD_ERR("Unable to get link state (err=%d)", ret); 1922 return -1; 1923 } 1924 1925 /* Disable link before setting configuration */ 1926 dpaa2_dev_set_link_down(dev); 1927 1928 /* Based on fc_conf, update cfg */ 1929 cfg.rate = state.rate; 1930 cfg.options = state.options; 1931 1932 /* update cfg with fc_conf */ 1933 switch (fc_conf->mode) { 1934 case RTE_FC_FULL: 1935 /* Full flow control; 1936 * OPT_PAUSE set, ASYM_PAUSE not set 1937 */ 1938 cfg.options |= DPNI_LINK_OPT_PAUSE; 1939 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE; 1940 break; 1941 case RTE_FC_TX_PAUSE: 1942 /* Enable RX flow control 1943 * OPT_PAUSE not set; 1944 * ASYM_PAUSE set; 1945 */ 1946 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE; 1947 cfg.options &= ~DPNI_LINK_OPT_PAUSE; 1948 break; 1949 case RTE_FC_RX_PAUSE: 1950 /* Enable TX Flow control 1951 * OPT_PAUSE set 1952 * ASYM_PAUSE set 1953 */ 1954 cfg.options |= DPNI_LINK_OPT_PAUSE; 1955 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE; 1956 break; 1957 case RTE_FC_NONE: 1958 /* Disable Flow control 1959 * OPT_PAUSE not set 1960 * ASYM_PAUSE not set 1961 */ 1962 cfg.options &= ~DPNI_LINK_OPT_PAUSE; 1963 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE; 1964 break; 1965 default: 1966 DPAA2_PMD_ERR("Incorrect Flow control flag (%d)", 1967 fc_conf->mode); 1968 return -1; 1969 } 1970 1971 ret = dpni_set_link_cfg(dpni, CMD_PRI_LOW, priv->token, &cfg); 1972 if (ret) 1973 DPAA2_PMD_ERR("Unable to set Link configuration (err=%d)", 1974 ret); 1975 1976 /* Enable link */ 1977 dpaa2_dev_set_link_up(dev); 1978 1979 return ret; 1980 } 1981 1982 static int 1983 dpaa2_dev_rss_hash_update(struct rte_eth_dev *dev, 1984 struct rte_eth_rss_conf *rss_conf) 1985 { 1986 struct rte_eth_dev_data *data = dev->data; 1987 struct rte_eth_conf *eth_conf = &data->dev_conf; 1988 int ret; 1989 1990 PMD_INIT_FUNC_TRACE(); 1991 1992 if (rss_conf->rss_hf) { 1993 ret = dpaa2_setup_flow_dist(dev, rss_conf->rss_hf); 1994 if (ret) { 1995 DPAA2_PMD_ERR("Unable to set flow dist"); 1996 return ret; 1997 } 1998 } else { 1999 ret = dpaa2_remove_flow_dist(dev, 0); 2000 if (ret) { 2001 DPAA2_PMD_ERR("Unable to remove flow dist"); 2002 return ret; 2003 } 2004 } 2005 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf; 2006 return 0; 2007 } 2008 2009 static int 2010 dpaa2_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 2011 struct rte_eth_rss_conf *rss_conf) 2012 { 2013 struct rte_eth_dev_data *data = dev->data; 2014 struct rte_eth_conf *eth_conf = &data->dev_conf; 2015 2016 /* dpaa2 does not support rss_key, so length should be 0*/ 2017 rss_conf->rss_key_len = 0; 2018 rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf; 2019 return 0; 2020 } 2021 2022 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev, 2023 int eth_rx_queue_id, 2024 struct dpaa2_dpcon_dev *dpcon, 2025 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf) 2026 { 2027 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private; 2028 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 2029 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id]; 2030 uint8_t flow_id = dpaa2_ethq->flow_id; 2031 struct dpni_queue cfg; 2032 uint8_t options, priority; 2033 int ret; 2034 2035 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_PARALLEL) 2036 dpaa2_ethq->cb = dpaa2_dev_process_parallel_event; 2037 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) 2038 dpaa2_ethq->cb = dpaa2_dev_process_atomic_event; 2039 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED) 2040 dpaa2_ethq->cb = dpaa2_dev_process_ordered_event; 2041 else 2042 return -EINVAL; 2043 2044 priority = (RTE_EVENT_DEV_PRIORITY_LOWEST / queue_conf->ev.priority) * 2045 (dpcon->num_priorities - 1); 2046 2047 memset(&cfg, 0, sizeof(struct dpni_queue)); 2048 options = DPNI_QUEUE_OPT_DEST; 2049 cfg.destination.type = DPNI_DEST_DPCON; 2050 cfg.destination.id = dpcon->dpcon_id; 2051 cfg.destination.priority = priority; 2052 2053 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) { 2054 options |= DPNI_QUEUE_OPT_HOLD_ACTIVE; 2055 cfg.destination.hold_active = 1; 2056 } 2057 2058 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED && 2059 !eth_priv->en_ordered) { 2060 struct opr_cfg ocfg; 2061 2062 /* Restoration window size = 256 frames */ 2063 ocfg.oprrws = 3; 2064 /* Restoration window size = 512 frames for LX2 */ 2065 if (dpaa2_svr_family == SVR_LX2160A) 2066 ocfg.oprrws = 4; 2067 /* Auto advance NESN window enabled */ 2068 ocfg.oa = 1; 2069 /* Late arrival window size disabled */ 2070 ocfg.olws = 0; 2071 /* ORL resource exhaustaion advance NESN disabled */ 2072 ocfg.oeane = 0; 2073 /* Loose ordering enabled */ 2074 ocfg.oloe = 1; 2075 eth_priv->en_loose_ordered = 1; 2076 /* Strict ordering enabled if explicitly set */ 2077 if (getenv("DPAA2_STRICT_ORDERING_ENABLE")) { 2078 ocfg.oloe = 0; 2079 eth_priv->en_loose_ordered = 0; 2080 } 2081 2082 ret = dpni_set_opr(dpni, CMD_PRI_LOW, eth_priv->token, 2083 dpaa2_ethq->tc_index, flow_id, 2084 OPR_OPT_CREATE, &ocfg); 2085 if (ret) { 2086 DPAA2_PMD_ERR("Error setting opr: ret: %d\n", ret); 2087 return ret; 2088 } 2089 2090 eth_priv->en_ordered = 1; 2091 } 2092 2093 options |= DPNI_QUEUE_OPT_USER_CTX; 2094 cfg.user_context = (size_t)(dpaa2_ethq); 2095 2096 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX, 2097 dpaa2_ethq->tc_index, flow_id, options, &cfg); 2098 if (ret) { 2099 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret); 2100 return ret; 2101 } 2102 2103 memcpy(&dpaa2_ethq->ev, &queue_conf->ev, sizeof(struct rte_event)); 2104 2105 return 0; 2106 } 2107 2108 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev, 2109 int eth_rx_queue_id) 2110 { 2111 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private; 2112 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 2113 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id]; 2114 uint8_t flow_id = dpaa2_ethq->flow_id; 2115 struct dpni_queue cfg; 2116 uint8_t options; 2117 int ret; 2118 2119 memset(&cfg, 0, sizeof(struct dpni_queue)); 2120 options = DPNI_QUEUE_OPT_DEST; 2121 cfg.destination.type = DPNI_DEST_NONE; 2122 2123 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX, 2124 dpaa2_ethq->tc_index, flow_id, options, &cfg); 2125 if (ret) 2126 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret); 2127 2128 return ret; 2129 } 2130 2131 static inline int 2132 dpaa2_dev_verify_filter_ops(enum rte_filter_op filter_op) 2133 { 2134 unsigned int i; 2135 2136 for (i = 0; i < RTE_DIM(dpaa2_supported_filter_ops); i++) { 2137 if (dpaa2_supported_filter_ops[i] == filter_op) 2138 return 0; 2139 } 2140 return -ENOTSUP; 2141 } 2142 2143 static int 2144 dpaa2_dev_flow_ctrl(struct rte_eth_dev *dev, 2145 enum rte_filter_type filter_type, 2146 enum rte_filter_op filter_op, 2147 void *arg) 2148 { 2149 int ret = 0; 2150 2151 if (!dev) 2152 return -ENODEV; 2153 2154 switch (filter_type) { 2155 case RTE_ETH_FILTER_GENERIC: 2156 if (dpaa2_dev_verify_filter_ops(filter_op) < 0) { 2157 ret = -ENOTSUP; 2158 break; 2159 } 2160 *(const void **)arg = &dpaa2_flow_ops; 2161 dpaa2_filter_type |= filter_type; 2162 break; 2163 default: 2164 RTE_LOG(ERR, PMD, "Filter type (%d) not supported", 2165 filter_type); 2166 ret = -ENOTSUP; 2167 break; 2168 } 2169 return ret; 2170 } 2171 2172 static struct eth_dev_ops dpaa2_ethdev_ops = { 2173 .dev_configure = dpaa2_eth_dev_configure, 2174 .dev_start = dpaa2_dev_start, 2175 .dev_stop = dpaa2_dev_stop, 2176 .dev_close = dpaa2_dev_close, 2177 .promiscuous_enable = dpaa2_dev_promiscuous_enable, 2178 .promiscuous_disable = dpaa2_dev_promiscuous_disable, 2179 .allmulticast_enable = dpaa2_dev_allmulticast_enable, 2180 .allmulticast_disable = dpaa2_dev_allmulticast_disable, 2181 .dev_set_link_up = dpaa2_dev_set_link_up, 2182 .dev_set_link_down = dpaa2_dev_set_link_down, 2183 .link_update = dpaa2_dev_link_update, 2184 .stats_get = dpaa2_dev_stats_get, 2185 .xstats_get = dpaa2_dev_xstats_get, 2186 .xstats_get_by_id = dpaa2_xstats_get_by_id, 2187 .xstats_get_names_by_id = dpaa2_xstats_get_names_by_id, 2188 .xstats_get_names = dpaa2_xstats_get_names, 2189 .stats_reset = dpaa2_dev_stats_reset, 2190 .xstats_reset = dpaa2_dev_stats_reset, 2191 .fw_version_get = dpaa2_fw_version_get, 2192 .dev_infos_get = dpaa2_dev_info_get, 2193 .dev_supported_ptypes_get = dpaa2_supported_ptypes_get, 2194 .mtu_set = dpaa2_dev_mtu_set, 2195 .vlan_filter_set = dpaa2_vlan_filter_set, 2196 .vlan_offload_set = dpaa2_vlan_offload_set, 2197 .vlan_tpid_set = dpaa2_vlan_tpid_set, 2198 .rx_queue_setup = dpaa2_dev_rx_queue_setup, 2199 .rx_queue_release = dpaa2_dev_rx_queue_release, 2200 .tx_queue_setup = dpaa2_dev_tx_queue_setup, 2201 .tx_queue_release = dpaa2_dev_tx_queue_release, 2202 .rx_queue_count = dpaa2_dev_rx_queue_count, 2203 .flow_ctrl_get = dpaa2_flow_ctrl_get, 2204 .flow_ctrl_set = dpaa2_flow_ctrl_set, 2205 .mac_addr_add = dpaa2_dev_add_mac_addr, 2206 .mac_addr_remove = dpaa2_dev_remove_mac_addr, 2207 .mac_addr_set = dpaa2_dev_set_mac_addr, 2208 .rss_hash_update = dpaa2_dev_rss_hash_update, 2209 .rss_hash_conf_get = dpaa2_dev_rss_hash_conf_get, 2210 .filter_ctrl = dpaa2_dev_flow_ctrl, 2211 #if defined(RTE_LIBRTE_IEEE1588) 2212 .timesync_enable = dpaa2_timesync_enable, 2213 .timesync_disable = dpaa2_timesync_disable, 2214 .timesync_read_time = dpaa2_timesync_read_time, 2215 .timesync_write_time = dpaa2_timesync_write_time, 2216 .timesync_adjust_time = dpaa2_timesync_adjust_time, 2217 .timesync_read_rx_timestamp = dpaa2_timesync_read_rx_timestamp, 2218 .timesync_read_tx_timestamp = dpaa2_timesync_read_tx_timestamp, 2219 #endif 2220 }; 2221 2222 /* Populate the mac address from physically available (u-boot/firmware) and/or 2223 * one set by higher layers like MC (restool) etc. 2224 * Returns the table of MAC entries (multiple entries) 2225 */ 2226 static int 2227 populate_mac_addr(struct fsl_mc_io *dpni_dev, struct dpaa2_dev_priv *priv, 2228 struct rte_ether_addr *mac_entry) 2229 { 2230 int ret; 2231 struct rte_ether_addr phy_mac, prime_mac; 2232 2233 memset(&phy_mac, 0, sizeof(struct rte_ether_addr)); 2234 memset(&prime_mac, 0, sizeof(struct rte_ether_addr)); 2235 2236 /* Get the physical device MAC address */ 2237 ret = dpni_get_port_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token, 2238 phy_mac.addr_bytes); 2239 if (ret) { 2240 DPAA2_PMD_ERR("DPNI get physical port MAC failed: %d", ret); 2241 goto cleanup; 2242 } 2243 2244 ret = dpni_get_primary_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token, 2245 prime_mac.addr_bytes); 2246 if (ret) { 2247 DPAA2_PMD_ERR("DPNI get Prime port MAC failed: %d", ret); 2248 goto cleanup; 2249 } 2250 2251 /* Now that both MAC have been obtained, do: 2252 * if not_empty_mac(phy) && phy != Prime, overwrite prime with Phy 2253 * and return phy 2254 * If empty_mac(phy), return prime. 2255 * if both are empty, create random MAC, set as prime and return 2256 */ 2257 if (!rte_is_zero_ether_addr(&phy_mac)) { 2258 /* If the addresses are not same, overwrite prime */ 2259 if (!rte_is_same_ether_addr(&phy_mac, &prime_mac)) { 2260 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW, 2261 priv->token, 2262 phy_mac.addr_bytes); 2263 if (ret) { 2264 DPAA2_PMD_ERR("Unable to set MAC Address: %d", 2265 ret); 2266 goto cleanup; 2267 } 2268 memcpy(&prime_mac, &phy_mac, 2269 sizeof(struct rte_ether_addr)); 2270 } 2271 } else if (rte_is_zero_ether_addr(&prime_mac)) { 2272 /* In case phys and prime, both are zero, create random MAC */ 2273 rte_eth_random_addr(prime_mac.addr_bytes); 2274 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW, 2275 priv->token, 2276 prime_mac.addr_bytes); 2277 if (ret) { 2278 DPAA2_PMD_ERR("Unable to set MAC Address: %d", ret); 2279 goto cleanup; 2280 } 2281 } 2282 2283 /* prime_mac the final MAC address */ 2284 memcpy(mac_entry, &prime_mac, sizeof(struct rte_ether_addr)); 2285 return 0; 2286 2287 cleanup: 2288 return -1; 2289 } 2290 2291 static int 2292 check_devargs_handler(__rte_unused const char *key, const char *value, 2293 __rte_unused void *opaque) 2294 { 2295 if (strcmp(value, "1")) 2296 return -1; 2297 2298 return 0; 2299 } 2300 2301 static int 2302 dpaa2_get_devargs(struct rte_devargs *devargs, const char *key) 2303 { 2304 struct rte_kvargs *kvlist; 2305 2306 if (!devargs) 2307 return 0; 2308 2309 kvlist = rte_kvargs_parse(devargs->args, NULL); 2310 if (!kvlist) 2311 return 0; 2312 2313 if (!rte_kvargs_count(kvlist, key)) { 2314 rte_kvargs_free(kvlist); 2315 return 0; 2316 } 2317 2318 if (rte_kvargs_process(kvlist, key, 2319 check_devargs_handler, NULL) < 0) { 2320 rte_kvargs_free(kvlist); 2321 return 0; 2322 } 2323 rte_kvargs_free(kvlist); 2324 2325 return 1; 2326 } 2327 2328 static int 2329 dpaa2_dev_init(struct rte_eth_dev *eth_dev) 2330 { 2331 struct rte_device *dev = eth_dev->device; 2332 struct rte_dpaa2_device *dpaa2_dev; 2333 struct fsl_mc_io *dpni_dev; 2334 struct dpni_attr attr; 2335 struct dpaa2_dev_priv *priv = eth_dev->data->dev_private; 2336 struct dpni_buffer_layout layout; 2337 int ret, hw_id, i; 2338 2339 PMD_INIT_FUNC_TRACE(); 2340 2341 dpni_dev = rte_malloc(NULL, sizeof(struct fsl_mc_io), 0); 2342 if (!dpni_dev) { 2343 DPAA2_PMD_ERR("Memory allocation failed for dpni device"); 2344 return -1; 2345 } 2346 dpni_dev->regs = rte_mcp_ptr_list[0]; 2347 eth_dev->process_private = (void *)dpni_dev; 2348 2349 /* For secondary processes, the primary has done all the work */ 2350 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2351 /* In case of secondary, only burst and ops API need to be 2352 * plugged. 2353 */ 2354 eth_dev->dev_ops = &dpaa2_ethdev_ops; 2355 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) 2356 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx; 2357 else if (dpaa2_get_devargs(dev->devargs, 2358 DRIVER_NO_PREFETCH_MODE)) 2359 eth_dev->rx_pkt_burst = dpaa2_dev_rx; 2360 else 2361 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx; 2362 eth_dev->tx_pkt_burst = dpaa2_dev_tx; 2363 return 0; 2364 } 2365 2366 dpaa2_dev = container_of(dev, struct rte_dpaa2_device, device); 2367 2368 hw_id = dpaa2_dev->object_id; 2369 ret = dpni_open(dpni_dev, CMD_PRI_LOW, hw_id, &priv->token); 2370 if (ret) { 2371 DPAA2_PMD_ERR( 2372 "Failure in opening dpni@%d with err code %d", 2373 hw_id, ret); 2374 rte_free(dpni_dev); 2375 return -1; 2376 } 2377 2378 /* Clean the device first */ 2379 ret = dpni_reset(dpni_dev, CMD_PRI_LOW, priv->token); 2380 if (ret) { 2381 DPAA2_PMD_ERR("Failure cleaning dpni@%d with err code %d", 2382 hw_id, ret); 2383 goto init_err; 2384 } 2385 2386 ret = dpni_get_attributes(dpni_dev, CMD_PRI_LOW, priv->token, &attr); 2387 if (ret) { 2388 DPAA2_PMD_ERR( 2389 "Failure in get dpni@%d attribute, err code %d", 2390 hw_id, ret); 2391 goto init_err; 2392 } 2393 2394 priv->num_rx_tc = attr.num_rx_tcs; 2395 /* only if the custom CG is enabled */ 2396 if (attr.options & DPNI_OPT_CUSTOM_CG) 2397 priv->max_cgs = attr.num_cgs; 2398 else 2399 priv->max_cgs = 0; 2400 2401 for (i = 0; i < priv->max_cgs; i++) 2402 priv->cgid_in_use[i] = 0; 2403 2404 for (i = 0; i < attr.num_rx_tcs; i++) 2405 priv->nb_rx_queues += attr.num_queues; 2406 2407 /* Using number of TX queues as number of TX TCs */ 2408 priv->nb_tx_queues = attr.num_tx_tcs; 2409 2410 DPAA2_PMD_DEBUG("RX-TC= %d, rx_queues= %d, tx_queues=%d, max_cgs=%d", 2411 priv->num_rx_tc, priv->nb_rx_queues, 2412 priv->nb_tx_queues, priv->max_cgs); 2413 2414 priv->hw = dpni_dev; 2415 priv->hw_id = hw_id; 2416 priv->options = attr.options; 2417 priv->max_mac_filters = attr.mac_filter_entries; 2418 priv->max_vlan_filters = attr.vlan_filter_entries; 2419 priv->flags = 0; 2420 #if defined(RTE_LIBRTE_IEEE1588) 2421 priv->tx_conf_en = 1; 2422 #else 2423 priv->tx_conf_en = 0; 2424 #endif 2425 2426 /* Allocate memory for hardware structure for queues */ 2427 ret = dpaa2_alloc_rx_tx_queues(eth_dev); 2428 if (ret) { 2429 DPAA2_PMD_ERR("Queue allocation Failed"); 2430 goto init_err; 2431 } 2432 2433 /* Allocate memory for storing MAC addresses. 2434 * Table of mac_filter_entries size is allocated so that RTE ether lib 2435 * can add MAC entries when rte_eth_dev_mac_addr_add is called. 2436 */ 2437 eth_dev->data->mac_addrs = rte_zmalloc("dpni", 2438 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries, 0); 2439 if (eth_dev->data->mac_addrs == NULL) { 2440 DPAA2_PMD_ERR( 2441 "Failed to allocate %d bytes needed to store MAC addresses", 2442 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries); 2443 ret = -ENOMEM; 2444 goto init_err; 2445 } 2446 2447 ret = populate_mac_addr(dpni_dev, priv, ð_dev->data->mac_addrs[0]); 2448 if (ret) { 2449 DPAA2_PMD_ERR("Unable to fetch MAC Address for device"); 2450 rte_free(eth_dev->data->mac_addrs); 2451 eth_dev->data->mac_addrs = NULL; 2452 goto init_err; 2453 } 2454 2455 /* ... tx buffer layout ... */ 2456 memset(&layout, 0, sizeof(struct dpni_buffer_layout)); 2457 if (priv->tx_conf_en) { 2458 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS | 2459 DPNI_BUF_LAYOUT_OPT_TIMESTAMP; 2460 layout.pass_timestamp = true; 2461 } else { 2462 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS; 2463 } 2464 layout.pass_frame_status = 1; 2465 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token, 2466 DPNI_QUEUE_TX, &layout); 2467 if (ret) { 2468 DPAA2_PMD_ERR("Error (%d) in setting tx buffer layout", ret); 2469 goto init_err; 2470 } 2471 2472 /* ... tx-conf and error buffer layout ... */ 2473 memset(&layout, 0, sizeof(struct dpni_buffer_layout)); 2474 if (priv->tx_conf_en) { 2475 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS | 2476 DPNI_BUF_LAYOUT_OPT_TIMESTAMP; 2477 layout.pass_timestamp = true; 2478 } else { 2479 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS; 2480 } 2481 layout.pass_frame_status = 1; 2482 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token, 2483 DPNI_QUEUE_TX_CONFIRM, &layout); 2484 if (ret) { 2485 DPAA2_PMD_ERR("Error (%d) in setting tx-conf buffer layout", 2486 ret); 2487 goto init_err; 2488 } 2489 2490 eth_dev->dev_ops = &dpaa2_ethdev_ops; 2491 2492 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) { 2493 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx; 2494 DPAA2_PMD_INFO("Loopback mode"); 2495 } else if (dpaa2_get_devargs(dev->devargs, DRIVER_NO_PREFETCH_MODE)) { 2496 eth_dev->rx_pkt_burst = dpaa2_dev_rx; 2497 DPAA2_PMD_INFO("No Prefetch mode"); 2498 } else { 2499 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx; 2500 } 2501 eth_dev->tx_pkt_burst = dpaa2_dev_tx; 2502 2503 /*Init fields w.r.t. classficaition*/ 2504 memset(&priv->extract.qos_key_cfg, 0, sizeof(struct dpkg_profile_cfg)); 2505 priv->extract.qos_extract_param = (size_t)rte_malloc(NULL, 256, 64); 2506 if (!priv->extract.qos_extract_param) { 2507 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow " 2508 " classificaiton ", ret); 2509 goto init_err; 2510 } 2511 for (i = 0; i < MAX_TCS; i++) { 2512 memset(&priv->extract.fs_key_cfg[i], 0, 2513 sizeof(struct dpkg_profile_cfg)); 2514 priv->extract.fs_extract_param[i] = 2515 (size_t)rte_malloc(NULL, 256, 64); 2516 if (!priv->extract.fs_extract_param[i]) { 2517 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow classificaiton", 2518 ret); 2519 goto init_err; 2520 } 2521 } 2522 2523 ret = dpni_set_max_frame_length(dpni_dev, CMD_PRI_LOW, priv->token, 2524 RTE_ETHER_MAX_LEN - RTE_ETHER_CRC_LEN 2525 + VLAN_TAG_SIZE); 2526 if (ret) { 2527 DPAA2_PMD_ERR("Unable to set mtu. check config"); 2528 goto init_err; 2529 } 2530 2531 /*TODO To enable soft parser support DPAA2 driver needs to integrate 2532 * with external entity to receive byte code for software sequence 2533 * and same will be offload to the H/W using MC interface. 2534 * Currently it is assumed that DPAA2 driver has byte code by some 2535 * mean and same if offloaded to H/W. 2536 */ 2537 if (getenv("DPAA2_ENABLE_SOFT_PARSER")) { 2538 WRIOP_SS_INITIALIZER(priv); 2539 ret = dpaa2_eth_load_wriop_soft_parser(priv, DPNI_SS_INGRESS); 2540 if (ret < 0) { 2541 DPAA2_PMD_ERR(" Error(%d) in loading softparser\n", 2542 ret); 2543 return ret; 2544 } 2545 2546 ret = dpaa2_eth_enable_wriop_soft_parser(priv, 2547 DPNI_SS_INGRESS); 2548 if (ret < 0) { 2549 DPAA2_PMD_ERR(" Error(%d) in enabling softparser\n", 2550 ret); 2551 return ret; 2552 } 2553 } 2554 RTE_LOG(INFO, PMD, "%s: netdev created\n", eth_dev->data->name); 2555 return 0; 2556 init_err: 2557 dpaa2_dev_uninit(eth_dev); 2558 return ret; 2559 } 2560 2561 static int 2562 dpaa2_dev_uninit(struct rte_eth_dev *eth_dev) 2563 { 2564 struct dpaa2_dev_priv *priv = eth_dev->data->dev_private; 2565 struct fsl_mc_io *dpni = (struct fsl_mc_io *)eth_dev->process_private; 2566 int i, ret; 2567 2568 PMD_INIT_FUNC_TRACE(); 2569 2570 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2571 return 0; 2572 2573 if (!dpni) { 2574 DPAA2_PMD_WARN("Already closed or not started"); 2575 return -1; 2576 } 2577 2578 dpaa2_dev_close(eth_dev); 2579 2580 dpaa2_free_rx_tx_queues(eth_dev); 2581 2582 /* Close the device at underlying layer*/ 2583 ret = dpni_close(dpni, CMD_PRI_LOW, priv->token); 2584 if (ret) { 2585 DPAA2_PMD_ERR( 2586 "Failure closing dpni device with err code %d", 2587 ret); 2588 } 2589 2590 /* Free the allocated memory for ethernet private data and dpni*/ 2591 priv->hw = NULL; 2592 eth_dev->process_private = NULL; 2593 rte_free(dpni); 2594 2595 for (i = 0; i < MAX_TCS; i++) { 2596 if (priv->extract.fs_extract_param[i]) 2597 rte_free((void *)(size_t)priv->extract.fs_extract_param[i]); 2598 } 2599 2600 if (priv->extract.qos_extract_param) 2601 rte_free((void *)(size_t)priv->extract.qos_extract_param); 2602 2603 eth_dev->dev_ops = NULL; 2604 eth_dev->rx_pkt_burst = NULL; 2605 eth_dev->tx_pkt_burst = NULL; 2606 2607 DPAA2_PMD_INFO("%s: netdev deleted", eth_dev->data->name); 2608 return 0; 2609 } 2610 2611 static int 2612 rte_dpaa2_probe(struct rte_dpaa2_driver *dpaa2_drv, 2613 struct rte_dpaa2_device *dpaa2_dev) 2614 { 2615 struct rte_eth_dev *eth_dev; 2616 struct dpaa2_dev_priv *dev_priv; 2617 int diag; 2618 2619 if ((DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) > 2620 RTE_PKTMBUF_HEADROOM) { 2621 DPAA2_PMD_ERR( 2622 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA2 Annotation req(%d)", 2623 RTE_PKTMBUF_HEADROOM, 2624 DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE); 2625 2626 return -1; 2627 } 2628 2629 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 2630 eth_dev = rte_eth_dev_allocate(dpaa2_dev->device.name); 2631 if (!eth_dev) 2632 return -ENODEV; 2633 dev_priv = rte_zmalloc("ethdev private structure", 2634 sizeof(struct dpaa2_dev_priv), 2635 RTE_CACHE_LINE_SIZE); 2636 if (dev_priv == NULL) { 2637 DPAA2_PMD_CRIT( 2638 "Unable to allocate memory for private data"); 2639 rte_eth_dev_release_port(eth_dev); 2640 return -ENOMEM; 2641 } 2642 eth_dev->data->dev_private = (void *)dev_priv; 2643 /* Store a pointer to eth_dev in dev_private */ 2644 dev_priv->eth_dev = eth_dev; 2645 dev_priv->tx_conf_en = 0; 2646 } else { 2647 eth_dev = rte_eth_dev_attach_secondary(dpaa2_dev->device.name); 2648 if (!eth_dev) { 2649 DPAA2_PMD_DEBUG("returning enodev"); 2650 return -ENODEV; 2651 } 2652 } 2653 2654 eth_dev->device = &dpaa2_dev->device; 2655 2656 dpaa2_dev->eth_dev = eth_dev; 2657 eth_dev->data->rx_mbuf_alloc_failed = 0; 2658 2659 if (dpaa2_drv->drv_flags & RTE_DPAA2_DRV_INTR_LSC) 2660 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC; 2661 2662 /* Invoke PMD device initialization function */ 2663 diag = dpaa2_dev_init(eth_dev); 2664 if (diag == 0) { 2665 rte_eth_dev_probing_finish(eth_dev); 2666 return 0; 2667 } 2668 2669 rte_eth_dev_release_port(eth_dev); 2670 return diag; 2671 } 2672 2673 static int 2674 rte_dpaa2_remove(struct rte_dpaa2_device *dpaa2_dev) 2675 { 2676 struct rte_eth_dev *eth_dev; 2677 2678 eth_dev = dpaa2_dev->eth_dev; 2679 dpaa2_dev_uninit(eth_dev); 2680 2681 rte_eth_dev_release_port(eth_dev); 2682 2683 return 0; 2684 } 2685 2686 static struct rte_dpaa2_driver rte_dpaa2_pmd = { 2687 .drv_flags = RTE_DPAA2_DRV_INTR_LSC | RTE_DPAA2_DRV_IOVA_AS_VA, 2688 .drv_type = DPAA2_ETH, 2689 .probe = rte_dpaa2_probe, 2690 .remove = rte_dpaa2_remove, 2691 }; 2692 2693 RTE_PMD_REGISTER_DPAA2(net_dpaa2, rte_dpaa2_pmd); 2694 RTE_PMD_REGISTER_PARAM_STRING(net_dpaa2, 2695 DRIVER_LOOPBACK_MODE "=<int> " 2696 DRIVER_NO_PREFETCH_MODE "=<int>"); 2697 RTE_INIT(dpaa2_pmd_init_log) 2698 { 2699 dpaa2_logtype_pmd = rte_log_register("pmd.net.dpaa2"); 2700 if (dpaa2_logtype_pmd >= 0) 2701 rte_log_set_level(dpaa2_logtype_pmd, RTE_LOG_NOTICE); 2702 } 2703